International Journal of Application or Innovation in Engineering & Management (IJAIEM)
Web Site: www.ijaiem.org Email: editor@ijaiem.org
Volume 3, Issue 6, June 2014
ISSN 2319 - 4847
Improving Performance Metrics of CMP using
Configuration Unit design
Mr. Mohammed Haris1, Mrs. Kavitha.V2
1
M.Tech [VLSI Design and Embedded Systems], CMR Institute of Technology,
Bangalore, Karnataka, India
2
Ph.D Scholar, Jain University, Associate Professor, Dept. of ECE, CMR Institute of Technology,
Bangalore, Karnataka, India
Abstract
In this paper, two configuration unit designs have been designed with multiple RFUs where these RFUs are the functional units
of conventional processors or ASIPs, but with a major difference that these RFUs are reconfigurable. Multiple RFUs have been
incorporated in different numbers in each design where each RFU is bound to perform some computations. Two designs have
been synthesized and simulated and results are evaluated. Where performance is a criterion there slight area and delay
constraints are negotiable. More number of RFUs has been used so that the computations are performed at a higher rate. Lesser
RFUs can lead to delay in instruction execution. Each unit is capable of performing different operations at different time as it is a
reconfigurable unit. Reconfigurability is very important as we cannot afford a specialized hardware all the time for certain
computations.
Keywords: Reconfigurable Functional Units, RISPs, Reconfigurable Logic, Reconfigurable Computing.
1. Introduction
The reconfigurable processors are commonly known as Reconfigurable Instruction Set Processor (RISP) that consist a
microprocessor core with an extended reconfigurable logic. It consists of reconfigurable functional units. The processor is
adapted by these reconfigurable configuration units for a certain application while processor core provides software
programmability. The RISPs execute the instruction just as normal processors and ASIPs though the main difference is
that the instruction set is divided into two sets: first is the fixed instruction set which is implemented in fixed hardware
and second is the reconfigurable instruction set which is implemented in reconfigurable logic and can be altered in any
manner during execution of the program.
The reconfigurable instruction set has the ability to be modified after the manufacture of the processor. In some
applications the RISP are the processors of choice. Evolving standards, unknown applications and broad diversity of
algorithms are cases where fixed solution or hardware will eventually fail to deliver the required performance. RISPs offer
the flexibility that ASIPs lack. RISPs are the prominent platforms for variety of complex computations.
In this paper, a reconfigurable instruction set processor having an efficient configuration unit design has been proposed
which can utilize the RFUs (Reconfigurable Functional Units) very efficiently and compute the instructions.
2. Related Work
Many number of different reconfigurable hardware based architectures have been proposed till now. Previously proposed
reconfigurable processor architectures generally fit into one of two categories depending on size of the computations they
map onto the reconfigurable logic. The two types are Fine-grained and Coarse-grained Reconfigurable Processors. Finegrained Reconfigurable Processors, such as PRISC, OneChip and CHIMERAE integrate the small blocks of
reconfigurable logic into superscalar processor architectures, treating the reconfigurable logic as programmable ALUs
that can be configured to implement application-specific instructions. These systems can achieve better performance than
conventional superscalar processors on a wide range of applications by mapping commonly-executed sequences of
instructions onto their reconfigurable units, but the maximum speedup they can achieve is limited by the small amount of
logic in their reconfigurable units.
2.1 Trend toward Reconfigurable Processors
The designers of today’s digital electronic systems face a fundamental trade-off between flexibility and performance when
they select the computing elements. The available alternatives span a wide spectrum with the general-purpose (GP)
processors and the application-specific integrated circuits (ASICs) at opposite ends. General Purpose processors are used
in personal computers, workstations, servers, as building blocks for most contemporary supercomputers and
increasingly in embedded systems. General Purpose processors are flexible due to their versatile instruction sets that
allow the implementation of any computable task. On the other hand ASICs are dedicated hardware devices that are tuned
to a very small number of applications or even to just one task. They are mainly used in high volume embedded system
Volume 3, Issue 6, June 2014
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International Journal of Application or Innovation in Engineering & Management (IJAIEM)
Web Site: www.ijaiem.org Email: editor@ijaiem.org
Volume 3, Issue 6, June 2014
ISSN 2319 - 4847
markets such as telecommunications, consumer electronics and the automotive industry. For a given task, dedicated
architectures execute faster, require less silicon area, and are less power hungry than general purpose architectures. The
main drawback of specialized architectures is their lack of flexibility. If the application changes a new ASIC must be
developed.
3. Reconfigurable Instruction Set Processors
Today embedded systems are composed of many hardware and software components that interact with each other. The
balance between these components will be the key for success of a system. Due to the nature of the software, software
components are a bit easier to modify than the hardware components. Thanks to this flexibility, software components
running on programmable processors provide an easier way to eliminate the bugs, to change the applications, to reuse the
components, to differentiate a product or products, or to reduce the very more important time to market. However, when
compared to hardware solutions, software components are much slower and consume more power. Hardware components
are used when speed and power consumption are critical. Unfortunately hardware components require a lengthy and
expensive design process. Additionally typical hardware components cannot be further modified after they have been
manufactured. The task of the system designer is to find an adequate balance between these components which interact
very closely.
A reconfigurable instruction set processor (RISP) consists of a microprocessor core that has been extended with
reconfigurable logic. It is similar to an ASIP but instead of specialized functional units, it contains reconfigurable
functional units. The reconfigurable functional units provide the adaptation of the processor to the application, while the
processor core provides software programmability.
4. Existing Methods
In previous papers, many different designs related to reconfigurable processors have been proposed where architectures
vary and have different optimizations in power, performance, area and delay parameters. More and more advanced
concepts have been introduced in order to enhance the performance of reconfigurable processors. In the upcoming section
we have the proposed design where we have two designs with different number of multiple RFUs where performance is a
criterion. Designs with different numbers of RFUs have been designed and have proved that an additional RFU can
increase performance with a slight increase in area and delay which doesn’t make much difference while considering
performance.
5. Proposed Design
A configuration unit design i.e. a reconfigurable processor with multiple RFUs is designed where the functional units in
the core are reconfigurable and can be reconfigured by op-codes according to the demands of the running applications.
They have been tightly coupled with integrated field programmable gate array (FPGA) cores. Two configuration unit
designs have been designed where one design has 9 RFUs and the other has 8 RFUs.
Two configuration unit designs have been designed which are in figure 5.2 and figure 5.4 with multiple RFUs which are
reconfigured every time with respect to change in op-codes to perform a particular operation. Each RFU is capable of
performing different computations at different times.
Figure 5.1 Configuration Unit Interfaces with 9 RFUs [1]
Figure 5.2 Configuration Unit Design with 9 RFUs [1]
The working of the configuration unit is very crucial. It can compute many operations with multiple RFUs where each
RFU is assigned an instruction or holds an instruction to be performed. Each RFU will perform some operation depending
Volume 3, Issue 6, June 2014
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International Journal of Application or Innovation in Engineering & Management (IJAIEM)
Web Site: www.ijaiem.org Email: editor@ijaiem.org
Volume 3, Issue 6, June 2014
ISSN 2319 - 4847
upon the op-codes given. Here the op-codes play a wide role that have the ability to reconfigure the RFUs and can change
the functionality of an RFU. Each RFU will perform a specific operation that has to be performed which purely depends
on the op-codes given.
Figure 5.3 Configuration Unit Interfaces with 8 RFUs [1]
Figure 5.4 Configuration Unit Design with 8 RFUs [1]
6. Result
The Simulation results of the proposed designs are implemented using Verilog Hardware Description Language on Xilinx
ISE. Simulation results are obtained for both the configuration unit design using Modelsim which are shown below in the
figure 6.1 and 6.2 respectively
Figure 6.1 shows the Simulation result of configuration unit design with 9RFUs where 9RFUs are performing 9 different
operations at different cycles. Figure 6.2 shows the result where 8RFUs are performing 8 different operations.
Figure 6.1 Simulation result of configuration unit design with 9RFUs
Figure 6.2 Simulation result of configuration unit design with 8RFUs
Volume 3, Issue 6, June 2014
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International Journal of Application or Innovation in Engineering & Management (IJAIEM)
Web Site: www.ijaiem.org Email: editor@ijaiem.org
Volume 3, Issue 6, June 2014
ISSN 2319 - 4847
The two configuration unit designs have been designed and simulated and a comparison has been done on both the
designs depending upon various parameters.
Figure 6.3 Bar Chart representation of Device utility
Figure 6.4 Bar Chart representation of Timing utility
Figure 6.3 and figure 6.4 show the device utility and timing utility bar chart respectively. Here various parameters are of a
slight difference which clearly states that an increase in 1 number of RFU doesn’t make much difference when
performance is considered mainly.
7. Conclusion
Here two configuration unit designs with multiple RFUs have been designed and implemented. These configuration unit
designs include multiple RFUs which are reconfigurable and perform several tasks. These RFUs are reconfigured by opcodes. This design can compute various complex computations and wide algorithms in future. Here two designs with
different number of RFUs have been designed and have analyzed the difference. We can use any of the design depending
upon the requirements. RISPs are prominent platforms which can be used as an alternative. RISP design is not an easy
task. The design of the reconfigurable logic is bound to be completely different from the standard FPGAs.
References
[1] M. Aqeel Iqbal and Shoab Ahmed Khan, “Performance Enhancements in Reconfigurable Instruction Set Processors
Using Tightly Coupled Configuration Units”, Middle-East Journal of Scientific Research 15 (7): 998-1004, 2013.
[2] Von rolf enzler and Marco platzner, “Dynamically Reconfigurable Processors”, researcher at the electronics lab,
ETH zurich, with the main interest in reconfigurable computing, 1997.
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International Journal of Application or Innovation in Engineering & Management (IJAIEM)
Web Site: www.ijaiem.org Email: editor@ijaiem.org
Volume 3, Issue 6, June 2014
ISSN 2319 - 4847
[3] Francisco Barat, Student Member, IEEE, Rudy Lauwereins, Senior Member, IEEE, and Geert Deconinck, Senior
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[9] Aqeel Iqbal. M., Uzma Saeed Awan and Shoab A. Khan, 2010. “Reconfigurable computing technology used for
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AUTHORS
Mr. Mohammed Haris is currently pursuing his M.Tech in VLSI Design and Embedded System in CMR Institute of
Technology and he is in the final semester of his course. His interests lie in System-on-chip, Reconfigurable Computing
and Wireless Communication. He continues his research in these areas. He has received the B.E degree in Electronics and
Communication Engineering from BGS Institute of Technology in the year 2012.
Mrs. Kavitha.V is currently working in CMR Institute of Technology as an Associate Professor in the Department of
Electronics and Communication and is a Ph.D Scholar from Jain University. Her interest lies in the field of
communication and low power applications. Currently she is doing her research work in low power applications.
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