International Journal of Application or Innovation in Engineering & Management (IJAIEM)
Web Site: www.ijaiem.org Email: editor@ijaiem.org, editorijaiem@gmail.com
Volume 2, Issue 11, November 2013
ISSN 2319 - 4847
COMPARISION OF FLOATING GATE &
PSEUDO FLOATING GATE TECHNIQUES
K.Ramesh1, Srimanta Kumar Dash 2 and Gayatri Devi3
1,2
Asst. prof, Dept. of ETC ,ABIT, Cuttack-14
3
Prof, Dept. of CSE ,ABIT, Cuttack-14
ABSTRACT
The pseudo floating gates can compute multiple valued signals. The main operation of pseudo floating gate is bidirectional
property by control signals.
Keywords: Floating Gate, Pseudo Floating gate.
1. INTRODUCTION
Floating gate is a normal MOS transistor except that the gate terminal is electrically isolated & has no DC path to a fix
potential. The gate is completely surrounded by SiO2, a high quality insulator that prevents charge stored on the floating
gate from leaking. In most cases using a standard CMOS process, a small leakage often exists. This leakage is crucial for
modern process. For 0.35nm process with an oxide thickness less than 70A0, reprogramming may be necessary.
As their programming & initializing makes slight use of some complex techniques, there can be structures involving
direct coupling to the floating gate. Pseudo floating gate is constantly being recharged either by a forced leakage or by a
constant feedback. Frequent recharging may require additional elements, thus adding some unwanted side effects such as
leakage.
To exploit the floating gate computational property, the implementation multiple values of logic or functions are
essential.
In reference [2, 3, 5] the Multiple Valued logic is based on signal processing that is carried out using multiples of logic
levels and Thresholds.
Multiple valued logic circuits are to reduce signal lines on the chip effectively due to increase of information per line. The
most of the designs have been current mode circuits due to the difficulties inherent in adding up signals in the voltage
mode and the need for additional fabrication steps/masks. The voltage mode CMOS circuits within multiple-valued logic
have encountered to constructs and realized a device that can distinguish the logical levels .The multiple valued design
consume less area and are faster.
2. A VOLTAGE MODE MULTIPLE VALUED FLOATING GATE INVERTER
The Capacitive divider function of the floating gate is used to weight the input signal and the floating gate potential
would determine the output. For this case of multiple valued signals processing the inverter is made analogue. The
feedback capacitor Cf can be obtained a certain gain for multi input analogue floating gate inverter. The gain should be 1
by adjusting the Cf/Ci ratio. The output satisfying Vout = Vdd – Vin.
3. PSEUDO FLOATING GATE (PFG):
The pseudo floating gates are recharged by either a forced leakage or by a constant feedback in Ref [4,6].The main
difference is the use of a feedback ‘buffer’ instead of a recharge switch & thus eliminating the recharge clocks & periods.
The pseudo floating gates can compute multiple valued signals. The main operation of pseudo floating gate as
bidirectional property by control signals.
Volume 2, Issue 11, November 2013
Page 25
International Journal of Application or Innovation in Engineering & Management (IJAIEM)
Web Site: www.ijaiem.org Email: editor@ijaiem.org, editorijaiem@gmail.com
Volume 2, Issue 11, November 2013
ISSN 2319 - 4847
4. SIMULATION MODEL FOR PFG MOS TRANSISTORS:
Vicm = (c1 v1 + c2 v2 +………+ cn vn + Q o) / (co + c1 + c2 + ……… + cn)
VPFG = w1 vicm + w2 vb
:
Where,
Qo = initial charge on FG during fabrication
Vicm = Internal Common Mode Voltage
Vb = Biasing Voltage
The multiple input pseudo floating gate MOS transistor is a pseudo floating gate transistor with multiple control gate.Vi is
voltage of the control gate ‘n’ input control gates are capacitively coupled to the pseudo floating gate.If we do not
consider week feedback buffer the physical structure of the pseudo floating gate transistor is the same with floating gate
transistor.
5. % VOLTAGE CHARACTERISTICS OF PFG MOS TRANSISTOR
Vb=0:0.5:5;
Vicm=-5:0.5:0;
w1=0:0.1:1;
w2=0:0.1:1;
y1=Vicm.*w1
subplot(221);
plot(w1,y1,'r');
Xlabel ('w1 variable in x-axis');
Ylabel ('y1 voltage in y-axis');
Title('Generation of characteristics');
Grid;
y2=Vb1.*w2;
subplot(222);
plot(w2,y2,'g');
Xlabel ('w2 variable in x-axis');
Ylabel ('y2 voltage in y-axis');
Title('Generation of charactristics');
Grid;
w=0:0.1:1;
y=y1+y2;
subplot(223);
plot(w,y,'r');
Xlabel ('w variable in x-axis');
Ylabel ('Vgs voltage in y-axis');
Title('Generation of charactristics');
Grid;
Vt=0.5;
Ko=5;
Ids=Ko.*(y-Vt).^2;
subplot(224);
plot(y,Ids,'r');
Grid;
Xlabel ('Vgs voltage in x-axis');
Ylabel ('Ids current in y-axis in mA');
Title('Generation of transfer charactristics'
Volume 2, Issue 11, November 2013
Page 26
International Journal of Application or Innovation in Engineering & Management (IJAIEM)
Web Site: www.ijaiem.org Email: editor@ijaiem.org, editorijaiem@gmail.com
Volume 2, Issue 11, November 2013
ISSN 2319 - 4847
6. CONCLUSION:
1. Now a day, its application to neural network is a great challenge to the fabrication of pseudo floating gate.
2. Multi pseudo floating gates can be used in circuit to reduce the multi signal path. This work is going on & it will be
published very soon.
References
[1.] G. Devi, et. al, “Analog multi input floating gate inverter with pseudoneuromos” in I J A CSA VOL.3, NO-5 may
2012.
[2.] Omid mirmotahari, et. al ,“Pseudo floating gate & reverse signal flow”. Recent Advances in Technologies book
published NOV-1.2009.
[3.] R.Jensen & Y.Berg (2007), “Dual data rate cyclic d/converter using semi floating gate devices”, 2007.
[4.] O.Mirmotahari, Y.Berg (2003), “A Novel Multiple input Multiple Valued Semi floating Gate Latch”, IEEE May
2003(ISMVL) 227-231.
[5.] K.C. Smith, “Multiple-valued logic: a tutorial and appreciation”, IEEE Computer, 21: 17-27 April 1998.
[6.] O Rouse diet Buisson, G. Moring. F. Paillardet and E. Mazaleyrat, “A new characterization method for accurate
capacitor matching measurements using pseudo-floating gate test structures in submicron CMOS and BICMOS
technologies”. In International conference on microelectronic test structures (ICMTS), 223-227, 1998.
AUTHOR
K.Ramesh is continuing Ph.D. His research activities and interest include VLSI realization of Analogue
integrated circuit, Communication System. K. Ramesh received the engineering degree from OUAT and
currently, working as Asst. Prof. , Dept. of ENTC, ABIT , Cuttack-14 , Odisha.
Srimanta Kumar Dash is continuing Ph.D. His research activities and interest include VLSI realization of
Analogue integrated circuit , Radar Technology and systems. Srimanta Kumar Dash received the engineering
degree from MSRIT, Bangalore and currently , working as Asst. Prof. , Dept. of ENTC, ABIT , Cuttack-14 ,
Odisha.
Dr Gayatri Devi heads the PG Dept. of CSE at ABIT Cuttack-14, Odisha. Her current field of interest in MOS
integrated circuits and system & application of Neural Network. G. Devi received PG degree in Mathematics
from Utkal University and engineering degree (B.Tech in ENTC & M. Tech in CSE) and Ph.D from Utakal
University, Odisha. She is a member of IEEE , Odisha Information Tech. of society and Odisha Mathematical society.
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