International Journal of Application or Innovation in Engineering & Management (IJAIEM)
Web Site: www.ijaiem.org Email: editor@ijaiem.org, editorijaiem@gmail.com
Volume 2, Issue 10, October 2013
ISSN 2319 - 4847
Real Time Fast Algorithm of 2D DWT Based
DSP Technology
Ghazi Ibrahem Raho 1, Ali Jbaeer Dawood 2 and Muzhir Shaban Al-Ani 3
1
Amman Arab University – Computer Information Systems Department
2&3
Al-Anbar University – College of Computer Science
Abstract
Two Dimensional Discrete Wavelet Transform (2D-DWT) algorithms play an important part in our life including the huge growth
of their applications in image and video compression. In addition, to work at real time signal processing, we need to reduce
number of operations as possible and to speed up the processing rate. These specifications are implemented via the merging and
integrated of hardware and software environments in the overall system. This system is implemented via the combination of
hardware and software components using real time processing. The implemented system demonstrates an accurate, fast, flexible
and real time processing system.
Keywords: 2D-DSP, Real Time Algorithms, 2D-DWT, and Image Compression.
1. INTRODUCTION
Digital Signal Processor (DSP) and Discrete Wavelet Transform (DWT) are of the most powerful technologies that will
shape science and engineering in the twenty-first century. Revolutionary changes have already been made in a broad
range of fields: communications, mobile, medical imaging, radar & sonar, satellite imaging, and remote sensing, to name
just a few. Each of these areas has developed a deep DSP technology, with its own algorithms, mathematics, and
specialized techniques. This combination of breath and depth makes it impossible for any one individual to master all of
the DSP technology that has been developed. DSP education involves two tasks: learning general concepts that apply to
the field as a whole, and learning specialized techniques for your particular area of interest. This chapter starts our
journey into the world of digital signal processing by describing the dramatic effect that DSP has made in several diverse
fields [1].
Most of the signals (1D & 2D) are directly encountered in science and engineering are continuous: light intensity that
changes with distance; voltage that varies over time; a chemical reaction rate that depends on temperature, etc. Analogto-Digital Conversion (ADC) and Digital-to-Analog Conversion (DAC) are the processes that allow digital computers to
interact with these everyday signals. Digital information is different from its continuous counterpart in two important
respects: it is sampled, and it is quantized. Both of these restrict how much information a digital signal can contain [2].
There are several ways to calculate and implement the fast algorithms, such as solving simultaneous linear equations or
the correlation method. The Fast Fourier Transform (FFT) is another method for calculating the DFT. While it produces
the same result as the other approaches, it is incredibly more efficient, often reducing the computation time by hundreds.
While the FFT only requires a few dozen lines of code, it is one of the most used algorithms in DSP applications [3],[4].
2. LITERATURE REVIEWS
Many works are published related to this subject and some of these are listed below:
Sandro V. Silva & Sergio Bampi (2005) investigated that the tradeoffs between area, power and data throughput of
several implementations of the Discrete Wavelet Transform using the lifting scheme in various pipeline designs and
showed the results of five different architectures synthesized and simulated in FPGAs [5].
Mehboob Alam and et al., (2005) presented a new algorithm for a 2D non-separable lifted bi-orthogonal wavelet
transform. This algorithm is derived by factoring complementary pairs of wavelet transform 2D filters. The results are
efficient architectures for real time signal processing, which do not require transpose memory for the 2D processing of
data [6].
Maria E. Anglopoulou and et al., (2008) implemented several schedules on FPGA based platforms for the forward 2D
DWT by using a lifting-based filter-bank implementation. these designs were realized in VHDL and optimized in terms
of throughput and memory requirements, in accordance with the principles of both the schedules and the lifting
decomposition [7].
Juyoung Kim and Taegeun Park (2009) proposed a fully-utilized, block-based 2D DWT (discrete wavelet transform)
architecture, which consists of four 1D DWT filters with two-channel QMF lattice structure. The proposed architecture
requires about 2MN-3N registers to save the intermediate results for higher level decomposition [8].
Volume 2, Issue 10, October 2013
Page 1
International Journal of Application or Innovation in Engineering & Management (IJAIEM)
Web Site: www.ijaiem.org Email: editor@ijaiem.org, editorijaiem@gmail.com
Volume 2, Issue 10, October 2013
ISSN 2319 - 4847
Sugreev Kaur and Rajesh Mehra (2010) presented a high speed and area efficient DWT processor based design for Image
Compression applications. In this proposed design, pipelined partially serial architecture has been used to enhance the
speed along with optimal utilization and resources available on target FPGA [9].
Muzhir Shaban Al-Ani and Talal Ali Hammouri (2011) developed an efficient video compression approach based on
frames difference approaches that concentrated on the calculation of frame near distance. The selection of the meaningful
frame depends on many factors such as compression performance, frame details, frame size and near distance between
frames [10].
Yamini S.Bute and R.W. Jasutkar (2012) presented an efficient VLSI architecture of a high speed, low power Discrete
Wavelet Transform computing. There are number of architectures present for realizing DWT. Based on the application
and the constraints imposed, the appropriate architecture can be chosen [11].
Azadeh Safari, Yinan Kong adopted the lifting DWT which is the most computation-efficient scheme of wavelet analysis
and outlines the multi-resolution features of the wavelet transform. Details of the lifting wavelet transform are analyzed to
propose a high-speed, less-area and power-efficient digital image compression scheme [12].
Lenin Raja, A. Merline, Dr.R.Ganesan Proposed a High speed and reduced –area 2D discrete wavelet transform (2DDWT) architecture. Results indicate that while BP design exhibit inherent speed advantages.DS design requires
significantly fewer hardware resource with increased precision and DWT level [13].
From these works we can say that DSP and DWT are very important fields to develop, in addition the compensation of
these two operations are very important issues to support processing time.
3. TWO DIMENSIONAL DWT
Two dimensional DWT is obtained via the implementation of low pass and high pass filters on rows and columns of
image respectively. A low pass filter and a high pass filter are chosen, such that they exactly halve the frequency range
between themselves. This filter pair is called the Analysis Filter pair. First, the low pass filter is applied for each row of
data, thereby getting the low frequency components of the row. But since the LPF is a half band filter, the output data
contains frequencies only in the first half of the original frequency range. The high pass filter is applied for the same row
of data, and similarly the high pass components are separated, and placed by the side of the low pass components. This
procedure is done for all rows. As mentioned above, the LL band at the highest level can be classified as most important,
and the other 'detail' bands can be classified as of lesser importance, with the degree of importance decreasing from the
top of the pyramid to the bands at the bottom. DWT is a multispectral technique used for converting signal or image into
four different bands such as low-low (LL), low-high (LH), high-low (HL) and high-high (HH) as demonstrated in figure
(1) [14],[15].
Figure (1) Decomposition of image applying DWT
4. DSP TECHNOLOGY
A digital signal processor is a specialized microprocessor with an optimized architecture for the fast operational needs of
digital signal processing. Digital signal processing algorithms typically require a large number of mathematical
operations to be performed quickly and repetitively on a set of data. Signals (perhaps from audio or video sensors) are
constantly converted from analog to digital, manipulated digitally, and then converted again to analog form. Many DSP
applications have constraints on latency; that is, for the system to work, the DSP operation must be completed within
some fixed time.
For example the Texas Instruments TMS320C5x provides several features that support multiprocessing. In addition to
providing the equivalent of bus request and bus grant signals (called HOLD and HOLDA on the TMS320C5x), the
processor also allows an external device to access its on-chip memory. To accomplish this, the external device first asserts
the TMS320C5x's HOLD input. When the processor responds by asserting HOLDA, the external device asserts BR,
indicating that it wishes to access the TMS320C5x's on-chip memory. The TMS320C5x responds by asserting Instruction
Acquisition IAQ. The external device can then read and write the TMS320C5x's on-chip memory by driving
TMS320C5x's address, data, and read/write lines. When finished, the external device desserts HOLD and Block repeat
(BR). This allows the creation of multiprocessor systems that do not require shared memory for interprocessor
communications.
Texas Instruments produce the C6000 series DSP’s, which have clock speeds of 1.2 GHz and implement separate
instruction and data caches. They also have an 8 MiB 2nd level cache and 64 EDMA channels. The top models are
capable of as many as 8000 MIPS (instructions per second), use VLIW (very long instruction word), perform eight
Volume 2, Issue 10, October 2013
Page 2
International Journal of Application or Innovation in Engineering & Management (IJAIEM)
Web Site: www.ijaiem.org Email: editor@ijaiem.org, editorijaiem@gmail.com
Volume 2, Issue 10, October 2013
ISSN 2319 - 4847
operations per clock-cycle and are compatible with a broad range of external peripherals and various buses
(PCI/serial/etc). TMS320C6474 chips each have three such DSP's, and the newest generation C6000 chips support
floating point as well as fixed point processing [16],[17].
5. DSP SYSTEM ARCHITECTURE
The proposed digital signal processing system is implemented via DSP processor to perform FFT and IFFT. This system
is implemented to perform real time processing via serial port. Matlab software introduces a simulation of Texas
Instruments TMS320C5x and TMS320C6x. The architecture of the real time DSP system is shown in figure (2) and it is
divided into the following main parts [18]-[20]:
 Main DSP processor which is the main part that carries out all operations.
 Input Interface Unit (IIU) which contains of a sensor that converts the input into electrical signal, high speed Analog
to Digital Convertor (ADC) which convert the electrical signal into digital form, then a latch device that pass the
incoming data when a clock signal is on.
 Output Interface Unit (OIU) which contains of a latch device that pass the incoming data when a clock signal is on,
(DAC) which converts the digital signal into analog form, then the DAC passes the analog signal into the analog
display.
 Input Memory Unit (IMU) which connected to the input interface unit to store and share the input data.
 Output Memory Unit (OMU) which connected to the output interface unit to store and share the output data.
 Control Unit (CU) which includes a crystal oscillator which control all over the system including input / output
devices and processor.
Figure (2) Architecture of the real time DSP system
6. THE PROPOSED SYSTEM
Literature reviews indicated that there are many approaches to implement 2D DWT, here we try to implement a simple
efficient approach that can be use to realize a real time processing aspect. The proposed first level 2D DWT is shown in
figure (3) in which low pass filters and high pass filters are implemented respectively on rows and columns to generate
Low Low band (LL1), Low High band (LH1), High Low band (HL1) and High High band (HH1).
This proposed system is implemented via many stages as illustrated in figure (3) and these stages are listed below; control
of flow of pixels, set of shift registers, applying low pass and high pass filters.
The two wavelet filters are both implemented and executed by the DSP processor for comparisons. The proposed
algorithm is optimized at source code level and memory usage. The execution time for performing both DWTs is
measured for 2D-DWT for different number of level (first level & second level).
Figure (3) first level 2D DWT
Volume 2, Issue 10, October 2013
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International Journal of Application or Innovation in Engineering & Management (IJAIEM)
Web Site: www.ijaiem.org Email: editor@ijaiem.org, editorijaiem@gmail.com
Volume 2, Issue 10, October 2013
ISSN 2319 - 4847
7. RESULTS AND ANALYSIS
Real Time Fast Algorithm of 2D DWT Based DSP Technology is implemented via Matlab environment and using
hardware simulator that can be performed at real time. 2D DWT is the adequate example of this system, in which can be
applied to any image signal after it converted into digital form. The tested original image is considered to be 500*500
pixels in which there are 250,000 complex operations. That leads to save 1/16 of 250,000 depending on the cycle rate of
DSP. Figure (4) shows an example of different types of wavelet to perform the effects of number of operations. This figure
shows pepper color image before and after compression and their histogram in each case. Figure (5) shows an example of
level two compression, in which it can see that the compressed image has some different from the original image. The
powerful of the implemented system comes from the merging of 2D-DWT and DSP technology to perform an efficient
and flexible real time system.
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8. CONCLUSION
Digital signal processing is one of the most important technologies that applied in a wide range of fields in our life. The
proposed system maintain a large number of mathematical operations to be performed quickly on a set of data, includes
high performance, and cost efficient processors. The proposed system is implemented via merging of hardware and
software environments in the overall system using serial port. The main advantage of this system is that all operations are
done on-line or real time processing. The obtained results show that you can do your own operation and function using
simple modification on the software algorithm.
References
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http://www.dspguide.com/ch1/1.htm accessed at 1/10/2010.
[2] Hahnsang Kim et al., "EPspectra: A Formal Toolkit for Developing DSP Software Applications",
http://www.sds.lcs.mit.edu/SpectrumWare/ accessed at 10/10/2010.
[3] Shuvra S. Bhattacharyya et al., "The CBP Parameter – A Useful Annotation to Aid Block diagram Computers for
DSP", Proceedings of the 2000 International Conference on Circuits and Systems (ISCAS 2000).
[4] KennethW.K.Lui et al., "A study of two-dimensional sensor placement using time-difference-of-arrival
measurements", Digital Signal Processing 19 (2009) 650–659.
[5] Sandro V. Silva & Sergio Bampi, “Area and Throughput Trade-Offs in the Design of Pipelined Discrete Wavelet
Transform Architectures”, Proceedings of the Design, Automation and Test in Europe Conference and Exhibition
(DATE’05), 2005.
[6] Mehboob Alam and et al., “An Efficient Architecture for a Lifted 2D Biorthogonal DWT”, Journal of VLSI Signal
Processing 40, 335–342, 2005.
[7] Maria E. Anglopoulou and et al., “Implementation and Comparison of the 5/3 Lifting 2D Discrete Wavelet
Transform Computation Schedules on FPGAs”, Journal of Signal Processing Systems 51, 3–21, 2008.
[8] Juyoung Kim and Taegeun Park, “High Performance VLSI Architecture of 2D Discrete Wavelet Transform with
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Volume 2, Issue 10, October 2013
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International Journal of Application or Innovation in Engineering & Management (IJAIEM)
Web Site: www.ijaiem.org Email: editor@ijaiem.org, editorijaiem@gmail.com
Volume 2, Issue 10, October 2013
ISSN 2319 - 4847
[9] Sugreev Kaur and Rajesh Mehra, “High Speed and Area Efficient 2D DWT Processors Based |Image Compression”,
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[16] K. Rath, "A Novel Reconfigurable Execution Core for Merged DSP Microcontroller", Journal of Computer Science 3
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AUTHORS
1
Ghazi Ibrahem Raho, Associated professor at Computer Information System& Information Technology at Amman Arab
University – Amman - Jordan. Doctoral Fellowship(1988)- Research & Computer –University of Marseilles - France.
Ph.D. (1981), in Computer Information System& Information Technology, College of Planning &Cybernetics - ASE –
Romania. M.Sc. (1979), in Computer Information System& System Analysis College Of Planning & Cybernetics – Romania.
Postgraduate Diploma(1980), in Information &Applied mathematics UNESCO , Bucharest. B .Sc.(1976) Statistics Almustanseriy
university Baghdad –Iraq.
2
Ali Jbaeer Dawood has received Ph. D. in Computer science, Iraqi Commission for Computers and Informatics Informatics Institute for Postgraduate Studies (2010). He joined in (2000-2003) to Computer Science Department College of
Science- Baghdad University, Baghdad, Iraq as an external lecturer. He joined in (2001-2003) to Computer Science
Department College of Computer, Anbar University, Anbar, Iraq as an external lecturer. He joined in (2002-2007) to Computer
Science Department, AL-Mansour University College, Baghdad, Iraq as an external lecturer. He joined in (2005-2007) to Computer
Science Department, College of Science, AL-Moustasria University, Baghdad, Iraq as a lecturer. He joined in (2007-tell now) to
Computer Science Department College of Computer, Anbar University, Anbar, Iraq as a lecturer. Deputy Dean at College of
Computer, AL-Anbar University, Anbar, Iraq (2010-2012).
3
Muzhir Shaban Al-Ani has received Ph. D. in Computer & Communication Engineering Technology, ETSII, Valladolid
University, Spain, 1994. Assistant of Dean at Al-Anbar Technical Institute (1985). Head of Electrical Department at AlAnbar Technical Institute, Iraq (1985-1988), Head of Computer and Software Engineering Department at Al-Mustansyria
University, Iraq (1997-2001), Dean of Computer Science (CS) & Information System (IS) faculty at University of
Technology, Iraq (2001-2003). He joined in 15 September 2003 Electrical and Computer Engineering Department, College of
Engineering, Applied Science University, Amman, Jordan, as Associated Professor. He joined in 15 September 2005 Management
Information System Department, Amman Arab University, Amman, Jordan, as Associated Professor, then he joined computer science
department in 15 September 2008 at the same university. He joined in August 2009 College of Computer Science, Al-Anbar
University, Al-Anbar, Iraq, as Professor.
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