TDDI04
Concurrent Programming,
Operating Systems,
and Real-time Operating Systems
Contents: Memory Management
§ Background
•
•
Relocation
Dynamic loading and linking
§ Swapping
Memory Management
§ Contiguous Allocation
§ Paging
§ Segmentation
[SGG7] Chapter 8
Copyright Notice: The lecture notes are mainly based on Silberschatz’s, Galvin’s and Gagne’s book (“Operating System
Concepts”, 7th ed., Wiley, 2005). No part of the lecture notes may be reproduced in any form, due to the copyrights
reserved by Wiley. These lecture notes should only be used for internal teaching purposes at the Linköping University.
Acknowledgment: The lecture notes are originally compiled by C. Kessler, IDA.
Klas Arvidsson, IDA,
Linköpings universitet.
TDDI04, K. Arvidsson, IDA, Linköpings universitet.
Background
How to generate code?
§ When the compiler/assembler/linker generates code,
how does it handle …
§ Not all processes fit into memory
(i.e., memory is a resource)
•
•
§ To be run, a program must be brought into memory
and placed within a process
Absolute Jumps?
Adresses of global variables?
Relocation table:
- line 3, patch base+1
- line 3, patch base+5
§ Input queue – collection of processes on the disk that are
waiting to be brought into memory to run the program
§ User programs go through several steps before being run
•
e.g., relocation
Symbolic addressing:
Relative addressing:
Absolute addressing:
…
0: …
243: …
Definition of data X
1: Space for data
244: Space for data
…
2: …
245: …
If (X) goto P
3: If (*1) goto 5
as
…
P: …
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5: …
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Dynamic Loading
Address binding of instructions and data to memory
addresses can happen at three different stages:
§ Loading:
•
§ Compile time / Link time:
•
If memory location known a priori,
absolute code can be generated;
•
must recompile code
if starting location changes
§ Load time: Must generate relocatable code
if memory location is not known at compile time
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•
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Move the compiled and linked image into program memory,
patch remaining relative addresses, and start execution.
•
Better memory-space utilization
> unused routine is never loaded
Useful when large amounts of code are needed
to handle infrequently occurring cases
No special support from OS required
•
> implemented through compiler runtime system
Example: Java dynamic class loading
•
load
time
Need hardware support for address maps
(e.g., base and limit registers, MMU).
TDDI04, K. Arvidsson, IDA, Linköpings universitet.
248: …
8.4
§ Dynamic loading:
• postpone loading of some routine until it is called
link
time
§ Execution time: Binding delayed until run time
if the process can be moved during its execution
from one memory segment to another.
246: If (*244) goto 248
Static
247: …
loading
4: …
Binding of Instructions and Data to Memory
•
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© Silberschatz, Galvin and Gagne 2005
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Dynamic Linking
Logical vs. Physical Address Space
§ Static linking:
• Copy together a program from its modules and libraries used
• relocation (patching) of relative addresses with new ones
• update relocation table and table of externally visible symbols
§ Dynamic linking:
•
•
•
“true” linking postponed until execution time
Small piece of code, stub, used to locate the appropriate
memory-resident library routine
Stub replaces itself with a call to the address of the routine,
and executes the routine
•
OS needed to check if routine is in processes’ memory area
or other accessible memory area
•
Dynamic linking is particularly useful for libraries
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Memory-Management Unit (MMU)
§ The concept of a logical address space
that is bound to a separate physical address space
is central to proper memory management
• Logical address
> generated by the CPU
CPU
> also referred to as virtual address
memory
•
Physical address
Logical
Physical
> address seen by the memory unit
addresses
addresses
§ Logical and physical addresses are the same
in compile-time and load-time address-binding schemes
§ Logical (virtual) and physical addresses differ
in execution-time address-binding scheme
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Swapping
§ Hardware device that maps virtual to physical address
§ The value in the relocation register is added to every address
generated by a user process at the time it is sent to memory
§ The user program deals with logical addresses;
it never sees the real physical addresses
§ A process can be swapped temporarily out of memory
to a backing store, and then brought back into memory
for continued execution
§ Backing store
Dynamic relocation using a relocation register
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Swapping
•
must provide direct access to these memory images
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§ Dual mode: Main memory separated into 2+ partitions:
• Resident OS kernel,
usually held in low memory with interrupt vector
• User processes
then held in high memory
•
swapping variant
used for priority-based scheduling algorithms
•
lower-priority process is swapped out
so higher-priority process can be loaded and executed
§ Major part of swap time is transfer time
total transfer time is directly proportional
to the amount of memory swapped
Swapping
is costly!
§ Modified versions of swapping are found on many systems
(i.e., UNIX, Linux, and Windows)
TDDI04, K. Arvidsson, IDA, Linköpings universitet.
fast disk large enough to accommodate copies of all
memory images for all users
Contiguous Allocation
§ Roll out, roll in
•
•
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§ Multi-partition allocation
• Relocation-register scheme
> protect user processes 1 process has 1 block
(partition) of memory
from each other,
> and from changing OS code / data
• Relocation register contains
value of smallest physical address
• Limit register contains range
of logical addresses
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© Silberschatz, Galvin and Gagne 2005
8.12
2
HW address protection (1)
HW address protection (2)
with base and limit registers
with relocation and limit registers
A base and a limit register
define a logical address space
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logical address
= physical address
(as long as in
process’ range)
© Silberschatz, Galvin and Gagne 2005
A base and a limit register
define a logical address space
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© Silberschatz, Galvin and Gagne 2005
8.14
Contiguous multi-partition allocation
Contiguous Allocation (Cont.)
2 variants:
§ Hole – block of available memory
•
§ Fixed partition scheme
•
•
•
All partitions have equal (fixed) size
•
– Internal fragmentation
holes of various size are scattered throughout memory
§ When a process arrives, it is allocated memory from a hole
large enough to accommodate it
(unused)
+ Simple model
– Degree of multiprogramming
limited by #partitions
§ OS maintains information about:
a) allocated partitions
b) free partitions (holes)
OS
OS
OS
OS
process 5
process 5
process 5
process 5
process 9
§ Variable partition scheme
•
•
process 8
Size of loaded program dictates partition size
process 2
– External fragmentation
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Dynamic Storage-Allocation Problem
How to satisfy a request of size n from a list of free holes?
§ First-fit: Allocate the first hole that is big enough
§ Best-fit: Allocate the smallest hole that is big enough;
•
•
must search entire list, unless ordered by size.
Produces the smallest leftover hole.
must also search entire list.
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process 2
8.16
process 2
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Fragmentation
§ External Fragmentation – total memory space exists to
satisfy a request, but it is not contiguous
§ Internal Fragmentation – allocated memory may be slightly
larger than requested memory; this size difference is memory
internal to a partition, but not being used
§ Reduce external fragmentation by compaction
•
Shuffle memory contents to place all free memory together
in one large block
•
Compaction is possible only if relocation is dynamic,
and is done at execution time
•
I/O problem
Produces the largest leftover hole.
Simulations show: First-fit and best-fit better than worst-fit
in terms of storage utilization
process 2
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§ Worst-fit: Allocate the largest hole;
•
•
process 9
process 10
> Lock job in memory while it is involved in I/O
> Do I/O only into OS buffers
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Example of Compacting
Example of Compacting: Solution 1
p1
p1
p1
p2
p3
p2
p2
pnew
p3
p3
pnew
p4
p4
p4
Move all occupied areas to one side until there is a hole large enough for pnew
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Example of Compacting: Solution 2
p1
p1
p3
p2
p2
p3
pnew
p4
p4
Search and select one (or a few) processes to move to free a hole large enough…
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Paging: Address Translation Scheme
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Paging
§ Goals:
• Physical address space of a process can be noncontiguous
• Process is allocated physical memory whenever the latter is
available – no external fragmentation
§ Divide physical memory into fixed-sized blocks called frames.
Frame size is power of 2, between 512 bytes and 8192 bytes.
§ Divide logical memory into blocks of same size, called pages.
§ Internal fragmentation
§ Keep track of all free frames
§ Set up a page table to translate
logical to physical addresses
§ To run a program of size n pages,
need to find n free frames and load program
TDDI04, K. Arvidsson, IDA, Linköpings universitet.
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•
Frame 0
•
Page => Frame
mapping
Page 1
Page number (p) –
index into a page
table which contains
the base address of
each page in
physical memory
Frame 1
Frame 2
Page 2
Frame 3
Page 3
0010 => 10110
Frame 4
1 character = 1 byte
Page offset (d) –
combined with base
address to define
the physical memory
address that is sent
to the memory unit
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Paging Example
Page 0
§ Address generated by
CPU is divided into:
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Frame 5
Frame/page size = 4 bytes = 22 bytes
Frame 6
Number of pages = 4 = 22
Logical addr. space size = 16 =
22+2
Frame 7
Physical address
space size = 32 bytes
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Allocating frames from free-frame list
Implementation of the Page Table
§ Page table is kept in main memory
§ Page-table base register (PTBR)
points to the page table
§ Page-table length register (PRLR)
indicates size of the page table
§ Every data/instruction access requires 2 memory accesses.
•
One for the page table and one for the data/instruction.
§ Solve the two-memory-access problem
•
by using a special fast-lookup cache (in hardware):
translation look-aside buffer (TLB)
After allocation
Before allocation
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© Silberschatz, Galvin and Gagne 2005
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> Implements an associative memory
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Paging Hardware With TLB
Associative Memory
§ Associative memory = content-addressable memory
• ADT Dictionary
Page number
Frame number
f
p
TLB: Address translation (p, f)
If p is in TLB, get frame number f out
Otherwise get frame number from page table in memory
•
•
TLB: fast, small, and expensive,
§ TLB realized in hardware => parallel search for contents
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Typ. 64…1024 TLB entries
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Effective Access Time
Memory Protection
§ Memory cycle time: t
§ implemented by
associating protection bit
with each frame
§ Time for associative lookup: ε
in main memory
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§ TLB hit ratio α
•
percentage of times that a page number is found in TLB
§ Effective Access Time (EAT):
EAT = (t + ε) α + (2t + ε)(1 – α)
= 2t + ε – α t
Example: For t =100 ns, ε = 20 ns, α = 0.8:
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EAT = 140 ns
© Silberschatz, Galvin and Gagne 2005
§ Valid-invalid bit attached
to each entry in the page
table:
• “valid”: the associated
page is in the process’
logical address space,
and is thus a legal
page
• “invalid”: the page is
not in the process’
logical address space
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Page Table Structure
Hierarchical Page Tables
§ The “large page table problem”
•
Most modern systems support large logical address spaces
(232 … 264 bytes)
•
For 232 logical addresses with a page size 212 = 4096,
page table has 220 = 1M entries,
thus needing 4 MB physical memory
§ Break up the
logical address space into
multiple page tables
§ A simple technique is a
two-level page table:
§ Page table structures:
•
•
•
Hierarchical Paging: “page the page table”
Hashed Page Tables
Inverted Page Tables
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Two-Level Paging Example
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Address-Translation Scheme
§ A logical address (on 32-bit machine with 4K page size)
is divided into:
•
•
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§ Address-translation scheme for a two-level 32-bit paging
architecture
a page number consisting of 20 bits
a page offset consisting of 12 bits
§ Since the page table is paged, the page number is
further divided into:
• a 10-bit page number
•
a 10-bit page offset
page number
§ Thus, a logical address is as follows:
page offset
pi
p2
d
10
10
12
where pi is an index into the outer page table, and p2 is
the displacement within the page of the outer page table
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Hashed Page Tables
Inverted Page Table
§ Common in address spaces > 32 bits
§ One entry for each
real page of memory
§ The virtual page number is hashed into a page table.
This page table contains a chain of elements hashing to the
same location.
§ Virtual page numbers are compared in this chain searching
for a match.
If a match
is found,
the corresponding
physical frame
is extracted.
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§ Entry: <pid, p>
p: virtual address of the
page stored in that
real memory location,
pid: process that owns that page
(as address space identifier)
§ Decreases memory needed to store each page table, but
increases time needed to search the table when a page
reference occurs
§ Use hash table to limit the search to one — or at most a few —
page-table entries
§ Examples: UltraSPARC, PowerPC, Itanium
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Shared Pages
– Easy with paged memory!
Shared Pages Example
§ Shared code
• One copy of read-only (reentrant) code shared among
processes (i.e., text editors, compilers, window systems).
•
Shared code must appear in same location in the logical
address space of all processes
§ Private code and data
• Each process keeps a separate copy of the code and data
•
The pages for the private code and data can appear
anywhere in the logical address space
§ Shared pages are hard to implement when inverted page
tables are used
• Only 1 virtual page entry for every physical page
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Segmentation
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Logical View of Segmentation
§ Memory-management scheme
that supports a user view of memory:
1
4
1
2
§ A program is a collection of segments.
§ A segment is a logical unit such as:
•
main program, procedure,
function, method,
•
•
•
object, local variables, global variables,
3
2
4
3
common block, stack,
user space
symbol table, arrays
physical memory space
§ Idea: allocate memory according to such segments
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Example of Segmentation
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Segmentation Architecture
§ Logical address is a pair
<segment-number, offset>
§ Segment table – maps two-dimensional physical addresses;
each table entry has:
• base – physical starting address where the segment
resides in memory
• limit – specifies the length of the segment
§ 2 registers (part of PCB):
• Segment-table base register (STBR)
points to the segment table’s location in memory
• Segment-table length register (STLR)
indicates number of segments used by a program;
Segment number s is legal if s < STLR
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Segmentation Architecture:
Address Translation
Segmentation Architecture (cont.)
§ Relocation.
• dynamic
• by segment table
§Protection. With each entry in
segment table associate:
§ Sharing.
•read / write / execute privileges
•
•
•validation bit = 0
⇒ illegal segment
Protection bits in table entries
shared segments
same segment
number
§ Allocation.
• first fit/best fit
• external fragmentation
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Sharing of Segments
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Since segments vary in length,
memory allocation is a dynamic
storage-allocation problem
© Silberschatz, Galvin and Gagne 2005
8.44
Combining Segmentation and Paging
§
§
§
§
Each segment is organized as a set of pages.
Segment table entries refer to a page table for each segment.
TLB used to speed up effective access time.
Common in today’s operating systems (e.g. Solaris, Linux).
segment number
page number
s
virtual address:
displacement
p
d
if TLB hit for (s,p), get f,
otherwise:
segment
table origin
register
s
s’
page table for
this segment
p
f
segment
table for this
process
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TDDI04, K. Arvidsson, IDA, Linköpings universitet.
f
d
physical address
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