Joint IEEE-SA and ITU Workshop on Ethernet
Synchronization architecture
Michael Mayer,
Editor, G.8265, G.8275
Geneva, Switzerland, 13 July 2013
Overview
Architecture in ITU
Why?
Requirements
Synchronization recommendation structure
General aspects of architecture in ITU-T
Formal model example
Overview of key Synchronization
architecture recommendations
G.8264, Physical layer frequency (SyncE)
G.8265, Packet based frequency
G.8275, Packet based time/phase
Geneva, Switzerland,13 July 2013
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Architecture development
Start here
Development of architecture
starts with Requirements
Requirements
Network
Model
Which constrains equipment
specifications
Equipment
specifications
Deployment
Geneva, Switzerland,13 July 2013
A network model is then
developed
Ensuring that deployed
components meet all
functional requirements
for the network application
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Next generation synchronization
input constraints
Key aspects of NGN synchronization
Packet network infrastructure
Moving away from SONET/SDH
But can’t throw out existing network
New synchronization requirements
wireless backhaul requirements
Air interface requirements
New methods
CES, PTP, Synchronous Ethernet
New clock structures
BC, TC, GM
Architecture helps see how all pieces fit together
Geneva, Switzerland,13 July 2013
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Formal models based
on G.805
E1
E1
ETH
TDM timing
G.805
Functional
Model for
CES From
G.8264
ETH_CI
ETY
ETH_CI
Ext.Ref.
Ext.Ref.
UTC
E1
C
E
S
Switch
Geneva, Switzerland,13 July 2013
Switch
C
E
S
E1
Network
Element
Model
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Details of functions
Individual functions may be specified in
different recommendations
May include other aspects related to basic
transport, in addition to synchronization
Some blocks may contain significant detail
Sync functions in G.781
Clocks in G.8262 (e.g. EEC)
Transport functions in G.8021 (Ethernet)
Not all functions developed by Q13/15
Geneva, Switzerland,13 July 2013
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Ethernet Synchronization detail
Inputs
ETYn_AP:
ETYn_AI_Data
ETYn_AI_Clock
ETYn_AI_TSF
ETYn_AI_TSFrdi
ETYn_AI_TSFfdi
Outputs
ETH_FP and ETH_TFP:
ETH_CI_Data
ETH_CI_Clock
ETH_CI_SSF
ETH_CI_SSFrdi
ETH_CI_SSFfdi
ETH_PP:
ETH_PI_Data
ETH_FP:
ETH_CI_ESMC
ETYn/ETH_A_Sk_MP:
ETYn/ETH_A_Sk_MI_FilterConfig
ETYn/ETH_A_Sk_MI_MAC_Lengt
h
Holdover control MI
ETYn/ETH_A_Sk_MP:
ETYn/ETH_A_Sk_MI_pErrors
ETYn/ETH_A_Sk_MI_pFramesReceived
OK
ETYn/ETH_A_Sk_MI_pOctetsReceived
OK
From Ethernet equipment specification: G.8021
Geneva, Switzerland,13 July 2013
77
…More detail can be illustrated
ETH_ CI
( ETH _FP)
ETH _CI
( ETH _ TFP )
ETH _CI_ESMC
ETH_CI_Clock
Filter
MI_FilterConfig
ETH_ PI
( ETHTF _PP )
ETH_ PI
( ETHF _ PP )
Replicate
802.1AB/X protocols
802.3 protocols
MI_pFramesReceivedOK
MI_pOctetsReceivedOK
MAC Frame Counter
MI_pErrors
MAC Frame Check
MI_MAC_Length
MAC Length Check
ETYn Server Specific
ETYn _ AI
•
•
Description of functional block will specify as much detail as necessary to define
implementation requirements
Ensures a high degree of interoperability is achievable using standards provided
by both IEEE and ITU
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Current versions
G.8264/Y.1364: Distribution of timing information
through packet networks
G.8264/Y.1364 (10/2008)
G.8264/Y.1364 (2008) Amd. 1 (09/2010)
G.8264/Y.1364 (2008) Cor. 1 (11/2009)
G.8264/Y.1364 (2008) Amd. 2 (02/2012)
G.8264/Y.1364 (2008) Cor. 2 (02/2012)
G.8265/Y.1365 : Architecture and requirements for
packet-based frequency delivery
G.8265/Y.1365 (10/2010)
G.8265/Y.1365 (2010) Amd. 1 (04/2011)
G.8265/Y.1365 (2010) Amd. 2 (10/2012)
G.8275: Architecture and requirements for packetbased time and phase delivery
Consented July 12, 2013
Geneva, Switzerland,13 July 2013
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New Options become
available
The development of a coordinated
architecture allows
Network to evolve
Understand limitations
Allow new capabilities to become
available
Example follows:
Multiple frequency distribution options for
wireless backhaul timing over multiple
networks
Geneva, Switzerland,13 July 2013
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Architecture results
in flexibility
Physical layer:
Synchronous
Ethernet signal
(carrying Operator A
reference)
Service owner provides timing
Mobile
Operator A
Synchronous
Ethernet signal
(carrying Operator A
reference)
Carrier
Operator B
RAN
BS
RAN
NC
(OTN)
Mobile
Operator A
Network limits
Direction of timing distribution
Synchronous
Ethernet signal
(traceable to carrier
timing reference)
Physical layer:
Intermediate carrier
provides timing
Mobile
Operator A
Ethernet signal
(synchronous or
asynchronous)
Carrier
Operator B
RAN
BS
Direction of timing distribution
Ethernet Signal
(Synchronous or
Asynchronous)
Network
RAN
BS
Operator A
(e.g. mobile operator)
Geneva, Switzerland,13 July 2013
Packet Timing signal
(Traceable to Operator A
Reference)
Operator B
(e.g. Ethernet)
Mobile
Operator A
G.8264-Y.1364.Amd.1(10)_F12.3
Ethernet Signal
(Synchronous or
Asynchronous)
GM
Network
Packet layer:
RAN
NC
(Ethernet)
Network limits
Service owner
provides timing
G.8264-Y.1364.Amd.1(10)_F12.2
Network
RAN
NC
Operator A
(e.g. mobile operator)
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Summary
Architecture recommendations are important
Developed to provide an overall framework for how technology
can be deployed in a network
Provide a framework for controlled technology evolution
Synchronization related architecture documents
Provide controlled evolution of technology
Ensure high degree of interoperability of different synchronization
technologies
Guidance for developing equipment recommendations to support
telecom specific requirements
Synchronization solutions must fit with packet traffic functions of NEs
Strong linkage to Hypothetical Reference Model (HRM) development
Provide guidance to other SDO’s
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