Personnel
Erik Larsson - Course leader (examinator)
 Email: erik.larsson@liu.se
Design for Test of Digital Systems
TDDC33
Dimitar Nikolov - Course assistant
 Email: dimitar.nikolov@liu.se
Madeleine Häger Dahlqvist - Course secretary
 Email: madeleine.hager.dahlqvist@liu.se
Erik Larsson
Department of Computer Science
2
Aim
Recommended Textbook
The purpose of the course is that students shall acquire knowledge
on the importance of design of testable digital systems and
develop the ability to formulate and solve problems related to
testing.
The recommended textbook is:
 VLSI Test Principles and Architectures, Laung-Terng Wang,
Chen-Wen Wu, Xiaoqing Wen Hardbound, 808 pages,
publication date: JUL-2006, ISBN-13: 978-0-12-370597-6
ISBN-10: 0-12-370597-5, Imprint: MORGAN KAUFFMAN
After completing the course, students shall be able to:
 describe for fundamental test and fault concepts
 methodical solve test related problems in a development
environment
 formulate and implement/apply test algorithms
 define and implement a minor design-for-test assignment
3
4
Alternative Literature
Survey/tutorial papers
 Principles of Testing Electronic Systems, Samiha Mourad and
Yervant Zorian, ISBN: 978-0-471-31931-3, Hardcover, 440
pages, August 2000
 A tutorial on built-in self-test. I. Principles,
Agrawal, V.D., Kime, C.R., Saluja, K.K.
 Digital Systems Testing and Testable Design, Miron Abramovici,
Melvin A. Breuer, Arthur D. Friedman ISBN:
978-0-7803-1062-9, Hardcover, 672 pages, September 1994,
Wiley-IEEE Press
 A tutorial on built-in self-test. 2. Applications,
Agrawal, V.D., Kime, C.R., Saluja, K.K.
 Essential of Electronic Testing for Memory and Mixed-Signal
VLSI Circuits, Michael L. Bushnell and Vishwani D. Agrawall,
1st ed. 2000. Corr. 2nd printing, 2005, 712 p., Hardcover ISBN:
978-0-7923-7991-1
 Resource-constrained system-on-a-chip test: a survey,
Xu, Q. and Nicolici, N.
 Design for testability - A survey,
Williams, T.W. and Parker, K.P.
 Introduction to Advanced System-on-Chip Test Design and
Optimization, Erik Larsson, Series: Frontiers in Electronic
Testing , Vol. 29, 2005, XVI, 388 p., Hardcover, ISBN:
978-1-4020-3207-3
5
Examination
6
Laborations
Registration
TEN1: Written exam (U,3,4,5), 3 ECTS
 The labs should be solved individually. Registration in WebReg.
 Written examination (max 40 (including 10 points from labs)
points)
 Questions regarding the registration are answered by Dimitar
 Last day for the registration is defined by Dimitar
 5=A=34p
General instructions
 4=B=28p
 3=C=22p
 The labs should be handed in using the covers located by the
printers
 UK=Fx=less than 22p
 Last day of handing in the labs will be told by Dimitar
LAB1: Laboratory work - 3 ECTS
Instructions and guidelines
 Can get up to 10 points to include in the written preexam”Dugga” (note - each dugga is given at one time; no
possibility repeat)
 Lab 1 - Test pattern generation
 Lab 2 - Design for test
 Lab 3, 4 - Boundary Scan
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8
Course Outline
Late Course Registration
 Introduction; Manufacturing, Wafer sort, Final test, Board and
System Test, Defects, and Faults
 Test generation; combinational and sequential test generation
 Design-for-Test techniques; test point insertion, scan, enhanced
scan
 Built-In Self-Test; Logic BIST and memory BIST
 Please find the correct form from:
http://www.lith.liu.se/blanketter/
 Fill the form and give it to Patrick Lambrix (director of studies) in
office: B 2B:474, Building B, Ground Floor
 System Chip Test; test architectures, test planning, test
scheduling, and test data compression, power constraints, test
data compression.
 System Test and boundary Scan
 Two invited speakers from SAAB
 Study visit to Flextronics
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Outline
 Electronics
Design for Test of Digital Systems
TDDC33
 Manufacturing
 Test, diagnosis, and verification
 Cost, defects, fault models, and quality of test
Erik Larsson
Department of Computer Science
12
Products with electronic systems
Production of electronic products
Wafer
IC
Board
“System”
13
14
16
Making electronic products
Design
Design
specification
Production
Transistor Count
Product
Types of products:
- First of a kind: product that breaks new ground
- Me too with a twist: improve existing product (example, fast bus)
- Derivate: add a little more functionality
- Next-generation product: replace mature product
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16
Integrated Circuits (ICs)
IC
Die
 Small Scale Integration (SSI), early 1960s
example, Philips TAA320 had two transistors
 Medium Scale Integration (MSI), late 1960s
example, Intel 4004 had 2300 transistors
 Large Scale Integration (LSI), mid-1970s
example, Intel 8008 had 4500 transistors
 Viper 2.0 RevB
 Very-Large Scale Integration (VLSI), 1980s,
example, Intel 80286, 134000 transistors
 Analog/Digital TV Processor
 10mm x 10 mm (100 mm2)‫‏‬
 Ultra-Large Scale Integration (ULSI), now,
more than 1 million transistors
 ~10 M gates
 Wafer-scale integration (WSI)
 ~50 M transistors
 System-on-a-chip
 ~100 clock domains
 Three dimensional integrated circuits (3D-ICs)
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18
17
Printed Circuit Board (PCB)‫‏‬
Multi-board system
Backplane
19
19
20
35
Types of systems
Digital systems
 Analog systems
 Digital systems
 Mixed signal systems
21
22
AND-gate
 Manufacturing
23
24
21
IC
IC manufacturing
Die
Chemical or plasma
etch
Si-substrate
Hardened resist
SiO
2
(a) Silicon base material
Si-substrate
Photoresist
SiO
2
Si-substrate
(d) After development and etching of resist,
chemical or plasma etch of SiO
2
Hardened resist
SiO
2
(b) After oxidation and deposition
of negative photoresist
 Viper 2.0 RevB
 Analog/Digital TV Processor
UV-light
 10mm x 10 mm (100 mm2)‫‏‬
Patterned
optical mask
 ~10 M gates
Exposed resist
 ~50 M transistors
Si-substrate
(e) After etching
SiO
2
Si-substrate
Si-substrate
 ~100 clock domains
(c) Stepper exposure
(f) Final result after removal of resist
25
17
Feature size
26
Linewidth
IC manufacturing
Space
Photoresist
Thickness
Substrate
Lithography has three parts: (1) Light source, (2) Wafer exposure (3) Resist
36
35
Bonding Techniques
Package-to-Board Interconnect
Flip-chip
39
42
Outline
IC Defects
 Electronics
 Manufacturing
 Defects, test, diagnosis, and verification
 Cost, defects, fault models, and quality of test
Seed
Salt
31
44
Defects and Faults
PCB Defects
 Example of a defect
Occurrence frequency (%)‫‏‬
Defect classes
51
1
6
13
6
8
5
5
5
Shorts
Opens
Missing components
Wrong components
Reversed components
Bent leads
Analog specifications
Digital logic
Performance (timing)‫‏‬
 A defect manifests itself as a fault
 Fault: permanent or temporary (in respect to time)
 Permanent (hard)
 Temporary (soft)‫‏‬
Ref.: J. Bateson, In-Circuit Testing, Van Nostrand Reinhold, 1985.
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Test
Verification, test and diagnosis
 Verification is to verify the correctness of the design. It is
performed through simulation, hardware emulation, or formal
methods. It is performed once prior to manufacturing. Responsible
for quality of design.
Device under test (DUT)
Stimulus
Response
 Test verifies the correctness of manufactured hardware. Test is a
two-part process:
 Test generation: software process executed once during design, and
Stimulus: test vectors
 Test application: electrical tests applied to hardware. Test application
performed on every manufactured device. Responsible for quality of
devices.
Test pattern: test vector + expected test response (ordered n-tuple of binary values)
Produced test response is compared against expected test response
Design specification is correct. It
means that tests can be
generated from the design
specification.
 Diagnosis: Identification of a specific fault that is present on DUT.
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36
47
Diagnosis and volume production
Outline
Yield
 Electronics
 Manufacturing
 Defects, test, diagnosis, and verification
Pass/fail testing
 Cost, defects, fault models, and quality of test
Diagnosis
First silicon
Ramp-up
Volume production
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67
Making fault free electronic products
Rule of ten: Finding
a defect in one later
step increases cost
with a factor 10
compared to
addressing the
defect in current
step.
Types of Test
 Production
ok?
ok?
ok?
ok?
ok?
Test Preparation
Production Test
In-Field Test
 Wafer sort (or probe)
Test of die on the wafer
 Final test (package)
Test of packaged chips
 Acceptance
Test to demonstrate compliance
with purchaser’s requirements
 Sample
Test some but not all parts
 Go/No-go
Pass or fail test
 Characterization
(performance)
Test actual parameters
 Stress screening (burn-in)
out
At high temperature to get wear-
 Diagnostic (repair)
Test to pinpoint defective part
 On-line
Test while system is in operation
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45
Types of Test
Important aspects
 Specify the test vector
 Determine correct response (expected response)
 Wafer sort - tests the logic of each die on the wafer
 Evaluate quality of test
 Fault coverage = No of faults detected / No. faults modeled
 Final test - tests the logic of each packaged IC
 Defect level (DL) = Number of faulty units shipped / Total number of
units shipped.
 Yield = Number of good parts / Total number of tested parts
 Board test - tests interconnections (soldering errors)
 Williams and Brown (1981): DL=1-Y(1-T)
where Y is yield and T is ratio of covered parts by test.
 For example:
 If possible to test for all defects: T=1 -> DL=1-Y(1-1) =0
 If no defective units manufactured: Y=1 -> DL=1-1 (1-T)=0 (T can be 0)
41
Manufacturing Test
42
Testing
 Determines whether manufactured chip meets specs
Automatic Test Equipment (ATE)‫‏‬
 Must cover high % of modeled faults
Test stimuli (TS)‫‏‬
0010100
0110000
 Must minimize test time (to control cost)‫‏‬
 No fault diagnosis
 Tests every device on chip
Device under test
Expected responses (ER)‫‏‬
1011001
1101010
 Test at speed of application or speed guaranteed by supplier
Produced responses (PR)‫‏‬
0111011
0100101
Compare
Pass/fail
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58
May 8, 2008
52
Tests
Automatic Test Equipment Components
 Good IC that pass test -> OK
Bad IC that fail test -> OK
 Consists of:
 Powerful computer
 Powerful 32-bit Digital Signal Processor (DSP) for analog testing
 Bad ICs that pass test -> test escape
Good ICs that fail test -> yield loss
Outcome of
test
 Test Program (written in high-level language) running on the
computer
Pass
Fail
 Probe Head (actually touches the bare or packaged chip to perform
fault detection experiments)
Good
OK
Yield
loss
Bad
Test
esc.
OK
IC
 Probe Card or Membrane Probe
(contains electronics to measure signals on chip pin or pad)
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46
Automatic Test Equipment Companies
Automatic Test Equipment Companies
 Teradyne was founded in 1960 by two
classmates from Massachusetts
Institute of Technology (MIT). http://
www.teradyne.com/
 Agilent Technologies (formed in 1999
from a division of Hewlett-Packard),
www.agilent.com
 LTX was founded in 1976 and the
headquarter is in Norwood, MA
(Greater Boston), http://www.ltx.com/
 Eagle Test Systems was founded in
1976. The headquarters is in Buffalo
Grove, Illinois, (merged to Teradyne
2008), http://www.eagletest.com/
 Credence Systems, Founded in 1978
as Semiconductor Test Solutions,
http://www.credence.com/
 Advantest Corporation (Kabushikigaisha Adobantesuto), founded in 1954.
Headquarter in Tokyo, Japan.
 LTXCredence merger 2008, http://
www.ltxc.com
 Verigy was in 2006 formed from a
division of Agilent Technologies, now
part os Advantest, https://
www.verigy.com/
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May 8, 2008
64
Automatic Test Equipments (ATEs)‫‏‬
Test generation
 Sapphire from Credence
 V93000 from Verigy
 T6577 from Advantest
 Tiger from Teradyne
a
z
b
ab
00
01
10
11
May 8, 2008
65
Fault models
72
Test generation
 Stuck-at Fault, Bridging Fault, Shorts (Resistive shorts), Opens,
Delay Faults, Transient Fault
Example: Create test for output connected to Vdd
 So far stuck-at fault model is the most used one:
Fault-free
 Motivations:
Faulty
Vdd
 Simple
1
X
0
1
 Covers quite well possible defects
 Above 65 nm: SA0 and SA1
1
0
1X
10
 At 65 nm -> TSMC standard: 6 fault types; DC-SA0/SA1, ACinput slow to rise (ISR), input slow to fall (ISF), output slow to
rise (OSR), output slow to fall (OSF)
 Below 65 nm (i.e 45 nm and 32 nm): ??
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May 8, 2008
73
1
z
0
0
0
1
Test generation
Stuck-at Fault
 A line is fixed to logic value 0 (stuck-at-0) or 1 (stuck-at-1)‫‏‬
Example: Create test for output connected to Vdd
Fault-free
 For the stuck-at fault model there are for a circuit with n lines
2*n possible fault sites
Faulty
Vdd
X
0
X
0
0
G3
A
B
1
G1
W
NOR
X
G2
U
NOR
AND
OR
Z
F
G4
H
AND
Y
Find test stimuli such that test responses are
different in fault-free and faulty device
G5
G
 Quality of a test is given by:
fault coverage = faults detected / total number of faults
 Example: 10 lines (20 faults) detect 12 faults: f.c.=12/20 (60%)
May 8, 2008
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Single Stuck-at Fault
 Three properties define a single stuck-at fault

Only one line is faulty

The faulty line is permanently set to 0 or 1

The fault can be at an input or output of a gate
 Example: XOR circuit has 12 fault sites ( ) and 24 single stuckat faults
Faulty circuit value
Good circuit value
j
c
1
0
a
b
d
e
Design for Test of Digital Systems
TDDC33
1(0)
s-a-0
g
1
Erik Larsson
0(1)
h
i
z
1
k
f
Test vector for h s-a-0 fault
76
Department of Computer Science