Scheduling and Communication Synthesis for Distributed Real-Time Systems Paul Pop Department of Computer and Information Science Linköpings universitet 1 of 30 June 14, 2000 Outline Motivation System Model and Architecture Scheduling and Communication Synthesis Time Driven Systems Event Driven Systems Real Life Example Conclusions Scheduling and Communication Synthesis for Distributed Real-Time Systems Paul Pop 2 of 30 June 14, 2000 Embedded Systems General purpose systems Microprocessor market shares in 1999 Embedded systems 99% 1% Scheduling and Communication Synthesis for Distributed Real-Time Systems Paul Pop 3 of 30 June 14, 2000 Distributed Real-Time Systems Safety critical applications (e.g. Drive-by-Wire): timing constraints, data and control dependencies. Communication protocols: Time Triggered Protocol (TTP), Controller Area Network (CAN). Scheduling of processes and communication of messages: guaranteeing timing constraints. Scheduling and Communication Synthesis for Distributed Real-Time Systems Paul Pop 4 of 30 June 14, 2000 Hardware/Software Codesign System Specification Architecture Selection Goals of the thesis: Scheduling... Scheduling of processes and messages for distributed hard real-time applications with Partitioning control and data dependencies in the context of a given communication protocol. Scheduling Hardware Synthesis Software Synthesis Communication synthesis... Optimization of the parameters of the communication protocol so that the overall system performance is increased and the Integration imposed timing constraints are satisfied. Scheduling and Communication Synthesis for Distributed Real-Time Systems Paul Pop 5 of 30 June 14, 2000 Related Work Scheduling: Static cyclic non-preemptive scheduling: P. Eles, G. Fohler, D. D. Gajski, H. Kasahara, H. Kopetz, K. Kuchcinski, J. Madsen, J. Xu. Fixed priority preemptive scheduling: J. Axelsson, S. Baruah, A. Burns, J. W. Layland, C. L. Liu, K. Tindell, J. A. Stankovic, , W. Wolf , T. Y. Yen. Communication synthesis: G. Borriello, R. Ernst, H. Hansson, J. Madsen, R. B. Ortega, K. Tindell. Scheduling and Communication Synthesis for Distributed Real-Time Systems Paul Pop 6 of 30 June 14, 2000 Characteristics and Message Distributed hard real-time applications. Heterogeneous system architectures. Systems with data and control dependencies. Scheduling of processes: Time triggered: Static cyclic non-preemptive scheduling, Event triggered: Fixed priority preemptive scheduling. Communications using the time-triggered protocol (TPP). The performance of the system can be significantly improved by considering the communication protocol and the control dependencies during scheduling. Scheduling and Communication Synthesis for Distributed Real-Time Systems Paul Pop 7 of 30 June 14, 2000 Outline Motivation System Model and Architecture Scheduling and Communication Synthesis Time Driven Systems Event Driven Systems Real Life Example Conclusions Scheduling and Communication Synthesis for Distributed Real-Time Systems Paul Pop 8 of 30 June 14, 2000 Conditional Process Graph (CPG) Subgraph corresponding to DCK P P00 P P11 C P P22 P P66 K P P12 12 P5 P7 P P88 P P99 P P14 14 D P13 K P15 P P16 16 P P17 17 P P10 10 First processor Second processor ASIC P P11 11 P P33 C C P4 D P P18 18 Scheduling and Communication Synthesis for Distributed Real-Time Systems Paul Pop 9 of 30 June 14, 2000 Hardware Architecture Hard real-time distributed systems. Nodes interconnected by a broadcast communication channel. Nodes consisting of: TTP controller, CPU, RAM, ROM, I/O interface. Communication between nodes is based on the time-triggered protocol. I/O Interface RAM CPU ROM ASIC TTP Controller Node Scheduling and Communication Synthesis for Distributed Real-Time Systems Paul Pop 10 of 30 June 14, 2000 Time Triggered Protocol I/O Interface H. Kopetz, Technical University of Vienna. RAM Intended for distributed real-time control applications that require high degree of dependability and predictability. ROM CPU ASIC Recommended by the X-by-Wire Consortium for use in safety critical applications in vehicles. TTP Controller Node S0 S1 Slot Integrates all the services required in the design of fault-tolerant distributed real-time systems. S2 S3 S0 S1 S2 TDMA Round Cycle of two rounds S3 Bus access scheme: time-division multiple-access (TDMA). Schedule table located in each TTP controller: message descriptor list (MEDL). Scheduling and Communication Synthesis for Distributed Real-Time Systems Paul Pop 11 of 30 June 14, 2000 Outline Motivation System Model and Architecture Scheduling and Communication Synthesis Time Driven Systems Event Driven Systems Real Life Example Conclusions Scheduling and Communication Synthesis for Distributed Real-Time Systems Paul Pop 12 of 30 June 14, 2000 Time Triggered Processes Input Problem Formulation Safety-critical application with several operating modes. Each operating mode is modelled by a CPG. The system architecture and mapping of processes to nodes are given. The worst case delay of each process is known. Output Local schedule tables for each node and the MEDL for the TTP controllers. Delay on the system execution time for each operating mode, so that this delay is as small as possible. Note Processes scheduled with static cyclic non-preemptive scheduling, and messages according to the TTP. Scheduling and Communication Synthesis for Distributed Real-Time Systems Paul Pop 13 of 30 June 14, 2000 Scheduling Example P1 P4 P3 P2 24 ms S1 S0 Round 1 m3 m1 m2 Round 2 Round 3 m4 Round 4 P1 P4 P3 P2 22 ms S0 S1 Round 1 m1 m2 Round 2 m3 Round 3 Round 4 P4 20 ms P2 S1 Round 1 m1 m2 Round 2 P1 m1 m2 m4 P1 S0 Round 5 P2 P3 m3 m4 P3 m3 m4 P4 Round 3 Scheduling and Communication Synthesis for Distributed Real-Time Systems Paul Pop 14 of 30 June 14, 2000 Scheduling Strategy 1. The scheduling algorithm has to take into consideration the TTP. Priority function for the list scheduling. 2. The optimization of the TTP parameters is driven by the scheduling. Sequence and lengths of the slots in a TDMA round are determined to reduce the delay. Two approaches: Greedy heuristic, Simulated Annealing (SA). Two variants: Greedy 1 tries all possible slot lengths, Greedy 2 uses feedback from the scheduling algorithm. SA parameters are set to guarantee near-optimal solutions in a reasonable time. Scheduling and Communication Synthesis for Distributed Real-Time Systems Paul Pop 15 of 30 June 14, 2000 Experimental Results Deviations from the near-optimal schedule lengths obtained by SA: Average Percentage Deviation [%] 60 50 40 Naive Designer Greedy 1 Greedy 2 30 20 10 0 80 160 240 320 Number of processes Scheduling and Communication Synthesis for Distributed Real-Time Systems Paul Pop 400 16 of 30 June 14, 2000 Outline Motivation System Model and Architecture Scheduling and Communication Synthesis Time Driven Systems Event Driven Systems Real Life Example Conclusions Scheduling and Communication Synthesis for Distributed Real-Time Systems Paul Pop 17 of 30 June 14, 2000 Event Triggered Processes Input Problem Formulation An application modelled using conditional process graphs. Each process has an execution time, a period, a deadline, and a priority. The system architecture and mapping of processes are given. Output Schedulability analysis for systems modelled using CPGs. Schedulability analysis for the time-triggered protocol. The MEDL for the TTP controllers so that the process set is schedulable on an as cheap (slow) as possible processor set. Note Processes scheduled with fixed priority preemptive scheduling, and messages according to the TTP. Scheduling and Communication Synthesis for Distributed Real-Time Systems Paul Pop 18 of 30 June 14, 2000 Example P0 27 P1 C C 30 P2 P9 30 P6 25 P3 CPG 25 P10 22 P7 19 P5 No conditions Conditions 32 P11 24 P4 P12 Worst Case Delays G1 120 100 G2 82 82 G2: 150 P8 G1: 200 Deadline: 110 Scheduling and Communication Synthesis for Distributed Real-Time Systems Paul Pop 19 of 30 June 14, 2000 Average Percentage Deviation [%] Experimental Results 100 Cost function: degree of schedulability 80 Ignoring Conditions 60 Conditions Separation 40 Relaxed Tightness 1 20 Relaxed Tightness 2 Brute Force 0 80 160 240 320 400 Number of processes Scheduling and Communication Synthesis for Distributed Real-Time Systems Paul Pop 20 of 30 June 14, 2000 Experimental Results (Cont.) Average execution time [s] 450 Brute Force 360 270 180 Ignoring Conditions Relaxed Tightness 2 Conditions Separation Relaxed Tightness 1 90 0 80 160 240 320 400 Number of processes Scheduling and Communication Synthesis for Distributed Real-Time Systems Paul Pop 21 of 30 June 14, 2000 Scheduling of Messages over TTP messages are dynamically produced by the processes frames are statically determined by the MEDL m1 S0 m2 Round 1 S1 m3 m4 Round 2 m5 Round 3 1. Single message per frame, allocated statically: Static Single Message Allocation (SM) 2. Several messages per frame, allocated statically: Static Multiple Message Allocation (MM) 3. Several messages per frame, allocated dynamically: Dynamic Message Allocation (DM) 4. Several messages per frame, split into packets, allocated dynamically Dynamic Packets Allocation (DP) Scheduling and Communication Synthesis for Distributed Real-Time Systems Paul Pop 22 of 30 June 14, 2000 Experimental Results Average Percentage Deviation [%] Cost function: degree of schedulability Ad-hoc 16 Single Message 12 8 Dynamic Message 4 Dynamic Packets 0 Multiple Messages 80 160 240 320 400 Number of processes Scheduling and Communication Synthesis for Distributed Real-Time Systems Paul Pop 23 of 30 June 14, 2000 Optimizing Bus Access (SM and MM) Process p2 misses its deadline! p1 p2 p3 m1 m2 p1 p2 p3 Swapping m1 with m2: all processes meet their deadlines. m2 p1 p2 p3 m1 Putting m1 and m2 in the same slot: all processes meet their deadline, the communication delays are reduced. m1 m2 Scheduling and Communication Synthesis for Distributed Real-Time Systems Paul Pop 24 of 30 June 14, 2000 OptimizeDM OptimizeDM Find the slot sizes that maximize the “degree of schedulability” OptimizeDM: for each node Ni do MinSizeSi = max(size of messages mj sent by node Ni) end for for each slot Si BestSizeSi = MinSizeSi Initialization: the size of a slot in a TDMA round has to accommodate the largest message sent by the corresponding node. Greedy heuristic: finds the local optimum for each slot. for each SlotSize in [MinSizeSi...MaxSize] do calculate the CostFunction if the CostFunction is best so far then BestSizeSi = SlotSizeSi end if Local optimum: find the best size for this slot, the size that leads to the “best so far” cost function. end for sizeSi = BestSizeSi end for end OptimizeDM Scheduling and Communication Synthesis for Distributed Real-Time Systems Paul Pop 25 of 30 June 14, 2000 Experimental Results Average percentage deviations [%] The quality of the greedy optimization heuristics: 2 1,5 OptimizeSM OptimizeMM OptimizeDM OptimizeDP 1 0,5 0 80 160 240 320 400 Number of processes Scheduling and Communication Synthesis for Distributed Real-Time Systems Paul Pop 26 of 30 June 14, 2000 Outline Motivation System Model and Architecture Scheduling and Communication Synthesis Time Driven Systems Event Driven System Real Life Example Conclusions Scheduling and Communication Synthesis for Distributed Real-Time Systems Paul Pop 27 of 30 June 14, 2000 Real Life Example Vehicle cruise controller. Modelled with a CPG of 32 processes and two conditions. Mapped on 5 nodes: CEM, ABS, ETM, ECM, TCM. Time triggered processes: (deadline 400 ms) Ad-hoc: Greedy 1: Greedy 2: SA: 429 ms 314 ms 323 ms 302 ms Event triggered processes: (no messages, deadline 130 ms) Ignoring Conditions: 138 ms Conditions Separation: 132 ms Relaxed Tightness 1, 2: 124 ms Brute Force: 124 ms Scheduling and Communication Synthesis for Distributed Real-Time Systems Paul Pop 28 of 30 June 14, 2000 Conclusions and Future Work Time triggered processes: Extension to static scheduling for CPGs to handle TTP. Improved schedule quality by using new priority function that considers the time triggered protocol. Significant performance improvements can be obtained by optimizing the access to the communication channel. Event triggered processes: Schedulability analysis with the TTP: four message scheduling approaches compared based on the issue of schedulability. Significant improvements to the “degree of schedulability” through the optimization of the bus access scheme. The pessimism of the analysis can be drastically reduced by considering the conditions. Mapping of processes and architecture selection. Scheduling and Communication Synthesis for Distributed Real-Time Systems Paul Pop 29 of 30 June 14, 2000 Contributions Time triggered processes: Static scheduling strategy for systems with both control and data dependencies. Optimization strategies for the synthesis of the bus access scheme. Event triggered processes: Less pessimistic schedulability analysis for hard real-time systems with both control and data dependencies Schedulability analysis for the time-triggered protocol. Optimization strategies for the synthesis of the bus access scheme. Scheduling and Communication Synthesis for Distributed Real-Time Systems Paul Pop 30 of 30 June 14, 2000