2002-10-15
Thesis Overview
High-Level Test Generation
and
=
Built-In Self-Test Techniques
for Digital Systems
=
Gert Jervan
Embedded Systems Laboratory (ESLAB)
Linköping University
=
High-Level Hierarchical
Test Generation
ts
ul
s
Re
al
ns
t
io
en
k
s
u
m
or
cl
ri
W
e
n
p
re
Co
Ex
tu
u
F
Hybrid Built-In
Self-Test Technique
Gert Jervan, IDA/SaS/ESLAB
Test? What Test?
Test and Design for Test of
Digital Systems
2
Licentiate Thesis Presentation
Semiconductor Design Flow
Idea!
Ver
l
eve
l
eve
tL
Cir
cui
el
Verification
Ga
Software Test
Syn
the
sis
RT
Lev
el
Sys
tem
(Webster's Revised Unabridged Dictionary)
DfT
F
ific
atio loorpl
ann
n
ing
...
te L
To prove the truth, genuineness, or quality
of by experiment, or by some principle or
standard.
Lev
=
Validation
Gert Jervan, IDA/SaS/ESLAB
3
Hardware Test
Licentiate Thesis Presentation
Product
Gert Jervan, IDA/SaS/ESLAB
4
Defects
Licentiate Thesis Presentation
Fault Models
=
Single stuck-at (SSA) fault model
Fault model abstraction mechanism for describing defects mathematically
=
stuck-open, bridging, delay, …
Gert Jervan, IDA/SaS/ESLAB
Gert Jervan, IDA/SaS/ESLAB
=
Device level
0 shorts, cracks, leaks,
impurities, bonding, ...
=
Board level
0 component errors,
track errors, ...
=
Functional
=
Wearout/Environment
0 Incorrect design
© IBM
0 temperature,
humidity, vibration,
radiation...
© Gert Jervan
5
Licentiate Thesis Presentation
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Licentiate Thesis Presentation
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2002-10-15
Test Generation
=
Design Flow
Exhaustive tests
System-level specification
2n test patterns for an n-input combinational
circuit
n
2
2n
4
10
20
Architecture exploration
100
~103 ~106 ~1030
=
Pseudorandom tests
=
Deterministic tests
ATPG
Behavioral
Abstract
RTL
Targeted
Gate, etc.
asm,
obj. code
0 Deterministic test generation is
an NP-complete problem!!
Communication
0 Different heuristics
Gert Jervan, IDA/SaS/ESLAB
HW
7
Licentiate Thesis Presentation
SW
Gert Jervan, IDA/SaS/ESLAB
8
Licentiate Thesis Presentation
Hierarchical Test Generation
=
=
=
Combining information
from different levels
of abstraction
Design Flow
Design
System-level specification
Architecture exploration
Top-down and
bottom-up approaches
?
FU
Behavioral
Abstract
RTL
Targeted
Gate, etc.
asm,
obj. code
Shortcomings at the RT-Level:
0 Very long test generation times
ATPG
0 Large designs are not addressed
Communication
0 Requires lots of information about the final
architecture and implementation
Gert Jervan, IDA/SaS/ESLAB
9
Licentiate Thesis Presentation
HW
Gert Jervan, IDA/SaS/ESLAB
Behavioral Level
=
if (IN1 > 0)
X = IN2 + 3;
--- q=1
else {
if (IN2 >= 0)
X = IN1 + IN2; --- q=2
else
X = IN1 * 5;
--- q=3
}
Y = X - 10;
Pure behavior
SW
10
Licentiate Thesis Presentation
High-level Testability
=
0 No allocation
Testability is an attribute of the
implementation
0 No scheduling
0 No assignment
=
Theoretical framework concerning highlevel testability is missing
-------- q=4
X = Y * 2;
OUT = X + Y;
-------- q=6
Gert Jervan, IDA/SaS/ESLAB
© Gert Jervan
No information
about the
structure
11
Licentiate Thesis Presentation
=
Proposed fault models efficiency is
demonstrated only experimentally
Gert Jervan, IDA/SaS/ESLAB
12
Licentiate Thesis Presentation
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2002-10-15
High-level Fault Models
=
Code coverage metrics
0 Path testing (P∞)
High-level Fault Models
=
State coverage
=
Condition coverage
0 Statement testing (P1)
0 Condition failures (stuck-at-true, stuck-atfalse)
0 Branch testing (P2)
=
0
9
15
26
30
31
34
36
38
70
72
75
76
0 Bit failures in variables, signals and ports
(stuck-at-0 and stuck-at-1)
0 Covers statement, branch, condition coverage
and partially path coverage
27
43
48
51
54
=
Gert Jervan, IDA/SaS/ESLAB
Bit coverage
78
13
Licentiate Thesis Presentation
Mutation Fault Model
Gert Jervan, IDA/SaS/ESLAB
14
Hierarchical Test
High-level Test Pattern Generation
=
1
Gap between the fault coverage figures
attained by test sequences generated
purely on a high level and those by the
gate-level ones
X
OUT
0
X
X
if (IN1 > 0)
X=IN2+3;
--- q=1
else {
if (IN2 >= 0)
X=IN1+IN2; -- q=2
else
X=IN1*5; --- q=3
}
X
=
Novel High-level Hierarchical ATPG
0 Combining behavioral level information with
gate-level accuracy
0 Based on hierarchical test generation
approach
Gert Jervan, IDA/SaS/ESLAB
15
Licentiate Thesis Presentation
Testing of Behavior
=
=
=
=
Introduction of control states into the
specification
Conversion of modified specification to
DDs
Test generation based on code coverage
metrics
Employing commercial constraint solver
(SICStus) for solving the constraints
Licentiate Thesis Presentation
Y=X-10;
-------- q=4
X = Y * 2;
OUT=X+Y;
-------- q=6
=
Hierarchical fault model
if (IN1 > 0)
X=IN2+3;
--- q=1
else {
if (IN2 >= 0)
X=IN1+IN2; -- q=2
else
X=IN1*5; --- q=3
}
=
2 test sets
Y=X-10;
X=Y*2;
OUT=X+Y;
Gert Jervan, IDA/SaS/ESLAB
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-------- q=4
-------- q=5
-------- q=6
Licentiate Thesis Presentation
Branch Activation Fault Model
...
if IN1 > 0
X := A;
else
X := B;
...
q
0
q’
IN1>0
1
2
...
X
q’
1
A
2
A≠ B
B
Gert Jervan, IDA/SaS/ESLAB
© Gert Jervan
17
Licentiate Thesis Presentation
Gert Jervan, IDA/SaS/ESLAB
18
Licentiate Thesis Presentation
3
2002-10-15
Testing FUs
=
Testing FUs
Library of FU-s
0 DD models on a structural level
=
=
=
0,1,2,3,4,5
if (IN1 > 0)
X=IN2+3;
--- q=1
else {
if (IN2 >= 0)
X=IN1+IN2; -- q=2
else
X=IN1*5; --- q=3
}
0 VHDL models on a behavioral/structural level
PODEM algorithm for gate-level test
generation (external tool)
“Intelligent” method to handle X values
and constants
Y=X-10;
X=Y*2;
OUT=X+Y;
OUT
q’
OUT’
6
X+Y
1
X
-------- q=4
-------- q=5
-------- q=6
OUT
0
X
Justification and propagation is performed
on a behavioral level
Behavioral Description
X
X
Gate-level netlist
Gert Jervan, IDA/SaS/ESLAB
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Licentiate Thesis Presentation
Gert Jervan, IDA/SaS/ESLAB
Automatic HTG Environment
20
Licentiate Thesis Presentation
Experimental Results
Behavioral VHDL
VHDL2DD
DD Model
FU Library
=
Hierarchical Test Pattern
Generation Environment
Gate-level ATPG
(external tool)
DD2Prolog
Test Cases Generator
Prolog DD model
Test Cases
=
Classical High-level synthesis benchmark
design
Industrial design example (slice of F4)
Constraint Solver Interface
Constraint Solver
(SICStus - external tool)
Yes!
Test Vectors
No!
Gert Jervan, IDA/SaS/ESLAB
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Licentiate Thesis Presentation
Gert Jervan, IDA/SaS/ESLAB
Experimental Results
=
22
Licentiate Thesis Presentation
Experimental Results
DIFFEQ
0
0
0
0
#
#
#
#
of
of
of
of
lines (Behavioral VHDL):
gates:
faults:
untestable faults:
59
4081
16222
384
0 # of detected faults:
0 Test generation time:
15277
468 sec
0 # of unique test vectors:
0 # of applied test vectors:
(includes vectors for reset etc.)
0 Fault efficiency:
(gate-level stuck-at coverage)
199
20896
Gert Jervan, IDA/SaS/ESLAB
© Gert Jervan
23
96.46% / 98.05%
Licentiate Thesis Presentation
High level ATPG
Hierarchical ATPG
FC
[%]
FC
[%]
Len
[#]
CPU
[s]
Len
[#]
CPU
[s]
testgen
FC
[%]
Len
[#]
CPU
[s]
DIFFEQ 1
97.25 553
954 98.05
199
468
99.62
1,177
4,792
DIFFEQ 2
94.57 553
954 96.46
199
468
96,75
923
4,475
• DIFFEQ 1 - optimized for speed
• DIFFEQ 2 - optimized for area
• High level ATPG - Politecnico di Torino
• testgen - Synopsys
Gert Jervan, IDA/SaS/ESLAB
24
Licentiate Thesis Presentation
4
2002-10-15
Hierarchical ATPG
Experimental Results - F4
1
X
OUT
0
VHDL
Lines
[#]
Stuck-at
faults
[#]
F4_Input
Handler_1
175
F4_Output
Handler_1
54
Design
X
CPU
[s]
FC
[%]
Test
length
CPU
[s]
FC
[%]
4872
62
228
64.22%
219
811
38.22%
872
26
1.52
76.26%
170
5
81.30%
X
if (IN1 > 0)
X=IN2+3;
--- q=1
else {
if (IN2 >= 0)
X=IN1+IN2; -- q=2
else
X=IN1*5; --- q=3
}
X
Y=X-10;
-------- q=4
Gate-level ATPG
High-level HTG
Test
length
X = Y * 2;
OUT=X+Y;
------
Gert Jervan, IDA/SaS/ESLAB
-------- q=6
if (IN1 > 0)
X=IN2+3;
--- q=1
else {
if (IN2 >= 0)
X=IN1+IN2; -- q=2
else
X=IN1*5; --- q=3
}
Tested 5616 faults
Untestable 0
Aborted 32
Fault coverage: 99.433428
35 Vectors
Y=X-10;
X=Y*2;
OUT=X+Y;
25
-------- q=4
-------- q=5
-------- q=6
Licentiate Thesis Presentation
Gert Jervan, IDA/SaS/ESLAB
26
Conclusions
=
=
=
Test Application
Hierarchical test generation approach to
incorporate structural information into the
high-level test generation environment
Improved fault coverage compared to the
high-level ATPG
SoC
SRAM
Test Access
Mechanism
27
Peripherial
Component
Interconnect
Wrapper
CPU
SRAM
Core
Under
Test
Sink
DRAM
UDL
Gert Jervan, IDA/SaS/ESLAB
Built-In Self-Test
28
=
Circuitry Under Test
CUT
Fault Coverage (%)
BIST
Control Unit
Typically TPG & TRA
are implemented as
linear feedback shift
registers (LFSR)
Licentiate Thesis Presentation
Problems with BIST
Progressive Coverage of Test Patterns
=
Need for on-chip
test: Appearance of
Built-In Self-Test
(BIST)
=
Test Access
Mechanism
MPEG
Licentiate Thesis Presentation
Test Pattern Generation (TPG)
Support from ATE
=
ROM
Source
Reduced test generation time and test
length compared to the gate-level ATPG
Gert Jervan, IDA/SaS/ESLAB
Licentiate Thesis Presentation
=
LFSR generated
vectors are
pseudorandom by
their nature
Pseudorandom
vectors:
0 Very long test
application time
Test Response Analysis (TRA)
0 Not guaranteed high
fault coverage
0 Area overhead
Number of Test Patterns
0 Additional delay
Gert Jervan, IDA/SaS/ESLAB
© Gert Jervan
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Licentiate Thesis Presentation
Gert Jervan, IDA/SaS/ESLAB
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Licentiate Thesis Presentation
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2002-10-15
Problems with BIST
=
100%
Possible solution:
Related Work
=
Fault Coverage
Combination of
pseudorandom test
and deterministic test
to form a Hybrid
BIST solution in
order to:
0 increase the fault
coverage
Improvement of pseudorandom test set
0 Multiple seed
• Hellebrand et. al (ITC’92, JETTA 98)
• Zacharia et. al (VTS’95)
0 Bit-flipping
• Touba et. al (ITC’95), Chatterjee et. al (VTS’95)
=
Minimization of test time
• Sugihara et. al (DATE 2000)
0 reduce the test
cost
Time
Gert Jervan, IDA/SaS/ESLAB
31
Licentiate Thesis Presentation
Gert Jervan, IDA/SaS/ESLAB
32
Licentiate Thesis Presentation
Objective
=
Hybrid BIST
Existing approaches:
Max. fault
coverage
0 To reduce the test application time
Optimal!
0 To improve the fault coverage
ATPG
0 Test cost minimization has not been addressed
directly
=
Our objective:
0 Optimal balance between pseudorandom and
deterministic test patterns in terms of time
and memory without losing in fault coverage
Gert Jervan, IDA/SaS/ESLAB
33
Licentiate Thesis Presentation
PRG
Time
Time
Time
(1)
(2)
(3)
Gert Jervan, IDA/SaS/ESLAB
34
Licentiate Thesis Presentation
LFSR Emulation
Hardware Based Hybrid BIST Architecture
ROM
Different
Approaches
SoC
...
...
Core
PRPG
...
.
.
.
SoC
CPU Core
ROM
LFSR1: 001010010101010011
N1: 275
load (LFSRj);
for (i=0; i<Nj; i++)
...
end;
LFSR2: 110101011010110101
N2: 900
...
BIST Controller
...
CUT
Core j
Core j+1
Core j+...
MISR
Gert Jervan, IDA/SaS/ESLAB
© Gert Jervan
35
Licentiate Thesis Presentation
Gert Jervan, IDA/SaS/ESLAB
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Licentiate Thesis Presentation
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2002-10-15
ATPG based approach
Cost Calculation for Hybrid BIST
Total Cost CTOTAL
Cost of
pseudorandom test
patterns CGEN
Number of remaining
faults after applying k
pseudorandom test
patterns rNOT(k)
Cost of stored
test CMEM
CTOTAL = αL + βS = CGEN + CMEM
Gert Jervan, IDA/SaS/ESLAB
37
Total Cost CTOTAL
Number of remaining
faults after applying k
pseudorandom test
patterns rNOT(k)
Number of pseudorandom
test patterns applied, k
Licentiate Thesis Presentation
+
++
+
++
+
++
++ ++++
+
++ +++++++++
+
+
++
Gert Jervan, IDA/SaS/ESLAB
Fault Table Based Approach
Cost of
pseudorandom test
patterns CGEN
Cost of stored
test CMEM
Number of pseudorandom
test patterns applied, k
38
Licentiate Thesis Presentation
Cost Calculation for Hybrid BIST
Max. achievable
fault coverage
Deterministic test set T
Fault table FT
R-RL
=> new FT
Static compaction of test set T
Length L
All detectable faults R
Set of faults RL
Gert Jervan, IDA/SaS/ESLAB
Pseudorandom
test sequence TL
39
Licentiate Thesis Presentation
Gert Jervan, IDA/SaS/ESLAB
40
Licentiate Thesis Presentation
Tabu search
Cost Calculation for Hybrid BIST
=
=
=
=
Iterative heuristic technique for
optimization
Gives good near-optimal solution
Applies restrictions (“tabus”) to avoid
local optima
Takes into account history
Tabu Search to minimize the
number of iterations
Gert Jervan, IDA/SaS/ESLAB
© Gert Jervan
41
Licentiate Thesis Presentation
Gert Jervan, IDA/SaS/ESLAB
42
Licentiate Thesis Presentation
7
2002-10-15
Experimental results
100
=
List size: 3
90
=
V*=4
Step size: 3% of
effective clocks
80
35
=
30
=
25
Experimental Results
70
E=7
60
50
20
=
15
10
Accuracy of the
final result at least
97,2%
40
30
20
5
10
0
0
c432
c499
c880
c1355
c1908
c2670
c3540
c5315
c6288
Deterministic
C432
c7552
C499
C880
C1355
C1908
Pseudorandom
C2670
Acceleration of search speed by using Tabu search
C3540
C5315
C6288
C7552
Percentage of the test vectors in the optimized test set compare to the original test set
Gert Jervan, IDA/SaS/ESLAB
43
Licentiate Thesis Presentation
Gert Jervan, IDA/SaS/ESLAB
Experimental Results
100
Pseudorandom Test Cost
Deterministic Test Cost
Hybrid BIST Cost
80
70
=
60
50
40
Licentiate Thesis Presentation
Conclusions - Hybrid BIST
=
90
44
=
30
20
Hybrid BIST solution which combines
pseudorandom and deterministic test
patterns in cost effective way
The BIST area overhead can be reduced
by implementing some of the required test
structures in software
Hybrid BIST approach can lead to the
significant reduction of test length without
losing in the fault coverage
10
0
C432
C499
C880
Gert Jervan, IDA/SaS/ESLAB
C1355
C1908
45
C2670
C3540
C5315
C6288
C7552
Licentiate Thesis Presentation
Gert Jervan, IDA/SaS/ESLAB
46
Conclusions
=
A novel high-level hierarchical ATPG
0 Testability evaluation at early stages of the
design flow
Licentiate Thesis Presentation
Future Work
=
Testability of HW/SW systems
=
High-level fault models
=
Hybrid BIST for sequential circuits
=
Self-test methods for other fault models
0 Efficient test patterns for manufacturing test
=
Hybrid BIST scheme
0 Optimal combination between pseudorandom
and deterministic test patterns
0 Method for test cost minimization
Gert Jervan, IDA/SaS/ESLAB
© Gert Jervan
47
Licentiate Thesis Presentation
Gert Jervan, IDA/SaS/ESLAB
48
Licentiate Thesis Presentation
8