P
Power
Constrained
C
t i d Test
T t Scheduling
S h d li
ffor
3D Stacked
St k d Chips
Chip
B t SenGupta
Breeta
S G t
U b Ingelsson
Urban
I
l
Erik
E ik Larsson
L
{breeta sengupta
{{breeta.sengupta,
g p urban.ingelsson,
urban ingelsson
g
erik larsson}@liu
erik.larsson}@liu.se
}@ se
Linkopings
p g University,
University
y, Sweden
Introduction :-
Purpose ::™
™
™
™
Schedule core tests for stacked 3D chips
Minimize the Test Application Time (TAT)
A maximum
i
power limitation
p
li it ti
The cost of control lines is considered
¾Two stages
¾Wafer sort
¾Fi l ttestt
¾Final
¾Single schedule
Test Scheduling Modes ::Pre-bond
Pre
bond and postpost
bond test schedule
PreBond Chip2
T4
T1
T4
T1
T2
T5
T3
0
T2
3D Stacked Chip Testing
T5
T3
T6
C1
C1+C2
TSP
¾ Pre-bond
Pre bond test schedules of each chip are performed serially
in post
post-bond
bond
¾ Minimizing
Mi i i i pre-bond
b d requirement
i
t ffor control
t l lines
li
for
f each
h
chip the overall number of control lines remain at a minimum
chip,
Chi 1
Chip1
PreBond Chip2
T1
T1
T2
T5
T3
Core2
Core4
Core5
BIST
engine
BIST
engine
BIST
engine
BIST
engine
T4
T2
BIST
engine
i
C1
Chip2
TPO
C1+C2
PreBond Chip2
PostBond Chip1 + Chip2
¾In post
post-bond,
bond power compatible sessions of pre-bond
pre bond are
performed concurrently
¾The number of sessions for each chip still remains the same
same,
hence the number of control lines required also remain at a
minimum,
i i
the
th same as SP
0
T5
T6
T1
T2
T5
T3
0
T5
T6
T2
T3
T4
C1+C2’
C1
TRS
TPO
C1
T6
C1+C2
C1
C2
T2
T3
T5
T6
TSP
Principle :-
Pmax
T1
T1
T2
P ti l Overlap
Partial
O
l p (PO)
( )
T4
T4
TSP
T3
PreBond Chip2
C1
Chip2
Core6
PreBond Chip1
T1
PreBond Chip1
Time
Chip1
BIST
engine
i
T4
0
T3
P
Pmax
T5
T3
T6
T2
Test
Controller
Core3
T6
0
Core1
Test
Controller
Pmax
T4
T1
¾Two stages
¾Pre bond (individual chips)
¾Pre-bond
¾Post-bond
¾Post
bond (all chips combined)
¾M ltipl schedules
¾Multiple
h d l
T6
S i l Processing
Serial
P
i g (SP)
( )
PreBond Chip1
Po
owe
er
P
Pmax
Pmax
PreBond Chip1
Final Test
Wafer
W f Sort
S t
Non
N Stacked
St k d Chip
Chip Testing
T ti g
TSP
ReScheduling (RS)
¾ Sessions are split in pre
pre-bond
bond, such that they can be performed
concurrently
tl with
ith sessions
i
off other
th chips
hi in
i post-bond,
t b d th
thus
reducing the overall test time
¾ Each
E h split
plit off session
i requires
q i
an additional
dditi
l control
t l line
li
Pre‐bond tests in SP are scheduled as per: V. Muresan
Pre
bond tests in SP are scheduled as per: V Muresan et al. Greedy Tree Growing Heuristics on Block‐Test et al Greedy Tree Growing Heuristics on Block Test
S h d li U d P
Scheduling Under Power Constraints, JETTA, 2004. C t i t JETTA 2004
The main objective of the algorithm implemented for ReScheduling are:
¾ Minimum number of splitting of sessions (wrt SP test
schedules)
h d l )
This helps in keeping the number of control lines to a
minimum.
i i
¾ The minimum TAT is accepted which has an acceptable
number of control lines
Th objective
The
bjj ti iis attained
tt i d by:
by
¾ Considering two pre-bond sessions at a time
time, which
belong
g to two different
ff
chips
p
This preserves the sessions defined by SP to the
maximum possible extent, since all tests in the stack are
not considered individually
¾ Reductions in test time for all possible session pairs is
calculated
l l t d and
d ttabulated,
b l t d, TATRS is
i obtained
bt i d b
by
y maximizing
i i i g
the sum of the time reductions by mutually exclusive
session pairs,
p
, from the table.
Th problem
The
bl
has
h a large
l g solution
l ti space, h
hence a greedy
g dy heuristic
h i ti was
applied which has a overall complexity of O(N log N) for N sessions
applied,
Experimental
Results
E p i
t lR
lt :Chip1
Chip2
Chip1 & Chip2
TAT
Pre-bond Test
Pre-bond Test
Post-Bond Test
Pre-bond + Post-bond
TSP
TPO
TRS R (%)
Z
300
300
300
0
TSP
TPO
TRS R (%) TSP
TPO
TRS R (%) TSP
Z
300
300
300
560
560
1200 1160 1160
3.3
0 ((6))
L
1374 1374 1374
0
L
1374 1374 1592 -15.9
15 9 2748 2107 1592 42.1
42 1 5496 4855 4558
17 1
17.1
3 (36)
102
1.9
20 (10)
M
26
26
27
-3.8
M
Z
300
300
300
0
L
Z
300
300
300
0
M*
M
L
1374 1374 1374
0
26
26
27
0
-3.8
600
52
52
48
6.7
7.7
104
TPO
104
TRS
Incr. in
Incr
control
lines
R (%) %(orig)
1374 1374 1374
0
1674 1374 1374 17.9 3348 3048 3048
9.0
0 ((16))
520
520
0
820
1640 1600 1600
24
2.4
0 (8)
M** 1040 1040 1040
0
2414 1824 1824 24.4
24 4 4828 4238 4238
12 2
12.2
0 (18)
520
780
780
49
4.9
Z: ASIC Z
Z
Z, L
L: System
S t
L,
L M:Muresans’
MM
’ Design
D i ; SP:
SP Serial
S i l Processing,
P
i
PO:
PO Partial
P ti l Overlap,
O l
RS:
RS
R S h d li
ReScheduling,
R
R: Reduction
R d ti (test
(t t time)
ti )
RS shows significant
g
test time reductions wrt SP and PO
Conclusions ::
™ Testing of stacked 3D chips is different from non
non-stacked
stacked
chip testing, as the same test schedule does not hold
good in pre-bond
pre bond and post
post-bond
bond stages
™ Splitting of sessions ⇒ Increase in Number of Control
Li
Lines
⇒ Increased
I
d Cost
C t
™ ReScheduling focuses on minimal splitting of pre-bond
sessions
i
™ Experimental results depict up to 42% reduction in post
postbond test time and 17% in overall test time