EEPROM
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8 6 7 2 3 4 5 1 REVISIONS TP1 V_CORE GRN REV DESCRIPTION DATE APPROVED 0.1UF DNI C15 C9 C13 P 47UF 470UF N DGND A DGND R12 BLU MISO DNI MOSI ADE7913DUT_REF TP15 0.1UF C21 DNI DGND DGND DGND GND C 4 DGND DGND AT24C64D-SSHM-T DGND DL4001-TP 10UF DNI C14 0.1UF DNI DGND D4 WP SDA DGND SCLK V_ADE VDD VIOLET A C11 CSB IPIN V1PIN CSB_A 0 N C RED CLKORDYB_A CLKODRDYB AGND_ADC1 IMIN P TP14 WHT 1/2 AA BT1 TP13 DNI DNI VCC 1 A0 2 A1 3 5 A2 SDA 6 SCL 7 V_CORE C U7 8 SCL WP DL4001-TP A TP12 D3 DNI 120OHM DNI GRN AGND_A C18 C16 DGND DGND TP11 0.1UF DL4001-TP 10UF DNI 470UF P 0.1UF C12 DNI C10 DGND 2 V_ADE 1 C C19 DNI 10UF XTAL2 A E1 0.1UF XTAL1 D2 DNI C17 V2PIN DGND DGND DNI TP10 DGND DL4001-TP V_ADE EXLVL A SCLK DNI V1PIN DGND 1 BLK 1 V_EXT DNI OUT ADJ DNI C8 MOSI ADE7913DUT_REF VDD VIOLET 1 12V MISO P CSB IPIN RED CLKORDYB_B CSB_B 47UF BLU 0.1UF +V_MTR +V CLKODRDYB V_CORE LM1117MP-3.3/NOPB VR1 DNI 4 3 OUT1 2 IN D1 0 AGND_ADC1 IMIN EEPROM VDD_MCU 0 CLKORDYB_B N TP9 RED DNI R17 B TP8 DGND1 CLKORDYB_A 0 DNI R3 GRN WHT DGND1 D R2 AGND_B TP7 DGND1 C XTAL2 TP6 DGND 1 DGND1 DNI XTAL1 0.1UF V2PIN C6 VIOLET DNI D TP5 DGND1 DGND1 V3P3_RS485 P V_ADE VDD DNI 4 OUT1 IN 2 OUT ADJ N SCLK N V1PIN TP24DNI 1 WHT 10K BLU 12V MOSI SCLK MOSI ADE7913DUT_REF 1 MISO MISO 2K TP4 CSB IPIN R10 RED 3 R11 TP3 CLKORDYB_C CSB_C CLKODRDYB AGND_ADC1 IMIN DNI WHT 1 TP2 VR2 DNI TP25 ORG GND C7 C 10K R9 AGND_C DNI LM1117MP-3.3/NOPB V2PIN C XTAL1 XTAL2 Y1 2 4.096MEGHZ 22PF C2 22PF C1 1 DGND 2K R14 DNI V_EXT SFH6186-3T DNI U4 B RXD6 4 A B 1 V3P3_RS485 DNI 3 C R16 2 DGND 1K 2 3 C 1K 4 DNI CF3 R8 2 C 3 1K 1 WHT A C5 1 1 WHT U3 V_EXT 5 DGND1 DNI DNI 1 WHT C22 P N 1 WHT DNI TP26 DNI TP27 15UF V3P3_RS485 FOOT PRINT ONLY DGND1 RS485 0.1UF TP18 10K GND 10K 6 7 R18 DNI A B 3 DE 4 DI CR1 A C 2 RE_N SMA6J5.0A-TR DNI 3 1 DNI DGND1 A SFH6186-3T DNI DNI 0.1UF A C RO DNI TP20 R7 C4 DNI CF2 DNI TP21 4 A 1 WHT 1 DNI U2 V_EXT 2 SFH6186-3T 1 WHT DNI CF3 0.1UF CF2 CF1 R13 U6 DNI 8 DNI C20 1K TP19 3 C ADM487EARZ VCC SFH6186-3T TP22 2 4 1K TP23 R6 1 WHT DNI DNI CF1 1 WHT A C3 DNI 4 0.1UF 1 A DNI R15 80.6 R5 DNI DS3 DS2 LNJ208R8ARA (RED) 80.6 R4 DNI LNJ208R8ARA (RED) 80.6 DS1 TXD6 U1 V_EXT 1 DNI DNI C DNI CF OPTO A C C DNI A A LNJ208R8ARA (RED) R1 DNI U5 V_EXT V3P3_RS485 V3P3_RS485 10K DNI DNI R19 V_EXT DNI AN A LO G DE V CES DNI SCHEMATIC HW TYPE: Customer Evaluation Board AD37913 SFH6186-3T THIS DRAWING IS THE PROPERTY OF ANALOG DEVICES INC. IT IS NOT TO BE REPRODUCED OR COPIED, IN WHOLE OR IN PART, OR USED IN FURNISHING INFORMATION TO OTHERS, DESIGN VIEW REV DRAWING NO. <DESIGN_VIEW> D 02-033799 OR FOR ANY OTHER PURPOSE DETRIMENTAL TO THE INTERESTS OF ANALOG DEVICES. PTD ENGINEER SIZE SCALE D SMITH D 1:1 THE EQUIPMENT SHOWN HEREON MAY BE PROTECTED BY PATENTS OWNED OR CONTROLLED BY OWNED ANALOG DEVICES. 8 7 6 5 4 3 2 SHEET 1 2 OF 8 8 6 7 2 3 4 5 1 REVISIONS REV DNI P3 DGND DGND 0.1UF C30 DNI MOLEX22-03-2031 D V_CORE S1 10K R42 DNI B3S1000 TSW-106-08-G-D KEYWAKE S2 DNI KEYPRG 10K DNI R41 DGND 3 4 V_CORE 1 2 3 B3S1000 P2 1 2 3 4 V_EXT DNI P4 3 4 DGND V_CORE DGND 1 2 1 2 10K 10K DNI R27 DGND DNI R26 TDO DNI TCK TSW-104-08-G-S V_CORE DGND DGND SCL SDA TSW-110-08-G-D EXLVL DGND K24A TP50 1 DNI CSB_C CSB_B CSB_A TMS 0.47UF TDI SERIAL DOWNLOAD PORT NEED TO VERIFY PIN OUT DNI C27 TRST DGND 1 2 3 4 5 6 7 8 9 10 11 12 V_CORE SCL SDA COMM 38KHZ ALARM TXD_IR RXD_IR CF1 DNI 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 0.1UF P1 C28 DNI 0.1UF C24 DNI DNI 100K 100K R22 DNI R21 DNI 100K V_CORE R20 DNI APPROVED DATE LCD CONNECTOR JTAG PORT D DESCRIPTION DNI 10K 1 K24A S 2 10K DGND R30 FDV301N FDV301N 2 10K S DNI 10K DNI R29 DNI C29 1 G CF3_B 1 G CF2_B 2 3 D Q3 3 D Q2 R43 R28 DNI CF1_B DNI DNI 3 D Q1 1 G DNI 1 DNI FDV301N DGND DGND DGND ADUC7026BSTZ DGND DGND DGND DNI 1 DNI AN A LO G DE V CES TP41 K24A 1 DNI TP40 K24A 1 DNI A TP39 K24A 1 DNI TP37 K24A 1 DNI K24A TP36 DNI DNI TP34 K24A 1 0.47UF 1 CF3 TP44 DNI S TP33 K24A 1 TP32 K24A 1 DGND TP43 DNI V_CORE RESET V_CORE 0.1UF 0.1UF C31 1 K24A CF2 K24A TP38 C25 K24A CF1 1 DNI 67996-416HLF B K24A TP42 P0.6/T1/MRST/PLAO[3]/AE TCK TDO P0.2/ PWM2L/BHE IOGND1 IOVDD1 LVDD DGND P3.0/AD0/PWM0H/PLAI[8] P3.1/AD1/PWM0L/PLAI[9] P3.2/AD2/PWM1H/PLAI[10] P3.3/AD3/PWM1L/PLAI[11] P2.4/PWM0H/MS0 P0.3/TRST/A16/ADCBUSY P2.5/PWM0L/MS1 P2.6/PWM1H/MS2 RST P3.4/AD4/PWM2H/PLAI[12] P3.5/AD5/PWM2L/PLAI[13] IRQ0/P0.4/PWMTRIP/PLAO[1]/MS1 1 DNI DNI TP31 0 DNI DNI 1K K24A R40 TEST DGND TP35 K24A DGND R35 0 1 DNI TP30 A 0 VDD_MCU ALARM 0 R39 DGND RESET DGND 0 R38 0 MOSI TXD_IR RXD_IR KEYWAKE KEYPRG COMM 38KHZ 0 R37 R34 SCLK TEST 21 22 TCK 23 TDO 24 25 26 DNI C26 V_CORE 27 28 29 30 31 32 33 34 TRST 35 36 37 RESET 38 39 CLKORDYB_C 40 DGND R24 DNI BOOT PIN 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 R36 R33 MOSI 10K 1K R23 RXD6 TXD6 0.1UF DNI B C23 DNI TMS TDI 0 V_CORE 0.1UF V_CORE 0 R32 MISO Y2 32.768KHZ DNI TP29 1 K24A WP CF3_B SCLK MISO CF1_B CF2_B CSB_A CSB_B CSB_C DNI TP28 1 K24A P1.2/SPM2/PLAI[2] P1.3/SPM3/PLAI[3] P1.4/SPM4/PLAI[4]/IRQ2 P1.5/SPM5/PLAI[5]/IRQ3 P4.1/AD9/PLAO[9] P4.0/AD8/PLAO[8] IOVDD2 IOGND2 P1.6/SPM6/PLAI[6] P1.7/SPM7/PLAO[0] P2.2/RS/PWM0L/PLAO[7] P2.1/WS/PWM0H/PLAO[6] P2.7/PWM1L/MS3 P3.7/AD7/PWMSYNC/PLAI[15] P3.6/AD6/PWMTRIP/PLAI[14] XCLKI XCLKO P0.7/ECLK/XCLK/SPM8/ PLAO[4] P2.0/SPM9/PLAO[5]/CONVSTART IRQ1/P0.5/ADCBUSY/PLAO[2]/MS0 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 P5 R31 CLKORDYB_C 2 DNI ADC4 ADC5 ADC6 ADC7 ADC8 ADC9 ADC10 GNDREF ADCNEG DAC0/ADC12 DAC1/ADC13 DAC2/ADC14 DAC3/ADC15 TMS TDI P0.1/PWM2H/BLE P2.3/AE P4.6/AD14/PLAO[14] P4.7/AD15/PLAO[15] BM/P0.0/CMPOUT/PLAI[7]/MS2 C ADE7913 EVAL PORT 1 DGND 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 ADC3/CMP1 ADC2/CMP0 ADC1 ADC0 ADC11 DACVDD AVDD2 AVDD1 AGND2 AGND1 DACGND DACREF VREF REFGND P4.5/AD13/PLAO[13] P4.4/AD12/PLAO[12] P4.3/AD11/PLAO[11] P4.2/AD10/PLAO[10] P1.0/T1/SPM0/PLAI[0] P1.1/SPM1/PLAI[1] C V_CORE R25 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 U8 THIS DRAWING IS THE PROPERTY OF ANALOG DEVICES INC. DNI IT IS NOT TO BE REPRODUCED OR COPIED, IN WHOLE OR IN PART, OR USED IN FURNISHING INFORMATION TO OTHERS, SCHEMATIC HW TYPE: Customer Evaluation Board AD37913 DESIGN VIEW REV DRAWING NO. <DESIGN_VIEW> D 02-033799 OR FOR ANY OTHER PURPOSE DETRIMENTAL TO THE INTERESTS OF ANALOG DEVICES. PTD ENGINEER SIZE SCALE D SMITH D 1:1 THE EQUIPMENT SHOWN HEREON MAY BE PROTECTED BY PATENTS OWNED OR CONTROLLED BY OWNED ANALOG DEVICES. 8 7 6 5 4 3 2 SHEET 1 3 OF 8 8 6 7 4 5 2 3 1 REVISIONS REV DESCRIPTION DATE APPROVED THIS IS THE SDP INTERFACE BD THIS ADAPTS THE METROLOGY BD TO THE SDP AS AN EVAL BD SDP INTERFACE D P8 B EEPROM_A0 DNI VDD_SDP_ADE R45 10K RESETB_SDP 0 0 R48 R50 VSS PAD SDA PAD 24LC32A-I/MC R52 100K 1 A0 2 A1 3 A2 4 EEPROM_A0 R46 R51 U9 8 VDD_SDP_ADE VCC 7 WP 6 SCL_SDP SCL 5 SDA_SDP GND GND SDPINTERFACE C P6 CLKORDYB_C_SDP 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 CSB_A_SDP CSB_B_SDP CSB_C_SDP MISO_SDP MOSI_SDP SCLK_SDP RESETB_SDP VDD_SDP_ADE VDD_SDP_ADE VDD_SDP_ADE PPTC082LFBN-RC GND B USB_VBUS 3.3V GND +V2 N 120OHM N 0.1UF 2 VDD_SDP_ADE C33 C34 1 470UF C35 GND 47UF DGND2 1 BLK 1 1 E2 OUT ADJ P 1 RED 12V TP45 LM1117MP-3.3/NOPB VR3 4 3 OUT1 IN 2 RED GND R49 P CLKORDYB_C_SDP SDA_SDP SCL_SDP R47 VDD_SDP_ADE DNI DNI 0.1UF CSB_B_SDP CSB_C_SDP CSB_A_SDP MOSI_SDP MISO_SDP SCLK_SDP DNI C32 C ID EEPROM VDD_SDP_ADE 100K USB_VBUS 120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 FX8-120S-SV(21) 0 5V 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 FX8-120S-SV(21) 100K P8 100K D GND GND GND GND GND A A AN A LO G DE V CES THIS DRAWING IS THE PROPERTY OF ANALOG DEVICES INC. IT IS NOT TO BE REPRODUCED OR COPIED, IN WHOLE OR IN PART, OR USED IN FURNISHING INFORMATION TO OTHERS, SCHEMATIC HW TYPE: Customer Evaluation Board AD37913 DESIGN VIEW REV DRAWING NO. <DESIGN_VIEW> D 02-033799 OR FOR ANY OTHER PURPOSE DETRIMENTAL TO THE INTERESTS OF ANALOG DEVICES. PTD ENGINEER SIZE SCALE D SMITH D 1:1 THE EQUIPMENT SHOWN HEREON MAY BE PROTECTED BY PATENTS OWNED OR CONTROLLED BY OWNED ANALOG DEVICES. 8 7 6 5 4 3 2 SHEET 1 4 OF 8 8 7 6 2 3 4 5 1 REVISIONS REV DESCRIPTION DATE APPROVED D D THIS IS A SECTION OF THE BOARD TO BE SNAPPED OFF DNI K24A TP16 1 DNI K24A TP46 1 DNI K24A TP47 1 TP48 DNI 1 K24A 1 DNI DNI K24A TP51 K24A TP49 DNI 1 P7 CLKORDYB_C_A C DNI P9 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 MOSI_A CSB_A_A CSB_B_A SCLK_A CLKORDYB_C_A CSB_A_A CSB_B_A CSB_C_A CSB_C_A VDD_MCU_A CSB_N_A MISO_A MOSI_A MISO_A CLKORDYB_C_A CLKORDYB_C_A CLKORDYB_C_A SCLK_A RESET_A VDD_MCU_A VDD_MCU_A VDD_MCU_A R44 0 DNI 104352-8 C LEODB25PLURL2 B B A A AN A LO G DE V CES THIS DRAWING IS THE PROPERTY OF ANALOG DEVICES INC. IT IS NOT TO BE REPRODUCED OR COPIED, IN WHOLE OR IN PART, OR USED IN FURNISHING INFORMATION TO OTHERS, SCHEMATIC HW TYPE: Customer Evaluation Board AD37913 DESIGN VIEW REV DRAWING NO. <DESIGN_VIEW> D 02-033799 OR FOR ANY OTHER PURPOSE DETRIMENTAL TO THE INTERESTS OF ANALOG DEVICES. PTD ENGINEER SIZE SCALE D SMITH D 1:1 THE EQUIPMENT SHOWN HEREON MAY BE PROTECTED BY PATENTS OWNED OR CONTROLLED BY OWNED ANALOG DEVICES. 8 7 6 5 4 3 2 SHEET 1 5 OF 8 8 6 7 2 3 4 5 SECONDARY(ISO)SIDE 1 REVISIONS PRIMARY SIDE REV DESCRIPTION DATE APPROVED ANALOG INPUT PER PHASE TEST PROBE POINTS FOR PRIMARY GROUND E1_A 1 2 .033UF C15_A D TS4148 RZ .033UF C12_A DNI DNI C7_A .033UF 0 DNI R4_A E3_A IMIN 1K AGND_ADC 150OHM IN 0 .033UF 2 R20_A C8_A IN 1 R15_A D3_A A C E2_A AGND_ADC1 R8_A TS4148 RZ R3_A 150OHM 51 2 51 D 1 DNI IPIN IN IP C D6_A A R9_A R16_A R21_A 0 1K 0 IM 150OHM E4_A R19_A 330K 330K 330K 0 C AGND_ADC TS4148 RZTS4148 RZ D9_A AD4_AC A C 150OHM V1P NET NAME SWAP TO REFLECT THE NEW SYMBOL YET TO BE CREATED. V1P AND VM 0 TS4148 RZ TS4148 RZ .033UF D2_A D8_A C A C A C9_A 1K R7_A VDDISO GNDISO V2P V1P VM IM IP LDO REF GNDISO TS4148 RZ TS4148 RZ D5_A D10_A A C A C R12_A VM AGND_ADC 1 2 3 4 5 6 7 8 9 10 VDDISO AGND_ADC V2P V1P VM IM IP LDO REF AGND_ADC R11_A 330K 330K 330K 150OHM OUT 0 OUT OUT OUT OUT OUT OUT OUT C VDD CSB SCLK MOSI MISO XTAL2 XTAL1 CLKODRDYB GND ADE7913 SUPPLY BYPASS V2P LAYOUT NOTE: KEEP THE VDD BYPASS CAP CLOSE TO DUT PIN19 NOTE:KEEP THE HIGH FREQ BYPASS CAP(0.1UF) CLOSE TO THE DUT PIN .033UF R6_A C10_A R2_A 1K 2 R13_A IN 1 R22_A DGND E5_A V2PIN U1_A 20 GND 19 VDD 18 CS_N 17 SCLK 16 MOSI 15 MISO 14 XTAL2 13 XTAL1 12 CLKOUT_DREADY_N 11 DGND 10UF R10_A 0.1UF C1A_A R5_A C2A_A R1_A TS4148 RZTS4148 RZ D7_A D1_A A C A C 2 .033UF C11_A 1 1K IN R14_A V1PIN B B SUPPLY BYPASS CLOSE TO PIN 9 AGND_ADC C14A_A 4.7UF C13A_A C6A_A 4.7UF C5A_A 0.1UF C4A_A 10UF C3A_A A REF LDO A 0.1UF CLOSE TO PIN 8 VDDISO 0.1UF CLOSE TO PIN 1 AN A LO G DE V CES AGND_ADC LAYOUT NOTE: 1. KEEP THE BYPASS CAP CIRCUITS CLOSE TO THE DUT PINS IN THE FOLLOWING ORDER A.) REF B)LDO C.)VDDISO AND WITH HIGH FREQ. CAPS(0.1UF) CLOSEST AGND_ADC THIS DRAWING IS THE PROPERTY OF ANALOG DEVICES INC. IT IS NOT TO BE REPRODUCED OR COPIED, IN WHOLE OR IN PART, OR USED IN FURNISHING INFORMATION TO OTHERS, SCHEMATIC HW TYPE: Customer Evaluation Board AD37913 DESIGN VIEW <DESIGN_VIEW> PTD ENGINEER SIZE SCALE D SMITH D 1:1 THE EQUIPMENT SHOWN HEREON MAY BE PROTECTED BY PATENTS OWNED OR CONTROLLED BY OWNED ANALOG DEVICES. 7 6 5 D 02-033799 OR FOR ANY OTHER PURPOSE DETRIMENTAL TO THE INTERESTS OF ANALOG DEVICES. 8 REV DRAWING NO. 4 3 2 SHEET 1 6 OF 8 8 6 7 2 3 4 5 SECONDARY(ISO)SIDE 1 REVISIONS PRIMARY SIDE REV DESCRIPTION DATE APPROVED ANALOG INPUT PER PHASE TEST PROBE POINTS FOR PRIMARY GROUND E1_B 1 2 .033UF C15_B D TS4148 RZ .033UF C12_B DNI DNI C7_B .033UF 0 DNI R4_B E3_B IMIN 1K AGND_ADC 150OHM IN 0 .033UF 2 R20_B C8_B IN 1 R15_B D3_B A C E2_B AGND_ADC1 R8_B TS4148 RZ R3_B 150OHM 51 2 51 D 1 DNI IPIN IN IP C D6_B A R9_B R16_B R21_B 0 1K 0 IM 150OHM E4_B R19_B 330K 330K 330K 0 C AGND_ADC TS4148 RZTS4148 RZ D9_B AD4_BC A C 150OHM V1P NET NAME SWAP TO REFLECT THE NEW SYMBOL YET TO BE CREATED. V1P AND VM 0 TS4148 RZ TS4148 RZ .033UF D2_B D8_B C A C A C9_B 1K R7_B VDDISO GNDISO V2P V1P VM IM IP LDO REF GNDISO TS4148 RZ TS4148 RZ D5_B D10_B A C A C R12_B VM AGND_ADC 1 2 3 4 5 6 7 8 9 10 VDDISO AGND_ADC V2P V1P VM IM IP LDO REF AGND_ADC R11_B 330K 330K 330K 150OHM OUT 0 OUT OUT OUT OUT OUT OUT OUT C VDD CSB SCLK MOSI MISO XTAL2 XTAL1 CLKODRDYB GND ADE7913 SUPPLY BYPASS V2P LAYOUT NOTE: KEEP THE VDD BYPASS CAP CLOSE TO DUT PIN19 NOTE:KEEP THE HIGH FREQ BYPASS CAP(0.1UF) CLOSE TO THE DUT PIN .033UF R6_B C10_B R2_B 1K 2 R13_B IN 1 R22_B DGND E5_B V2PIN U1_B 20 GND 19 VDD 18 CS_N 17 SCLK 16 MOSI 15 MISO 14 XTAL2 13 XTAL1 12 CLKOUT_DREADY_N 11 DGND 10UF R10_B 0.1UF C1A_B R5_B C2A_B R1_B TS4148 RZTS4148 RZ D7_B D1_B A C A C 2 .033UF C11_B 1 1K IN R14_B V1PIN B B SUPPLY BYPASS CLOSE TO PIN 9 AGND_ADC C14A_B 4.7UF C13A_B C6A_B 4.7UF C5A_B 0.1UF C4A_B 10UF C3A_B A REF LDO A 0.1UF CLOSE TO PIN 8 VDDISO 0.1UF CLOSE TO PIN 1 AN A LO G DE V CES AGND_ADC LAYOUT NOTE: 1. KEEP THE BYPASS CAP CIRCUITS CLOSE TO THE DUT PINS IN THE FOLLOWING ORDER A.) REF B)LDO C.)VDDISO AND WITH HIGH FREQ. CAPS(0.1UF) CLOSEST AGND_ADC THIS DRAWING IS THE PROPERTY OF ANALOG DEVICES INC. IT IS NOT TO BE REPRODUCED OR COPIED, IN WHOLE OR IN PART, OR USED IN FURNISHING INFORMATION TO OTHERS, SCHEMATIC HW TYPE: Customer Evaluation Board AD37913 DESIGN VIEW <DESIGN_VIEW> PTD ENGINEER SIZE SCALE D SMITH D 1:1 THE EQUIPMENT SHOWN HEREON MAY BE PROTECTED BY PATENTS OWNED OR CONTROLLED BY OWNED ANALOG DEVICES. 7 6 5 D 02-033799 OR FOR ANY OTHER PURPOSE DETRIMENTAL TO THE INTERESTS OF ANALOG DEVICES. 8 REV DRAWING NO. 4 3 2 SHEET 1 7 OF 8 8 6 7 2 3 4 5 SECONDARY(ISO)SIDE 1 REVISIONS PRIMARY SIDE REV DESCRIPTION DATE APPROVED ANALOG INPUT PER PHASE TEST PROBE POINTS FOR PRIMARY GROUND E1_C 1 2 .033UF C15_C D TS4148 RZ .033UF C12_C DNI DNI C7_C .033UF 0 DNI R4_C E3_C IMIN 1K AGND_ADC 150OHM IN 0 .033UF 2 R20_C C8_C IN 1 R15_C D3_C A C E2_C AGND_ADC1 R8_C TS4148 RZ R3_C 150OHM 51 2 51 D 1 DNI IPIN IN IP C D6_C A R9_C R16_C R21_C 0 1K 0 IM 150OHM E4_C R19_C 330K 330K 330K 0 C AGND_ADC TS4148 RZTS4148 RZ D9_C AD4_CC A C 150OHM V1P NET NAME SWAP TO REFLECT THE NEW SYMBOL YET TO BE CREATED. V1P AND VM 0 TS4148 RZ TS4148 RZ .033UF D2_C D8_C C A C A C9_C 1K R7_C VDDISO GNDISO V2P V1P VM IM IP LDO REF GNDISO TS4148 RZ TS4148 RZ D5_C D10_C A C A C R12_C VM AGND_ADC 1 2 3 4 5 6 7 8 9 10 VDDISO AGND_ADC V2P V1P VM IM IP LDO REF AGND_ADC R11_C 330K 330K 330K 150OHM OUT 0 OUT OUT OUT OUT OUT OUT OUT C VDD CSB SCLK MOSI MISO XTAL2 XTAL1 CLKODRDYB GND ADE7913 SUPPLY BYPASS V2P LAYOUT NOTE: KEEP THE VDD BYPASS CAP CLOSE TO DUT PIN19 NOTE:KEEP THE HIGH FREQ BYPASS CAP(0.1UF) CLOSE TO THE DUT PIN .033UF R6_C C10_C R2_C 1K 2 R13_C IN 1 R22_C DGND E5_C V2PIN U1_C 20 GND 19 VDD 18 CS_N 17 SCLK 16 MOSI 15 MISO 14 XTAL2 13 XTAL1 12 CLKOUT_DREADY_N 11 DGND 10UF R10_C 0.1UF C1A_C R5_C C2A_C R1_C TS4148 RZTS4148 RZ D7_C D1_C A C A C 2 .033UF C11_C 1 1K IN R14_C V1PIN B B SUPPLY BYPASS CLOSE TO PIN 9 AGND_ADC C14A_C 4.7UF C13A_C C6A_C 4.7UF C5A_C 0.1UF C4A_C 10UF C3A_C A REF LDO A 0.1UF CLOSE TO PIN 8 VDDISO 0.1UF CLOSE TO PIN 1 AN A LO G DE V CES AGND_ADC LAYOUT NOTE: 1. KEEP THE BYPASS CAP CIRCUITS CLOSE TO THE DUT PINS IN THE FOLLOWING ORDER A.) REF B)LDO C.)VDDISO AND WITH HIGH FREQ. CAPS(0.1UF) CLOSEST AGND_ADC THIS DRAWING IS THE PROPERTY OF ANALOG DEVICES INC. IT IS NOT TO BE REPRODUCED OR COPIED, IN WHOLE OR IN PART, OR USED IN FURNISHING INFORMATION TO OTHERS, SCHEMATIC HW TYPE: Customer Evaluation Board AD37913 DESIGN VIEW <DESIGN_VIEW> PTD ENGINEER SIZE SCALE D SMITH D 1:1 THE EQUIPMENT SHOWN HEREON MAY BE PROTECTED BY PATENTS OWNED OR CONTROLLED BY OWNED ANALOG DEVICES. 7 6 5 D 02-033799 OR FOR ANY OTHER PURPOSE DETRIMENTAL TO THE INTERESTS OF ANALOG DEVICES. 8 REV DRAWING NO. 4 3 2 SHEET 1 8 OF 8
