System Design&Methodologies
Fö 11/12- 2
Remember the Design Flow
Informal Specification,
Constraints
System Design&Methodologies
Modeling
Functional
Simulation
Arch. Selection
System model
Formal
Verification
System
architecture
Mapping
Estimation
Scheduling
Fö 11/12- 1
System-Level Power/Energy Optimization
1.
Sources of Power Dissipation
2.
Reducing Power Consumption
3.
System Level Power Optimization
4.
Dynamic Power Management
5.
Mapping and Scheduling for Low Energy
6.
Real-Time Scheduling with Dynamic Voltage Scaling
not OK
Mapped and
scheduled model
not OK
Simulation
Formal
Verification
OK
Softw. model
Softw. Generation
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Hardw. Synthesis
Softw. blocks
Simulation
Testing
OK
Prototype
not OK
Hardw. model
Simulation
Hardw. blocks
Fabrication
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System Design&Methodologies
Fö 11/12- 3
System Design&Methodologies
Why is Power Consumption an Issue?
Fö 11/12- 4
Sources of Power Dissipation in CMOS Devices
dynamic
• Portable systems - battery life time!
static
1
2
P = --- ⋅ C ⋅ V DD ⋅ f ⋅ N SW + Q SC ⋅ V DD ⋅ f ⋅ N SW + I leak ⋅ V DD
2
• Systems with a very limited power budget: Mars Pathfinder,
autonomous helicopter, ...
Switching power
Power required to
charge/discharge
circuit nodes
• Desktops and servers: high power consumption
- raises temperature and deteriorates performance & reliability
Short-circ. power
Dissipation due
to short-circuit
current
Leakage power
Dissipation
due to leakage
current
- increases the need for expensive cooling mechanisms
• One of the main difficulties with developing high performance
chips is heat extraction.
• High power consumption has economical and ecological
consequences.
Petru Eles, IDA, LiTH
C
= node capacitances
NSW = switching activities
(number of gate transitions
per clock cycle)
f
= frequency of operation
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VDD = supply voltage
QSC = charge carried by
short circuit current
per transition
Ileak = leakage current
System Design&Methodologies
Fö 11/12- 5
System Design&Methodologies
Sources of Power Dissipation in CMOS Devices (cont’d)
Fö 11/12- 6
Sources of Power Dissipation in CMOS Devices (cont’d)
CMOS transistor (N-type)
CMOS transistor (N-type)
CMOS inverter
Vdd
drain
drain
Vbs
body
te
Vbs
n
ga
The minimal voltage
required at the gate to
turn on the transistor
dr
ai
-
gate
so
ur
ce
n
ga
dr
ai
so
ur
ce
te
Threshold voltage:
gate
source
source
Vbs = body bias voltage
Vth = threshold voltage
Vdd = supply voltage
CL = output load capacitance
Vbs = body bias voltage
Vth = threshold voltage
Petru Eles, IDA, LiTH
Fö 11/12- 7
-
Charging and discharging the
output load capacitance
Momentary short circuits at a
gate’s output
System Design&Methodologies
Sources of Power Dissipation in CMOS Devices (cont’d)
CMOS transistor (N-type)
Vdd
☞
For long:
• Leakage power has been considered negligible compared to
dynamic.
☞
Today:
• Total dissipation from leakage is approaching the total from
dynamic.
☞
As technology drops below 65nm:
• Leakage power is exceeding dynamic.
n
ga
te
dr
ai
gate It flows even when
body
the voltage at the
gate is below Vth
CL
source
Static power
Vbs = body bias voltage
Vth = threshold voltage
Vdd = supply voltage
CL = output load capacitance
Petru Eles, IDA, LiTH
Fö 11/12- 8
Sources of Power Dissipation in CMOS Devices (cont’d)
CMOS inverter
drain
so
ur
ce
Dynamic power
Petru Eles, IDA, LiTH
System Design&Methodologies
Vbs
CL
body
-
Subthreshold leakage
conduction
Junction leakage (drain
and source to body)
Petru Eles, IDA, LiTH
System Design&Methodologies
Fö 11/12- 9
System Design&Methodologies
Power and Energy Consumption
Sources of Power Dissipation in CMOS Devices (cont’d)
☞ Leakage power is consumed even if the circuit is idle (standby). The
only way to avoid is decoupling from power.
Fö 11/12- 10
1
2
P = --- ⋅ C ⋅ V DD ⋅ f ⋅ N SW
2
1
2
E = P ⋅ t = --- ⋅ C ⋅ V DD ⋅ N CY ⋅ N SW
2
☞ Short circuit power can be around 10% of total.
NCY = number of cycles needed for the particular task.
☞ Switching power is still the main source of power consumption.
For the rest of the discussion, we consider mainly switching
power. At the end we come back to leakage.
Petru Eles, IDA, LiTH
• In certain situations we are concerned about power consumption:
- heath dissipation, cooling:
- physical deterioration due to temperature.
• Sometimes we want to reduce total energy consumed:
- battery life.
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System Design&Methodologies
Fö 11/12- 11
System Design&Methodologies
Reducing Power/Energy Consumption (cont’d)
Reducing Power/Energy Consumption
☞ The main sources:
• Reduce supply voltage
• Reduce switching activity
• Reduce capacitance
• Reduce number of cycles
Petru Eles, IDA, LiTH
Fö 11/12- 12
☞ Circuit level
• Ordering of transistors in gate (influences capacitance).
• Transistor sizing.
☞ Logic level
• Don’t-care optimization to reduce switching activity.
• Reduce spurious switching activity by balancing the delays of
paths that converge at each gate.
• Technology mapping.
• State encoding such that switching activity is minimised: if
state s has a large number of transitions to state q, they
should be given uni-distant codes.
• Encoding to minimise switching activity in arithmetic units or
on the bus.
• Gated clocks: Gate the clocks of circuits (registers, gates,
arithmetic units when they are in idle time periods.
Petru Eles, IDA, LiTH
System Design&Methodologies
Fö 11/12- 13
System Design&Methodologies
Reducing Power/Energy Consumption (cont’d)
Fö 11/12- 14
Reducing Power/Energy Consumption (cont’d)
☞ Architecture level
☞ Behavioral level
• Schedule and map operations so that number of cycles is
minimised (with increased number of switching per clock
cycle)  you can run at slower clock rate  you can reduce
supply voltage.
• Allocate and share modules so that power consumption is
reduced (for example, by reducing switching activity)
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• Specialise instruction set, datapath, register structure to the
particular architecture, with power consumption as an optimization
goal (see flow in Fö. 9).
- You have on the chip and you switch only those resources
(gates) you really need.
• Reduce power consumption on the bus.
- lower switching activity: clever encoding, reduce switching activity on the address bus by exploiting correlations;
- minimise the bus length (capacitance) by optimal module
placement.
- bus segmentation: transform a long heavily loaded global bus
into a partitioned set of local bus segments.
Petru Eles, IDA, LiTH
System Design&Methodologies
Fö 11/12- 15
System Design&Methodologies
Reducing Power/Energy Consumption (cont’d)
Fö 11/12- 16
Reducing Power/Energy Consumption (cont’d)
• Optimise the memory structure.
- Memory transfers are extremely power hungry: a memory
transfer takes 33 times more energy than an addition!
Reducing the number of memory accesses is a very efficient
way to save power!
- Adapt the number of caches, their size and associativity, and
the length of the cache line to the application  reduce
number of memory transfers.
- Interesting trade-off: larger caches consume more power but
reduce number of memory transfers  find the right balance!
Petru Eles, IDA, LiTH
• Provide instruction support for Power management:
- Instructions which allow to put in stand-by or shut down certain
parts of the system.
- Instructions which allow to dynamically fix the supply voltage
(dynamic voltage scaling).
Petru Eles, IDA, LiTH
System Design&Methodologies
Fö 11/12- 17
System Design&Methodologies
Fö 11/12- 18
System Level Power Optimization
Reducing Power/Energy Consumption (cont’d)
☞ System Level
Three techniques will be discussed:
• Static techniques are applied at design time.
- Compilation for low power: instruction selection considering
their power profile, data placement in memory, register
allocation.
- Algorithm design: find the algorithm which is the most powerefficient.
- Task mapping and scheduling.
• Dynamic techniques are applied at run time.
- These techniques are applied at run-time in order to reduce
power consumption by exploiting idle or low-workload periods.
Petru Eles, IDA, LiTH
1. Dynamic power management: a dynamic technique.
2. Task mapping: a static technique.
3. Task scheduling with dynamic power scaling: static & dynamic.
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System Design&Methodologies
Fö 11/12- 19
System Design&Methodologies
Dynamic Power Management (cont’d)
Dynamic Power Management (DPM)
Decisions:
application
power aware OS
hardware
• Switching among multiple power
states:
• idle
• sleep
• run
• Switching among multiple
frequencies and voltage levels.
Goal:
• Energy optimization
• QoS constraints satisfied
Petru Eles, IDA, LiTH
Fö 11/12- 20
Hardware Support (e.g. Intel Xscale Processor)
• RUN: operational
• IDLE: Clocks to the
CPU are disabled;
recovery is through
interrupt.
• SLEEP: Mainly
powered off;
recovery through
wake-up event.
• Other intermediate
states: DEEP
IDLE, STANDBY,
DEEP SLEEP
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0.75V, 60mW
150MHz
1.3V, 450mW
RUN
RUN
600MHz
RUN
1.6V, 900mW
RUN
800MHz
160μs
RUN
10μs
1.5ms
10μs
IDLE
40mW
140ms
90μs
SLEEP
160μW
System Design&Methodologies
Fö 11/12- 21
System Design&Methodologies
The Basic Concept of DPM
Dynamic Power Management (cont’d)
☞ DPM techniques are used in laptops, personal digital assistants
(PDAs), and other portable appliances in order to shut down or
place in stand-by unused devices.
The goal is power saving.
☞ DPM techniques are implemented in the operating system
(including Windows 2000 running on laptops).
☞ The power breakdown for a laptop computer:
- 36% of total power consumed by the display
- 18% by hard-disk
- 18% by wireless LAN interface
- 7% by keyboard, mouse, etc.
- 21% by digital VLSI circuits.
• When there are requests for a device  the device is busy;
otherwise it is idle.
• When the device is idle, it can be shut down to enter a low-power
sleeping state.
Workload Requests
Device state
don’t forget
these!
Power state
Requests
Busy
Busy
Idle
Tsd
Working
Sleeping
Twu Working
?
T1 T2 T3
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T4
Time
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System Design&Methodologies
Fö 11/12- 23
System Design&Methodologies
The Basic Concept of DPM (cont’d)
☞ Changing the power state takes time (several seconds) and extra energy.
• Tsd : shutdown delay
• Twu : wake-up delay
Send the device to sleep only if the saved energy justifies the overhead!
☞ The main Problems:
• Don’t shut down such that delays occur too frequently.
• Don’t shut down such that the savings due to the sleeping are
smaller than the power overhead of the state changes.
Petru Eles, IDA, LiTH
Fö 11/12- 22
Fö 11/12- 24
Power Management Policies
• Power management policies are concerned with predictions
related to idle periods:
- For shut-down: try to predict how long the idle period will be in
order to decide if a shut-down should be performed.
- For wake-up: try to predict when the idle period ends, in order
to avoid user delays due to Twu.
It is quite difficult, and often the wake-up is started simply
when a request has arrived.
• Typical Policies:
1. Time-out
2. Predictive
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System Design&Methodologies
Fö 11/12- 25
System Design&Methodologies
Predictive Policy
Time-out Policy
• Drawback: you waste energy during the period τ (compared to
instantaneous shut-down).
• Policies:
- Fixed time-out period: you set the value of τ, which then stays constant.
- Adjusted at run-time: increase or decrease τ, depending on the
length of previous idle periods.
☞ The length of an idle period is predicted. If the prediction is for an idle
period long enough, the shut-down is performed immediately (no time
interval T1 - T2 on slide 22).
• Example Policy
Shut down after
Idle Period
- L-shaped distribution for ---------------------------------------------------;
Previous Busy Period short busy period!
Short busy periods
are followed by
long idle periods.
Idle Period
☞ It is assumed that, after a device is idle for a period τ (the interval T1 - T2
on slide 22), it will stay idle for at least a period which makes it efficient
to shut down.
Busy periods longer
than a threshold θ
are followed by
short idle periods.
θ
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Busy Period
Attention!
This is just a very particular example for a policy!
it has been proposed for
a very particular application!
Such policies, if they can
be found at all, will differ
very much from application to application.
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System Design&Methodologies
Fö 11/12- 27
System Design&Methodologies
More Advanced Prediction Policies
☞ In the previous example it is assumed that we have a single, known
application running, that we can perform profiling on this application,
and draw a clear conclusion regarding its run-time behaviour (like
expressed by the “L-shape” diagram).
☞ Very often the above assumptions are not true:
• We do not know in advance all application running on the system;
• The behaviour of the applications changes during run-time,
depending on input data.
☞ In such cases more advanced run-time prediction techniques can be
applied like e.g. based on statistics, stochastic modelling, and
machine learning
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Fö 11/12- 26
Fö 11/12- 28
Mapping and Scheduling for Low Energy
☞ For many embedded systems DPM techniques, like presented
before, cannot be applied:
• They have no devices like hard-disk, no (or small) display 
VLSI is a main source of power dissipation.
• They have time constraints  we have to keep deadlines
(usually we cannot afford shut-down and wake-up times).
• The operating system is small  no sophisticated techniques at
run-time.
• The application is known at design time  we know a lot about
the application already at design time.
☞ Static techniques can be used (applied at design time).
Mapping and scheduling for low energy are important!
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System Design&Methodologies
Fö 11/12- 29
System Design&Methodologies
Fö 11/12- 30
Mapping for Low Energy
Mapping for Low Energy (cont’d)
τ1
τ2
τ3
τ5
WCET
Task
τ1
τ2
τ3
τ4
τ5
τ6
τ7
τ8
τ6
τ4
τ7
τ8
μp3
Energy
μp3
μp4
μp3
μp4
5
6
5
3
7
9
8
4
5
6
5
3
8
10
6
4
10
11
8
6
17
21
15
10
10
14
8
7
15
19
14
9
μp4
Consider a mapping:
μp3: τ1, τ3, τ6, τ7, τ8.
μp4: τ2, τ4, τ5.
Execution time: 52;
Time
μp3
Communication times and energy:
C1-2: t = 1; E = 3.
C3-5: t = 2; E = 5.
C4-8: t = 1; E = 3.
C5-7: t = 1; E = 3.
Energy consumed: 75.
0 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 52 54 56 58 60 62 64
τ1
τ3
τ6
τ2
μp4
τ7
τ5
τ8
τ4
bus
C1-2
C3-5
C5-7
C4-8
Bus
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Petru Eles, IDA, LiTH
System Design&Methodologies
Fö 11/12- 31
System Design&Methodologies
Mapping for Low Energy (cont’d)
Consider a mapping:
μp3: τ1, τ3, τ6, τ7.
μp4: τ2, τ4, τ5, τ8.
Execution time: 57;
Time
μp3
Communication times and energy:
C1-2: t = 1; E = 3.
C3-5: t = 2; E = 5.
C7-8: t = 1; E = 3.
C5-7: t = 1; E = 3.
τ3
τ6
τ2
μp4
τ7
τ5
τ4
Mapping for Low Energy (cont’d)
The second mapping with τ8 on μp4 consumes less energy;
Assume that we have a maximum allowed delay = 60.
Energy consumed: 70.
0 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 52 54 56 58 60 62 64
τ1
This second mapping is preferable, even if it is slower!
τ8
bus
C1-2
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C3-5
C5-7
Fö 11/12- 32
C7-8
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System Design&Methodologies
Fö 11/12- 33
Real-Time Scheduling with Dynamic Voltage Scaling
System Design&Methodologies
Fö 11/12- 34
Real-Time Scheduling with Dynamic Voltage Scaling (cont’d)
☞ The energy consumed by a task, due to switching power (slide 6):
1
2
E = --- ⋅ C ⋅ V DD ⋅ N CY ⋅ N SW
2
NSW = number of gate transitions
per clock cycle.
NCY = number of cycles needed
for the task.
• Reducing supply voltage VDD is the most efficient way to reduce
energy consumption.
☞ The frequency at which the processor can be operated depends on VDD:
2
( V DD – V t )
f = k ⋅ --------------------------- , k: circuit dependent constant; Vt: threshold voltage.
V DD
The execution time of the task:
V DD
t exe = N CY ⋅ ---------------------------------2
k ⋅ ( VDD – V t )
The scheduling problem (Fö9/10, slide 8):
Which task to execute at a certain moment on a certain processor so
that time constraints are fulfilled?
The scheduling problem with voltage scaling:
Which task to execute at a certain moment on a certain processor, and
at which voltage level, so that time constraints are fulfilled and energy
consumption is minimised?
☞ The problem: reducing supply voltage extends execution time!
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System Design&Methodologies
Fö 11/12- 35
System Design&Methodologies
Fö 11/12- 36
Variable Voltage Processors
The Basic Principle
We consider a single task τ:
• Several supply voltage levels are available.
• Supply voltage can be fixed by the application (operating system)
through execution of particular instructions.
- total computation: 109 execution cycles.
- deadline: 25 seconds.
- processor nominal (maximum) voltage: 5V.
- energy: 40 nJ/cycle at nominal voltage.
- processor speed: 50MHz (50×106 cycles/sec) at nominal voltage.
V2
• Frequency is adjusted to the current supply voltage.
109 cycles
52
Etotal = 40 J
slack
texe = 20 sec
• Several processors with variable voltage levels are already
available. There will be more and more in the near future.
0
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Petru Eles, IDA, LiTH
5
10
15
20
25
time (sec)
System Design&Methodologies
Fö 11/12- 37
System Design&Methodologies
Fö 11/12- 38
The Basic Principle (cont’d)
The Basic Principle (cont’d)
Let’s make it slower!
• VDD = 4V
- energy: 40×42/52 = 25nJ/cycle.
- speed: 50×4/5 = 40MHz
• VDD = 2.5V
- energy: 40×2.52/52 = 10nJ/cycle.
- speed: 50×2.5/5 = 25MHz
V2
750×106 cycles
V2
250×106 cycles
52
Etotal = 32.5 J
texe = 25 sec
109 cycles
52
Etotal = 25 J
42
texe = 25 sec
2.52
0
5
10
15
20
25
time (sec)
0
Petru Eles, IDA, LiTH
5
15
20
25
time (sec)
Petru Eles, IDA, LiTH
System Design&Methodologies
Fö 11/12- 39
System Design&Methodologies
Fö 11/12- 40
The Basic Principle (cont’d)
☞ If a processor uses a single supply voltage and completes a
program just on deadline, the energy consumption is minimised.
Consider two tasks τ1, τ2:
• Computation
- τ1: 250×106 execution cycles; τ2: 750×106 execution cycles;
• Deadline: 25 seconds.
• Processor nominal (maximum) voltage: 5V.
τ1
• Energy:
- 40 nJ/cycle at nominal voltage.
- 25 nJ/cycle at VDD = 4V.
τ2
• Processor speed:
6
- 50MHz (50×10 cycles/sec) at nominal voltage.
- 40MHz at VDD = 4V.
Petru Eles, IDA, LiTH
10
The Basic Principle (cont’d)
• Find the voltage so that the tasks just meet their deadline  you
have minimised energy consumption!
6
V2 250×10
cycles
750×106 cycles
42
Etotal = 25 J
τ1
0
Petru Eles, IDA, LiTH
τ2
5
10
15
20
25
time (sec)
System Design&Methodologies
Fö 11/12- 41
System Design&Methodologies
Considering Task Particularities
Energy consumed by a task:
1
2
E = --- ⋅ C ⋅ V DD ⋅ N CY ⋅ N SW
2
Considering Task Particularities (cont’d)
NSW = number of gate transitions
per clock cycle.
C = switched capacitance per
clock cycle.
Average energy consumed by task per cycle:
1
2
E CY = --- ⋅ C ⋅ V DD ⋅ N SW
2
☞ Often tasks differ from each other in terms of executed operations
 NSW and C differ from one task to the other.
The average energy consumed per cycle differs from task to task.
Petru Eles, IDA, LiTH
Consider two tasks τ1, τ2:
• Computation
- τ1: 250×106 execution cycles; τ2: 750×106 execution cycles;
• Deadline: 25 seconds.
• Processor nominal (maximum) voltage: 5V.
τ1
• Processor speed:
6
- 50MHz (50×10 cycles/sec) at nominal voltage.
τ2
- 40MHz at VDD = 4V.
- 25MHz at VDD = 2.5V.
•
Energy τ1
- 50 nJ/cycle at VDD = 5V.
- 32 nJ/cycle at VDD = 4V.
- 12.5 nJ/cycle at VDD = 2.5V.
•
Energy τ2
- 12.5 nJ/cycle at VDD = 5V.
- 8 nJ/cycle at VDD = 4V.
- 3 nJ/cycle at VDD = 2.5V.
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System Design&Methodologies
Fö 11/12- 43
System Design&Methodologies
Considering Task Particularities (cont’d)
☞ Here we have a solution with VDD = 4V, and deadline just fulfilled:
Etotal = 32nJ/cycle × 250 × 106cycles + 8nJ/cycle × 750 × 106cycles
V2
Fö 11/12- 42
250×106
cycles
750×106 cycles
Fö 11/12- 44
Considering Task Particularities (cont’d)
☞ Here we run τ1 at VDD = 2.5V, and τ2 at VDD = 5V; the tasks finish
just on deadline.
Etotal = 12.5nJ/cycle × 250 × 106cycles + 12.5nJ/cycle × 750 × 106cycles
V2 250×106 cycles
750×106 cycles
52
42
τ1
0
Petru Eles, IDA, LiTH
Etotal = 12.5 J
Etotal = 14 J
τ2
τ2
5
10
15
2.52
20
25
time (sec)
0
Petru Eles, IDA, LiTH
τ1
5
10
15
20
25
time (sec)
System Design&Methodologies
Fö 11/12- 45
System Design&Methodologies
Fö 11/12- 46
Discrete Voltage Levels
Considering Task Particularities (cont’d)
☞ If power consumption per cycle is not constant (but differs from task
to task), the rule on slide 33 is not true any more.
Voltage levels have to be reduced with priority for those tasks which
have a larger energy consumption per cycle.
☞ One particular voltage level has to be established for each task, so
that deadlines are just satisfied.
☞ Practical microprocessors can work only at a finite number of discrete
voltage levels.
The “ideal” voltage Videal, determined for a certain task does not exist.
☞ A task is supposed to run for time texe at the voltage Videal.
On the particular processor the two closest available neighbours to
Videal are: V1 < Videal < V2.
You have minimised the energy if you run the task for time t1 at
voltage V1 and for t2 at voltage V2, so that t1 + t2 = texe.
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System Design&Methodologies
Fö 11/12- 47
System Design&Methodologies
Scheduling Policies
Fö 11/12- 48
The Pitfalls with Ignoring Leakage
2
☞ The techniques described here, in order to find optimal voltage
levels for real-time tasks, can be applied both with:
E = NC ⋅ C eff ⋅ V dd + L g ⋅ ( V dd ⋅ K 3 ⋅ e
Minimise this and
ignore the rest!
• Static cyclic scheduling
• Priority-based scheduling
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Petru Eles, IDA, LiTH
K 4 ⋅ V dd
⋅e
K 5 ⋅ V bs
+ V bs ⋅ I ju ) ⋅ t
System Design&Methodologies
Fö 11/12- 49
System Design&Methodologies
Fö 11/12- 50
The Pitfalls with Ignoring Leakage
2
E = NC ⋅ C eff ⋅ V dd + L g ⋅ ( V dd ⋅ K 3 ⋅ e
E = NC ⋅ C eff ⋅
2
V dd
+ L g ⋅ ( V dd ⋅ K 3 ⋅ e
K 4 ⋅ V dd
⋅e
K 5 ⋅ V bs
K 4 ⋅ V dd
⋅e
K 5 ⋅ V bs
+ V bs ⋅ I ju ) ⋅ t
+ V bs ⋅ I ju ) ⋅ t
Dynamic decreases
with Vdd regardless
of increased time.
Leakage decreases
with Vdd, but growth
with time!
1. We don’t optimize global energy but only a part of it!
Energy per Cycle
8e-10
70nm technology, Crusoe processor
7e-10
6e-10
5e-10
4e-10
3e-10
Dynamic energy
2e-10
1e-10
2. We can get it even very wrong and increase energy
0
consumption!
0.5 0.55 0.6 0.65 0.7 0.75 0.8 0.85 0.9 0.95
1 Vdd
Jejurikar et. al., DAC’04
Petru Eles, IDA, LiTH
Petru Eles, IDA, LiTH
System Design&Methodologies
Fö 11/12- 51
2
E = NC ⋅ C eff ⋅ V dd + L g ⋅ ( V dd ⋅ K 3 ⋅ e
K 4 ⋅ V dd
⋅e
K 5 ⋅ V bs
+ V bs ⋅ I ju ) ⋅ t
System Design&Methodologies
2
E = NC ⋅ C eff ⋅ V dd + L g ⋅ ( V dd ⋅ K 3 ⋅ e
5e-10
4e-10
3e-10
Dynamic energy
2e-10
1e-10
0
Leakage energy
Energy per Cycle
Energy per Cycle
70nm technology, Crusoe processor
6e-10
7e-10
Jejurikar et. al., DAC’04
Petru Eles, IDA, LiTH
1 Vdd
⋅e
K 5 ⋅ V bs
+ V bs ⋅ I ju ) ⋅ t
6e-10
5e-10
Dynamic + Leakage
4e-10
3e-10
Dynamic energy
2e-10
1e-10
0
0.5 0.55 0.6 0.65 0.7 0.75 0.8 0.85 0.9 0.95
K 4 ⋅ V dd
Critical point!
If you go beyond this
70nm
with technology
Vdd energy grows
8e-10
8e-10
7e-10
Fö 11/12- 52
0.5 0.55 0.6 0.65 0.7 0.75 0.8 0.85 0.9 0.95
Jejurikar et. al., DAC’04
Petru Eles, IDA, LiTH
Leakage energy
1 Vdd
System Design&Methodologies
Fö 11/12- 53
System Design&Methodologies
Summary
• Power consumption becomes a central issue for embedded
systems design.
• Power/energy consumption can be reduced by reducing supply
voltage, switching activity, switched capacitance, number of
executed cycles.
• There are means at all levels of the design to reduce power
consumption: circuit, logic, behavioral, architecture, system level.
• At system level we distinguish dynamic techniques (applied during
run-time) and static techniques (applied at design time).
Petru Eles, IDA, LiTH
Fö 11/12- 54
Summary (cont’d)
• Dynamic power management is implemented by the operating
system, and is mainly used in portable appliances to shut down or
place in stand-by unused devices.
• Typical policies for power management are: time-out, predictive,
and stochastic.
• Both at task mapping and at scheduling, design decisions can be
made with have a huge impact on power/energy consumption.
• Real-time scheduling in the context of processors with voltage
scaling is extremely interesting. The main trade-off is voltage level
vs. execution time. One has to find the optimal voltage levels such
that energy consumption is reduced and deadlines are still
fulfilled.
Petru Eles, IDA, LiTH