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Component Configuration
VHDL
Component Configuration.
The generate statement.
• In order to simulate a VHDL specification, an (entity
declaration / architecture body) pair has to be
associated to component instances.
This binding is called component configuration.
1. Component Configuration
There are three mechanisms provided in VHDL for
component configuration:
1. Default binding (see Fö. 2, slide 14).
2. Configuration specification (see Fö 2, slide 17).
3. Configuration declaration.
2. Configuration Declaration
3. Specification of Regular Structures
4. The generate Statement
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Component Configuration
Component Configuration (cont’d)
Let us consider again the structural specification for the
four bit parity generator:
T1
V(1)
EVEN
T3
V(2)
entity XOR_GATE is
port(X, Y:in BIT; Z:out BIT);
end XOR_GATE;
architecture ARCH_XOR_1 of XOR_GATE is
begin
. . . . . . . . .
end ARCH_XOR_1;
V(0)
V
T2
architecture ARCH_XOR_2 of XOR_GATE is
begin
. . . . . . . . .
end ARCH_XOR_2;
V(3)
entity INV is
port(X:in BIT; Z:out BIT);
end INV;
entity PARITY is
port(V:in BIT_VECTOR(3 downto 0);
EVEN:out BIT);
end PARITY;
architecture ARCH_INV_1 of INV is
begin
. . . . . . . . .
end ARCH_INV_1;
architecture ARCH_INV_2 of INV is
begin
. . . . . . . . .
end ARCH_INV_2;
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Configuration Specification
use WORK.all;
architecture PARITY_STRUCTURAL of PARITY is
component XOR_GATE --component declaration
port(X,Y: in BIT; Z: out BIT);
end component;
component INV
--component declaration
port(X: in BIT; Z: out BIT);
end component;
-- configuration specifications:
for XOR1,XOR2:XOR_GATE use
entity XOR_GATE(ARCH_XOR_1);
for XOR3:XOR_GATE use
entity XOR_GATE(ARCH_XOR_2);
for INV1:INV use
entity INV(ARCH_INV_1);
signal T1, T2, T3: BIT;
begin
-- component instantiation statements:
XOR1: XOR_GATE port map (V(0), V(1), T1);
XOR2: XOR_GATE port map (V(2), V(3), T2);
XOR3: XOR_GATE port map (T1, T2, T3);
INV1: INV port map (T3, EVEN);
end PARITY_STRUCTURAL;
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Configuration Specification (cont’d)
• Component configuration through configuration
specification is static.
The respective architecture body has to be recompiled
whenever we want to simulate with a new binding.
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Configuration Declaration (cont’d)
Configuration Declaration
• Component configuration can be performed outside
the architecture body which instantiates a certain
component.
• A configuration declaration is a design unit which can
be compiled separately.
In a configuration declaration the binding of all
components which are part of a certain entity can be
specified.
• The particular architecture body has not to be
recompiled when the binding is changed.
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use WORK.all;
architecture PARITY_STRUCTURAL of PARITY is
component XOR_GATE --component declaration
port(X,Y: in BIT; Z: out BIT);
end component;
component INV
--component declaration
port(X: in BIT; Z: out BIT);
end component;
signal T1, T2, T3: BIT;
begin
XOR1: XOR_GATE port map (V(0), V(1), T1);
XOR2: XOR_GATE port map (V(2), V(3), T2);
XOR3: XOR_GATE port map (T1, T2, T3);
INV1: INV port map (T3, EVEN);
end PARITY_STRUCTURAL;
use WORK.all;
configuration CONFIG_1 of PARITY is
for PARITY_STRUCTURAL
for XOR1,XOR2:XOR_GATE use
entity XOR_GATE(ARCH_XOR_1);
end for;
for XOR3:XOR_GATE use
entity XOR_GATE(ARCH_XOR_2);
end for;
for INV1:INV use
entity INV(ARCH_INV_1);
end for;
end for;
end CONFIG_1;
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The generate Statement (cont’d)
Specification of Regular Structures.
The generate Statement.
Consider a 4-bit shift register
• The generate statement is an efficient way to specify
designs with a regular structure.
DFFx(0)
A
It provides a mechanism for conditional compilation.
Q
D
Clk
Q
DFFx(1)
Z(1)
D
Q
Clk
Q
DFFx(2)
Z(2)
D
Q
Clk
Q
DFFx(3)
Z(3)
D
Q
Clk
B
Q
Clk
label_id : generation_scheme generate
concurrent_statements
end generate optional_id;
The D flip-flop:
entity DFF is
port(D,CLK:in BIT; Q,QB:out BIT);
end Dff;
• The generation_scheme can be for or if.
architecture DFF_BEHAVIORAL of DFF is
begin
process(CLK)
begin
if CLK=’1’ then
Q <= D after 5ns;
QB <= not D after 5ns;
end if;
end process;
end DFF_BEHAVIORAL;
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The generate Statement (cont’d)
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The generate Statement (cont’d)
The same using a generate statement with a for scheme:
The 4-bit shift register:
entity SHIFT_4 is
port(A,CLK:in BIT; B:out BIT);
end SHIFT_4;
use Work.all;
architecture SHIFT_SIMPLE of SHIFT_4 is
component DFF
port(D,CLK:in BIT; Q,QB:out BIT);
end component;
signal Z: array(1 to 3) of BIT;
begin
DFF1:DFF port map(A,CLK,Z(1),open);
DFF2:DFF port map(Z(1),CLK,Z(2),open);
DFF3:DFF port map(Z(2),CLK,Z(3),open);
DFF4:DFF port map(Z(3),CLK,B,open);
end SHIFT_SIMPLE;
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use Work.all;
architecture SHIFT_GENERATE_1 of SHIFT_4 is
component DFF
port(D,CLK:in BIT; Q,QB:out BIT);
end component;
signal Z: array(0 to 4) of BIT;
begin
Z(0)<=A;
Q1:for I in 0 to 3 generate
DFFx:DFF port map(Z(I),CLK,Z(I+1),open);
end generate;
B<=Z(4);
end SHIFT_GENERATE_1;
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The generate Statement (cont’d)
The generate Statement (cont’d)
Irregularities can be handled using a generate statement with
an if scheme:
use Work.all;
architecture SHIFT_GENERATE_2 of SHIFT_4 is
component DFF
port(D,CLK:in BIT; Q,QB:out BIT);
end component;
signal Z: array(1 to 3) of BIT;
begin
Q1:for I in 0 to 3 generate
Q2:if I=0 generate
DFFfirst:DFF port map(A,CLK,Z(1),open);
end generate;
Q3:if I=3 generate
DFFlast:DFF port map(Z(3),CLK,B,open);
end generate;
Q4:if I>0 and I<3 generate
DFFx:DFF port map(Z(I),CLK,Z(I+1),open);
end generate;
end generate;
end SHIFT_GENERATE_2;
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Summary
• Component configuration can be performed in three
ways: default binding, configuration specification, and
configuration declaration.
• Configuration declaration provides the highest degree
of flexibility. Component configuration is performed in a
separate design unit. The units which instantiate the
components have not to be recompiled in order to
change the binding.
• The generate statement is typically used in order to
model designs with a regular structure.
It provides a mechanism for conditional compilation.
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A shift register model of configurable length:
entity SHIFT_N is
generic(LEN:integer);
port(A,CLK:in BIT; B:out BIT);
end SHIFT_4;
use Work.all;
architecture SHIFT_N_GENERATE of SHIFT_N is
component DFF
port(D,CLK:in BIT; Q,QB:out BIT);
end component;
signal Z: array(1 to LEN-1) of BIT;
begin
Q1:for I in 0 to LEN-1 generate
Q2:if I=0 generate
DFFfirst:DFF port map(A,CLK,Z(1),open);
end generate;
Q3:if I=LEN-1 generate
DFFlast:DFF port map(Z(LEN-1),CLK,B,open);
end generate;
Q4:if I>0 and I<LEN-1 generate
DFFx:DFF port map(Z(I),CLK,Z(I+1),open);
end generate;
end generate;
end SHIFT_N_GENERATE;
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