Test Time Minimization for Hybrid BIST
with Test Pattern Broadcasting
TALLINN TECHNICAL
UNIVERSITY
Raimund Ubar, Maksim Jenihhin
Dept. of Computer Engineering
Gert Jervan, Zebo Peng
Embedded Systems Laboratory
Linköping University, Sweden
{gerje, zebpe}@ida.liu.se
Tallinn Technical University, Estonia
{raiub, maksim}@pld.ttu.ee
Hybrid BIST Architecture
Overview
A Hybrid BIST architecture for testing core-based systems,
that allows test pattern broadcasting.
Embedded
Tester
The test architecture is suitable for SoCs containing cores
without predesigned BIST logic.
LFSR
Emulator
The approach uses test pattern broadcasting for both
pseudorandom and deterministic patterns.
SoC
Core 4
Core 2
INP2
INP4
TAM
Tester
Memory
To overcome the high complexity of test time minimization
problem we propose a fast algorithm to find an efficient
combination of pseudorandom and deterministic test sets
under given memory constraint.
0
Max(INPk)
INP1
Core 1
INP3
INP5
Core 5
Core 3
Tester
Controller
The efficiency of the approach is demonstrated by
experimental results.
Test Time Minimization Algorithm
Generate deterministic test patterns for the core to increase the fault
coverage of the core to 100%.
Test pattern size
Generation of the initial deterministic test set.
Test pattern size
n
Fill the unused bits with pseudorandom data.
Result
Broadcast generated test patterns for other cores in the system.
Optimization of the test sequence.
Starting from the end, if the test pattern is efficient for any cores, store it in
Test pattern size


LP
×
INP
k
,
j
∑
k
 k=1

1
Initialization

L j, min = min  --n
Optimization
Finding the initial state for the LFSR.
Initial hybrid test pattern sequence generation
Deterministic
Pseudorandom
Number of test patterns
Choosing effective test patterns for every core from the initial sequence
8* 7*
6*
5*
4* 3*
2*
1*
Number of test patterns
Choosing number of effective test patterns to store based on memory constraint
Deterministic
Pseudorandom
Stored Efficient Pseudorandom
{8, 7, 6, 5, 4, 3, 2, 1}*
Number of test patterns
the memory with the size of maximum required bits.
Repeat the procedure until the memory is filled.
Experimental Results
45000
60000
55000
40000
50000
Experimental system S1
35000
45000
Experimental system S2
30000
The worst initial state for the LFSR
40000
Experimental system S3
35000
25000
Memory
Memory
The best initial state for the LFSR
20000
30000
25000
15000
20000
15000
10000
10000
5000
5000
0
0
1
251
501
751
1001
1251
1501
Total Test Application Time
1751
2001
2251
2501
1
2001
4001
6001
8001
10001
Total Test Application Time
12001
14001
The experiments were carried out with
three virtual core-based systems.
Three memory constraints were
investigated for each experimental
system.
The worst and the best initial states for
the LFSR of each experimental system
were examined.
Conclusions
The optimal solutions for individual cores are neglected
in favor of finding a quasi-optimal solution for the
whole system.
The procedure is simple (similar to greedy algorithm)
and fast.
This straightforward approach can be used as:
cheap practical solution
quickly computable reference for comparison with more
sophisticated optimization algorithms
The best initial state for the pseudorandom test The worst initial state for the pseudorandom test
System Number Memory Pseudorandom Deterministi Total test CPU Pseudorandom Deterministic Total test CPU
Name of cores Constraint test length c test length length
time
test length
test length
length
time
(bits)
(clocks)
(clocks)
(clocks)
(sec)
(clocks)
(clocks)
(clocks) (sec)
20 000
85
181
266
2 990
138
3128
6
187, 64
228.67
S1
10 000
232
105
337
4 446
73
4519
5 000
520
55
575
5 679
40
5719
20 000
92
222
314
3 015
151
3166
7
718.49
969.74
S2
10 000
250
133
383
4 469
82
4551
5 000
598
71
669
5 886
49
5935
20 000
142
249
391
3 016
200
3216
5
221,48
318.38
S3
10 000
465
161
626
4 521
121
4642
5 000
1 778
88
1866
8 604
72
8676