!$! ! "# # # # #!# & !! A design and learning tool called AIM (advanced interconnect modeling) provides VLSI circuit and technology designers with the capability to model, optimize, and scale total delay in the presence of interconnect. % !" *7$%, %*0!.+**!0 %/ $2%*# * %*.!/%*# %),0 +* 0$! ,!."+.)*! +" $%,/ .!2%+1/ 3+.' %* 0$%/ .! ".+) 0!$*+(+#%( ,!./,!0%2! $/ +*!*0.0! )%*(5 +* 0$! !(5 +" 0$! %*0!.+**!0 +. /!/ %* 3$%$ 0$! .%2%*# #0! $/ !!* %*(1 ! %* 0$! *(5/%/ 0$!.! $/ *+0 !!* * !-1( !),$/%/ +* 1.0! )+ !(%*# +" 0$! .!/%/0*! * ,%0*! +" 0$! %*0!.+**!0 * 0$! %*0!.+**!0/ !,!*7 !*! +* 2.%+1/ %)!*/%+*/ $! ,.+(!) *!! / 0+ ! !47 )%*! ".+) 0$! +),.!$!*/%2! ,!./,!0%2! +" %*(1 %*# 0$! #0! %* 0$! !(5 *(5/%/ 1/%*# 1.0! )+ !(/ "+. 0$! 0+0( !(5 * %*(1 %*# 0$! !,!* !*! +" !(5 +* 2.%+1/ ,.)!0!./ %* 0$! %.1%0 * 0!$*+(+#%( +)%*/ 2*! %*0!.+**!0 )+ !(%*# %/ * !""%%!*0 17 .0! ".)!3+.' 0+ *(56! * +,0%)%6! "1* )!*0( 1%( 7 %*# (+' +" (( .%0%( ,0$/ *)!(5 * .%0..5 #0! ""!% The following definitions explain terms as they are used in the context of the accompanying article. Cin (input capacitance). Cin is proportional to the product of gate oxide capacitance per unit area, the gate length, and the gate width. The gate width is the total width of all the transistors tied to the input. Cin is often represented by the gate width in units of m. Circuit Domain. The circuit domain refers to the design realm of the circuit designer. Specifically, certain quantities are under the control of the circuit designer in the context of interconnect delay. These include the wire width, length, and space, or the gate width. HIVE. HIVE is an internal HP software package that creates closed functions of wire capacitance components as a function of the relevant geometrical quantities. HIVE starts with the wire geometries, performs 2D numerical field simulations and arrives at closest-fit analytical functions. Interconnect. Interconnect refers to the conducting wires on an integrated circuit chip that connect the components to each other and carry electrical signals. Technological Domain. The technological domain refers to the design realm of the process technology designer. Certain quantities that affect gate delay in the presence of interconnect are under control of the technology designer. These quantities include wire thickness, interlayer spacing, transistor gate oxide thickness, and so on. Hewlett-Packard Company 1995 Cwire Rwire Wire Gate Cin Gate Delay (tgate) Cbeg Cdist Cend Wire Delay (twire) /% 1%( %*# (+' )+ !(! 5 .%2%*# * .%0..5 +*7$%, %*0!.+**!0 %/ !/%#* * (!.*%*# 0++( "+. +0$ %.1%0 * 0!$*+(+#5 !/%#*!./ +*!.*! +10 .!"1( )+ !(%*# ,.! %0%+* * /(%*# +" 0+0( !(5 %* 0$! ,.!/!*! +" %*0!.+**!0 %*(1 !/ %.1%0 * ,.+!// 0!$*+(+#5 2.%(!/ 3$%(! ,.+2% %*# ".)!3+.' 0+ )*#! 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"1*0%+*/ +" 0$! 3%.! #!+)!0.5 /$+3* %* %# $! !.1.5 !3(!007'. +1.*( Upper Layer Upper Layer Wire su Interline t L sd w s Lower Layer Lower Layer = Wire (a) (b) dimensions in Fig. 2 show the variables that represent the size (width w, length L, and thickness t) of a typical wire, and the separation of the wire from conductors that are above (su), below (sd), and adjacent (s) to it. L, w, and s are variĆ ables in the circuit domain, while t, su, and sd are variables in the technology domain. A multilayer interconnect system, like the one shown in Fig. 2, provides different values of t, su, and sd depending on the wire layer* (polysilicon, M1, M2, M3, M4, etc.), upper conductor (M1, M2, M3, M4, or none), and lower conductor (substrate, polysilicon, M1, M2, M3, etc.). AIM allows all perĆ mutations of layer and upper and lower conductors. A layer variable in the circuit domain is defined that can take on any value selected from these permutations. The upper and lower conductors, when present, are asĆ sumed to be continuous plates of conductors. To a first order, this is an acceptable approximation when the upper and lower layers have densely spaced wires. The adjacent wires are assumed to be equidistant on both sides. For simĆ plicity, the Rwire and Cwire interconnect components are asĆ sumed to be uniformly distributed along the length of the wire. Any changes in layer or wire geometry that change Rwire or Cwire are important for capacitance extractions in actual layouts. There is no value to introducing this comĆ plication into AIM, where larger trends in delay on various parameters are of interest. Also, there would be no generalĆ ity in choosing a particular change in Rwire or Cwire along the wire. A key feature of AIM is that the logic gate delay is included as a full participant in the interconnect delay analysis. Gate delay is defined as the delay from the gate input to the beĆ ginning of the wire (see Fig. 1). Wire delay is the delay from the beginning of the wire to the end, and includes the effect of Cdist. The total delay is the sum of gate and wire delays: delay = tgate + twire. (1) The gate delay is expressed in a delayĆversusĆfanout format instead of simplifying the gate as an equivalent resistance as described in reference 2. The fanout is the sum of all the capacitance seen by the gate as if it were all lumped at the output, divided by the input capacitance: tgate = t0 + slope (Cbeg + Cwire + Cdist + Cend)/Cin tgate = - k × twire, (2) Wire geometry. (a) Circuit domain variables. (b) Technology domain variables. where t0 is the yĆintercept of the of the delayĆversusĆfanout curve, slope is the slope of the delayĆversusĆfanout curve, and k is an empirical constant that represents a correction factor to account for hiding" distant capacitance along a resistive wire (0k1 and is typically 0.5). The wire delay is the usual RC delay including the distributed nature of both the wire and nonwire capacitance: twire = Rwire × (Cwire/2 + Cdist/2 + Cend) (3) Cwire consists of the interline capacitance of the adjacent wires on the same layer, and the interlayer capacitance of the upper and lower layers. Cwire = Cinterlayer + Cinterline (4) The interlayer and interline components are expressed simply as the respective parallel plate capacitances. This formulation intentionally does not include fringing effects to make it easy to express the optimum width and optimum thickness forĆ mulas in the next section. Fringing effects are described in the section Accurate Delay Modeling" on page 3. The upper and lower layers are assumed to be quiescent but adjacent wires are allowed to have a signal switching in the opposite sense. A variable m accounts for the Miller effect and effectively doubles the value of the interline capacitance when the adjacent wires switch simultaneously in the oppoĆ site direction. If m =1 the adjacent wires are quiescent, and if m = 2 the wires are switched. Cwire = ewL/sd + ewL/su + 2m × etL/s (5) Rwire = ρL/tw (6) where e is the permittivity of the dielectric and ρ is the resisĆ tivity of the metal. The more general case of Cwire for upper and lower conductor switching can easily be constructed with extra Miller variables. The wire width w and thickness t appear in the numerator and denominator of the total delay expression. A larger width or thickness implies an inversely smaller Rwire but a larger Cwire. The net effect is a reduction of the wire delay (twire), but an increase in gate delay (tgate). The total delay therefore is optimum at an intermediate value of w or t. The total delay is differentiated with respect to w and t to give the optimum values wopt (optimal wire width) and topt (optimal wire thickness) at which the delay is a minimum. * M1, M2, M3, and so on represent different types of metal layers. February 1995 HewlettĆPackard Journal Hewlett-Packard Company 1995 ; 348 + Ǹ ǒ Ǔ * / ?6 -2 7( 79 1e ) (-78 ) )2( 8 7 e 7034) 7( ) 79 8 348 + Ǹ ǒ Ǔ * / ?6 -2 7 e ) e ) (-78 ) )2( ; e 7034) 1 7( 79 • • • • %6) 78-00 0-2)%60= 4634368-32%0 83 ;-(8, ; &98 8,) 7)'32(@ 36()6 ()4)2()2') 32 -28)60-2) 74%') 7 -7 -2'09()( ",-7 -7 8,) *6-2+-2+ )**)'8 ;,-', 6)(9')7 8,) -28)60%=)6 '%4%'-8%2')7 %7 -28)60-2) 74%') -7 6)(9')( ",) -28)60%=)6 '%4%'-8%2') ,%7 8,) *361 -28)60%=)6 + ; * ; 1-2 ǒ 7 * 7Ǔ 7 ) ; 1%< * ; 1-2 36 8,) '-6'9-8 ()7-+2)6 ;348 -7 %2 -14368%28 59%28-8= %2( 32) 8,%8 '%2 438)28-%00= &) ',%2+)( *36 )%', (-**)6)28 2)8 -2 % '-6'9-8 83 %',-):) 8,) 03;)78 ()0%= $-6) ;-(8,7 1978 &) -2'6)%7)( ;,)2 (6-:-2+ 032+)6 ;-6)7 0%6+)6 -2 8,) 46)7)2') 3* %2 )<86% 03%( %032+ 36 %8 8,) )2( 3* 8,) ;-6) +6)%8)6 (-78 %2( )2( ;,)2 (6-:-2+ ;-8, 78632+)6 (6-:)67 0%6+)6 -2 36 71%00)6 7034) ;,)2 %(.%')28 ;-6)7 %6) 7;-8',-2+ 1u ;,)6) 7 %2( 7 %6) 7-<8,@36()6 430=231-%0 *92'8-327 3* 7 %2( ;1-2t;t;1%< -7 8,) 6%2+) 3:)6 ;,-', 8,) *-88-2+ *92'8-32 %440-)7 36 8,) 8)',2303+= ()7-+2)6 348-1%0 ;-6) 8,-'/2)77 -7 8,) -14368%28 59%28-8= ",) (-**-'908= ,)6) -7 8,%8 -8 -7 238 437@ 7-&0) 83 ',%2+) 8,) ;-6) 8,-'/2)77 *36 )%', (-**)6)28 2)8 ",)6)*36) )78-1%8-327 1978 &) 1%() 3* 4%6%1)8)67 79', %7 8,) )<4)'8)( 6%2+) 3* ;-6) 0)2+8, (6-:)6 7->) ;-6) 74%'-2+ %2( 232;-6) 03%(7 -2 8,) ',-47 8,%8 %6) )<4)'8)( 83 &) ()@ 7-+2)( -2 8,) 8)',2303+= 2') 8,)7) 4%6%1)8)67 %6) /23;2 8,)2 32) '%2 78%8) 8,%8 8,) ;-6) 7,390( &) ()7-+2)( 83 &) 8,-'/)6 ;,)2 -8 -7 )<4)'8)( 83 &) 032+)6 (6-:)2 &= &-++)6 (6-:)67 36 -2 8,) 46)7)2') 3* % 7-+2-*-'%28 232;-6) 03%( 59%8-32 463:-()7 %2 %2%0=8-'%0 &%7-7 *36 8,) ;)00@/23;2 -28)6'322)'8 ()7-+2 +9-()0-2) 8,%8 944)6 0%=)67 3* 1)8%0 8,%8 +3 3:)6 032+)6 (-78%2')7 7,390( &) 1%() 8,-'/)6 ;,)6) 7 %2( 7 %6) 7-<8,@36()6 430=231-%07 ",)6) -7 % 79&80) -28)6%'8-32 &)8;))2 8,) 348-191 ;-(8, %2( 8,) 348-191 8,-'/2)77 3* 8,) ;-6) ",) :%6-%&0) ;348 ()@ 4)2(7 32 8,) 8,-'/2)77 3* 8,) ;-6) %2( :-') :)67% ",97 % ;-()6 ;-6) 1%= 0)%( 83 % 71%00)6 348-191 8,-'/2)77 %''36(@ -2+ 83 )59%8-32 * 8,) 232;-6) 03%(7 (-78 %2( )2( %6) 71%00 '314%6)( 83 &38, 8,) -28)60-2) %2( -28)60%=)6 '%4%'-@ 8%2')7 8,)2 ;348 ,%7 23 ()4)2()2') 32 ;-6) 8,-'/2)77 %2( 8348 ,%7 23 ()4)2()2') 32 ;-6) ;-(8, 2 8,-7 '%7) 8,) 8)',@ 2303+= ()7-+2)6 '%2 348-1->) 8,) ;-6) 8,-'/2)77 *631 % ()0%= 78%2(43-28 ;-8,398 %2= '327-()6%8-32 *36 8,) ;-(8, 3* 8,) ;-6) ",) %2%0=8-'%0 ()0%= 13()0 3* 8,) 46):-397 7)'8-32 463:-()7 -14368%28 -27-+,8 -283 8,) :%6-397 4%6%1)8)67 %**)'8-2+ ;-6) ()0%= "3 1%/) 74)'-*-' 46)(-'8-327 %&398 -28)6'322)'8 &),%:@ -36 -2 % 8)',2303+= -8 -7 2)')77%6= 83 97) %''96%8) 291)6-'%0 :%09)7 3* 8,) (-**)6)28 '31432)287 3* 8,) ()0%= ",)7) '31@ 432)287 %6) 463:-()( -2 &= # %2( !4-') ",) %2%@ 0=8-'%0 )<46)77-327 *631 # %6) 13(-*-)( 73 8,%8 8,)= '%2 &) 97)( ;-8, %8,)1%8-'% %8,)1%8-'% -7 %2 -28)6%'8-:) -28)646)8)( 463+6%11-2+ )2:-6321)28 8,%8 %003;7 32) 83 (3 79', 8,-2+7 %7 )<46)77 %2%0=8-'%0 )59%8-327 4)6*361 %2%0=7-7 %2( '6)%8) %2( 40387 # 463:-()7 *36 731) 7)'32(@36()6 )**)'87 238 -2'09()( -2 8,) ;-6) )<46)77-32 )59%8-32 ",) -28)60%=)6 '%4%'-8%2')7 Hewlett-Packard Company 1995 ",) ()4)2()2') 3* -28)60-2) '%4%'-8%2') 32 7 -7 13()0)( %7 % 7-<8,@36()6 430=231-%0 6%8,)6 8,%2 8,) 7-140) 0-2)%6 7 8)61 -2 8,) ()231-2%836 ",) -28)60-2) '%4%'-8%2') ,%7 8,) *361 -28)60-2) + ; * ; 1-2 ń 7 ) ; *; 1%< ǒń7 * ń 7Ǔ 1-2 # 97)7 8;3@(-1)27-32%0 *-2-8) )0)1)28 7-190%8-32 3* %'89%0 +)31)86-)7 -2 %2 8)',2303+= 83 3&8%-2 8,) '3)**-@ '-)287 3* 8,) 7-<8,@36()6 430=231-%07 +-:)2 %&3:) 968,)6 %''96%8) :%09)7 3* 8,)7) '31432)287 %6) %:%-0%&0) *36 %00 :%09)7 3* 8,) 0%=)6 :%6-%&0) 3:)6 79&786%8) 36 3:)6 92()6 )8' !4-') 7-190%8-327 32 :%6-397 &%7-' +%8)7 %6) 4)6*361)( 83 3&8%-2 %''96%8) 8 %2( 7034) :%09)7 -2 8,) 8)',2303+= 3* -2@ 8)6)78 36 8,) @m1 ! 8)',2303+= ! 97)( -2 8,-7 4%4)6 8 47 %2( 7034) 47*%2398 14-6-'%0 789(-)7 %6) %073 '%66-)( 398 83 )78-1%8) 8,) :%09) 3* / -2 )59%8-32 ",) :%09) 3* / 0-)7 &)8;))2 %2( -2 ! 8)',2303+= ",) ()4)2()2') 3* +%8) ()0%= 32 -2498 7034) '390( &) -2'09()( ;-8, 8,) %((-8-32 3* 32) 36 8;3 136) *-88-2+ 4%6%1)8)67 36 7-140-'-8= 8,-7 -7 238 -2863(9')( -2 8,) *-678 -140)1)28%8-32 3* 8,) 13()0 073 8,) )1@ 4,%7-7 -2 8,) ()0%= %2%0=7-7 -7 32 8,) 86)2(7 -2 ()0%= %7 % *92'8-32 3* :%6-397 ;-6) 4%6%1)8)67 ",)7) ()4)2()2'-)7 %6) 83 % *-678@36()6 %4463<-1%8-32 -2()4)2()28 3* 8,) -2498 ;%:)*361 7034) %8 8,) +%8) ",) ()0%= 46)(-'8)( &= 8,) ()0%= 13()0 -7 '314%6)( 83 % !4-') 7-190%8)( ()0%= 3* 8,) 7%1) +%8) ;-8, 8,) ;-6) 6)4@ 6)7)28)( &= % # 79&'-6'9-8 )0%= '%0'90%8-327 *36 (%8% 43-287 3* :%6-397 ;-6) ;-(8,7 0)2+8,7 %2( +%8) 7->)7 %6) 3&8%-2)( %2( 8,)= 7,3; 8,%8 8,) 1%6+-2 3* )6636 &)8;))2 8,) %2( !4-') 6)79087 -7 t *36 3* 8,) 7%140)7 t *36 3* 8,) 7%140)7 %2( t *36 3* 8,) 7%140)7 ",-7 463:-()7 '32*-()2') -2 8,) 46)(-'8-327 1%() ;-8, 8,) ()0%= 13()0 $-8, 8,) 136) '3140-'%8)( ;-6) '%4%'-8%2') )<46)77-327 *631 # 8,) ()0%= 13()0 -7 23 032+)6 86%'8%&0) &= ,%2( &98 -8 -7 78-00 -2 %2 %2%0=8-'%0 *361 8,%8 '%2 &) '3()( -283 %8,)1%8-'% )<46)77-327 ",) &%7-' ()0%= )<46)77-327 %2( 79&)<46)77-327 %6) -2 % 7-2+0) *-0) ",) 8)',2303+= ()4)2@ ()28 '3)**-'-)287 -2 8,) ;-6) '%4%'-8%2') )<46)77-327 %6) -2 % 7)4%6%8) 8)',2303+= *-0) ",-7 %003;7 (-**)6)28 -28)6'32@ 2)'8 8)',2303+-)7 83 &) %2%0=>)( &= 7-140= ',%2+-2+ 8,) 8)',2303+= *-0) )&69%6= );0)88@ %'/%6( 3962%0 Independent Quantities Dependent Quantities Cinterline M4 Wire: Cinterline Cinterlayer Cwire Rwire Gate: Input Capacitance (Cin) Delay (t0, slope) RC Delay Gate: Gate Delay Load: Cbeg Cend Cdist Gate+Wire: Total Delay 480 Cinterlayer M3 Cwire 400 Capacitance (aF/m) Wire: Layer Width (w) Length (L) Space (s) 320 240 Cinterline 160 Cinterlayer 80 0 Any Independent Quantity Constant Dependent Quantity Contours 2.0 2.5 3.0 Wire Width (m) 3.5 4.0 $- +$/) *(+*) )/. !*- ($)$(0(6.+ *1 - Any Independent Quantity $(+' ( )//$*) .#*2$)" /# $!! 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'$) -'4 2$/# 2$/# . 3+- .. $) ,0/$*) *2 1 - / 5 -* 2$/# /# 3/-+*'/ $)/ -'4 - '$) $. )*/ 5 -* 6 0. *! /# !-$)"$)" *(+*) )/ #$. #1$*- $. $)'0 $) /# 3+- ..$*). $" .#*2. /# .( 2$- 2$/# /# *)'4 #)" $)" /#/ $/ $. *1 - .0./-/ $)./ *! # - $. -(/$ $!! - ) $) /# +$/) 0-1 . # - 0/$*) $) Cinterline M4 480 Cinterlayer 400 Capacitance (aF/m) Any Dependent Quantity Any Independent Quantity 1.5 Substrate 320 Cwire 240 Cinterline 160 80 Cinterlayer 0 1.5 2.0 2.5 3.0 Wire Width (m) 3.5 4.0 $- +$/) *(+*) )/. !*- ($)$(0(6.+ *1 .0./-/ -0-4 2' //6&- *0-)' Hewlett-Packard Company 1995 4.0 240 aF/m 4.0 280 aF/m 3.5 Wire Space ( m) Wire Space ( m) 3.5 3.0 320 aF/m 2.5 360 aF/m 2.0 200 aF/m 3.0 2.5 240 aF/m 2.0 280 aF/m 2.0 2.5 3.0 Wire Width (m) 3.5 2.0 4.0 2.5 3.0 Wire Width (m) 3.5 4.0 ConstantĆcapacitance contours for M4 over M3. ConstantĆcapacitance contours for M4 over substrate. Cinterlayer might be expected from the larger distance of the wire to the substrate, but the significant feature is that the total capacitance is not significantly reduced despite the larger distance from the substrate. This is because Cinterline has increased. This increase is because more lines of flux from the lower surface of the wire terminate on the adjacent wire instead of the lower conductor. In other words, the fringing component has increased. Another result of fringing is that the interlayer capacitance now has a very weak dependence on wire width. parameters. Fig. 8 shows an example plot of the gate and wire delay components as a function of wire width. The optimum width is only 1.5 m, which is relatively small for a 5000Ćm long wire. There is a builtĆin function in AIM that provides the optimum width when the remaining variables in the system are specified. A visual representation of the relative importance of width and space is obtained from a contour plot of wire capacitance in a 2D space of wire width and interline spacing. Fig. 6 shows constantĆcapacitance contours for M4 over M3 lines. The data in Fig. 6 is a superset of the information in Fig. 4. Along any horizontal line in Fig. 6 several contours are cut, indicating a rapid increase in Cwire (interline and interlayer capacitance) with width. The dependence on space is also significant. Fig. 7 shows the contours for M4 wire over subĆ strate. The contours appear more horizontal indicating that there is a weak dependence on wire width and that a reducĆ tion in wire capacitance is easier to achieve with an increase in (interline) spacing. The contours have reduced in value but the reduction is substantial only when the wire spacing is large and the width is large. Such contours can be made for all the metal levels to provide a quick ready reference of wire capacitance for a range of geometries. ! RC delay is an important factor that causes a circuit designer to choose wider wires when they are long. However, it is important to realize that larger width comes with an increase in the total capacitance of the wire and therefore a possible increase in the total delay. There is an optimum width of the wire at which the total delay is a minimum. Equation 7 exĆ presses the dependence of the optimum width on various Hewlett-Packard Company 1995 Delay 400 Delay Components (ps) Thus, the conventional wisdom that upper layers of metal enjoy much reduced capacitance because of their distance from the substrate does not hold. For one thing, the upper layers may run over wires in the immediate lower layer and even when they do not, the total capacitance is not much lower. The optimum wire width illustrated in the previous section depends on a number of parameters, the most important being length L, gate width Cin, wire spacing s, and wire layer. AIM can rapidly generate the optimum width for a large range of these parameters. Fig. 9 shows the optimum width versus length for a few example cases with a 200ĆfF fixed load at the end of the wire. The curves are not smooth because of the limited number of data points generated and the slow variation of delay with length. The approximately square root dependence on length predicted in equation 7 is illustrated in Fig. 9. If the gate width is increased to 200 m, the curve moves to a higher wopt (optimum wire width) as predicted in equation 7. A larger interline spacing reduces wopt as illustrated by curve C, but this dependence is not strong. Curve D shows the optimum wire width for an M1 wire and is surprisingly close to A for the same conditions. This is because the interlayer spacings are similar when M1 tgate 300 200 twire 100 M4 over M3, L = 5000 m, Cin = 100 m, s = 2 m 1.5 2.0 2.5 3.0 Wire Width (m) 3.5 4.0 Total delay versus width. RC delay is reduced but wire gate delay is increased with larger wire width. February 1995 HewlettĆPackard Journal 500 B 2.0 M1 over Substrate C 1.5 A 1.0 D 2000 3000 Wire Length (m) 4000 5000 Curve Layer Spacing Gate Width A B C D M4 over M3 M4 over M3 M4 over M3 M1 over Substrate 1.6 m 1.6 m 10 m 1.6 m 50 m 200 m 200 m 50 m .2(+3+ 5(0$ 5(#2' 4$0131 5(0$ *$,&2' 3,#$0 #(%%$0$,2 * 7$0 1. "(,& ,# & 2$ 5(#2' "-,#(2(-,1 ,# 0$ !-2' 1300-3,#$# !7 3..$0 ,# *-5$0 "-,#3"2-01 *1- 2'$ #$.$,#$,"$ -% 5-.2 -, 5(0$ 2'("),$11 (1 4$07 5$ ) % 2'$ +(,(+3+ 5(#2' #$1(&, 03*$ %-0 (1 + 2'$, (& 1'-51 2' 2 2'$ -.2(+3+ 5(#2' " , !$ 1+ **$0 2' , 2'$ #$9 1(&, 03*$ 5(#2' %-0 + ,7 0$ 1-, !*$ "-,#(2(-,1 %3** 0 ,&$ -% '(&' ,# *-5 4 *3$1 %-0 2'$ 5(0$ *$,&2'1 1. "$1 ,# (,9 4$02$0 1(8$1 " , !$ 1(+3* 2$# 2- #$2$0+(,$ 2'$ 0 ,&$ -% -.2(9 +3+ 5(#2'1 -% 2'$ 5(0$ '(1 " , 2'$, .0-4(#$ &3(#$*(,$1 %-0 2$"',-*-&7 #$1(&,$01 (, 1$22(,& +(,(+3+ #$1(&, 03*$1 %-0 5(0$1 ! , (+.-02 ,2 , *71(1 2' 2 $," .13* 2$1 *-2 -% 31$%3* (,%-09 + 2(-, %-0 "(0"3(2 #$1(&,$0 (, 1(,&*$ %(&30$ (1 .*-2 -% #$* 7 "-,2-301 5(2' & 2$ 5(#2' *-,& 2'$ 6 6(1 ,# 5(0$ *$,&2' *-,& 2'$ 7 6(1 (& 1'-51 13"' .*-2 %-0 -4$0 5(2' 9+ 5(0$ 5(#2' 9+ 1. "(,& ,# 9% 480 ps 565 ps 395 ps 315 ps 220 ps Wire Length ( m) 4000 3000 145 ps 2000 1000 25 50 M3 over M2 200 1000 80-m Inverter, 2-m Interline Space, Optimized Width for Each Length 2000 3000 Wire Length (m) 4000 5000 -2 * #$* 7 4$0131 5(0$ *$,&2' %-0 4 0(-31 *$4$*1 Legend 5000 300 100 0.5 1000 75 100 125 150 Gate Width (Cin, m) -,12 ,2 #$* 7 "-,2-301 .1 (, ,# 5(0$ *$,&2' + M4 over M3 400 Total Delay (ps) Optimum Wire Width ( m) 2.5 $!03 07 $5*$229 ") 0# -30, * 175 200 1. "$ -% & 2$ 5(#2' + *- # 2 2'$ $,# '(1 **-51 0$ #7 0$%$0$,"$ %-0 /3(")*7 *--)(,& 3. 2'$ & 2$ 5(#2' 2' 2 5-3*# !$ ,$$#$# 2- #0(4$ "$02 (, 5(0$ *$,&2' 5(2' #$1(0$# #$* 7 *2$0, 2(4$*7 2'$ #$.$,#$,"$ -% #$* 7 -, 5(0$ *$,&2' %-0 &(4$, & 2$ 5(#2' " , !$ 1$$, -0 $6 +.*$ 9+ *-,& 5(0$ 5-3*# 0$9 /3(0$ , 9+ & 2$ 5(#2' 2- "'($4$ *$11 2' , 9.1 2-2 * #$* 7 9+ & 2$ 5(#2' 5-3*# 1$$ 4$07 0 .(# (,"0$ 1$ (, (21 #$* 7 !$7-,# 9+ *$,&2' 1 1$$, !7 2'$ !3,"'(,& -% 2'$ "-,2-301 (+(* 0 .*-21 %-0 -2'$0 5(0$1 -0 -2'$0 "-,#(9 2(-,1 " , $ 1(*7 !$ &$,$0 2$# 31(,& !3(*29(, %3,"2(-,1 .0-4(#$# (, "-++-, +(1"-,"$.2(-, (1 2' 2 , 3..$0 *$4$* -% +$2 * (1 *5 71 % 12$0 5'$, #0(4(,& *-,& #(12 ,"$1 -, 2'$ -0#$0 -% %$5 2'-31 ,# +("0-+$2$01 - , *78$ 2'(1 2'$ !3(*29(, 0-39 2(,$1 (, 0$ 31$# 2- .*-2 2-2 * #$* 7 #$.$,#$,2 /3 ,9 2(27 4$0131 5(0$ *$,&2' , (,#$.$,#$,2 /3 ,2(27 (& 1'-51 2'(1 .*-2 %-0 ,# 5(0$1 ** 5(2' +(,(+3+ (,2$0* 7$0 1. "$1 ,# 9+ (,2$0*(,$ 1. "$ '$ 5(0$ 5(#2' %-0 $ "' *$4$* (1 -.2(+(8$# %-0 $ "' *$,&2' 1 #(1"311$# $ 09 *($0 * 0&$ 9+ (,4$02$0 1(8$ (1 "'-1$, 2- $+.' 1(8$ 2'$ #$* 7 -4$0 2'$ & 2$ #$* 7 '$ 2-2 * #$* 7 (1 * 0&$0 %-0 2'$ 5(0$ 2' , 2'$ 5(0$ 4$, 2'-3&' 2'$ 5(0$ #$* 7 -% 2'$ 5(0$ (1 *-5$0 (21 '(&'$0 " . "(2 ,"$ *$ #1 2- * 0&$0 & 2$ #$* 7 *1- 2'$ 5(0$ 13%%$01 %0-+ '(&'$0 (,2$0*(,$ " . "(9 2 ,"$ 2' , 2'$ 5(0$ !$" 31$ -% 2'$ . 11(4 2(,& ,(20(#$ -4$0 2'$ 5(0$ '(*$ 2'$ 5(0$ ' 1 2'$ *-5$12 #$* 7 2'$ #$* 7 (1 0$+ 0) !*7 "*-1$ '$ -.2(+3+ 5(#2' %-0 9+ *-,& 5(0$ (1 + ,# 2' 2 %-0 , 5(0$ 5(2' 2'$ 1 +$ *$,&2' (1 + '$ % "2 2' 2 2'$ 5(0$ (1 1*-5$0 2' , 2'$ 5(0$ (1 ,-2 , 02(% "2 -% !32 ' 1 !$$, "-,%(0+$# !7 .("$ 1(+3* 2(-, 5(2' 13!"(0"3(21 ,7 "'(.1 0$ 1'03,) %0-+ -,$ &$,$0 2(-, -% 2$"',-*9 -&7 2- 2'$ ,$62 !7 *&-0(2'+(" **7 1" *(,& ** 2'$ * 7$01 (, 2'$ #$1(&, 2- + 2"' 2'$ #$1(&, 03*$1 -% 2'$ ,$5 2$"',-*-&7 '$ 0$13*2 -, 2'$ 5(0$1 (, 2'$ "(0"3(2 #-+ (, (1 0$#3"2(-, (, 5(#2'1 1. "$1 ,# *$,&2'1 '$0$ + 7 *1- !$ 1" *(,& -% 5(0$ #(+$,1(-,1 2'("),$11 (,2$0* 7$0 1. "(,&1 (, 2'$ 2$"'9 ,-*-&7 #-+ (, '$ 0$13*2 -, 2'$ 1 (1 0$#3"2(-, (, & 2$ 5(#2' ,# *$,&2' ,# *1- 1-30"$#0 (, 0$ 1 2 (1 0$* 2(4$*7 $ 17 2- .0$#("2 2'$ .$0%-0+ ,"$ 1" *(,& -% 2'$ #$* 7 %-0 *-&(" "(0"3(21 2' 2 ' 4$ 0$* 2(4$*7 1+ ** +-3,2 -% (,2$0"-,,$"2 2 (1 +3"' ' 0#$0 2- .0$#("2 #$* 7 1" *(,& (, "0(2(" * . 2'1 2' 2 ' 4$ * 0&$ +-3,2 -% (,2$0"-,,$"2 '(1 (1 !$" 31$ 2'$ Hewlett-Packard Company 1995 4.0 1.00 Delay Ratio M3 Wire, 2000-m long, 80-m Gate Width, 1.2-m Width, 2-m Space 0.95 Total Delay Ratio (CMOSA/CMOSB) 3.5 Wire Space ( m) 0.79 3.0 0.81 2.5 0.83 2.0 0.85 0.90 0.85 FETs Shrunk by 0.75 0.80 0.75 23% Penalty for FET Shrink 0.70 FETs Unscaled 0.65 2.0 2.5 3.0 Wire Width (m) 3.5 4.0 0.6 Delay ratio CMOSA/CMOSB with 0.75× wire and FET shrink. Unscaled gate width = 100 m, wire length = 5000 m. scaling factor depends on the interplay of a large number of parameters. AIM allows a rapid exploration of the design space and can pinpoint scenarios in which the delay imĆ provement could be compromised. To illustrate this capability, the scaling of delay from a 0.5Ćm CMOS technology (CMOSB) to the 0.35Ćm CMOSA technolĆ ogy is observed for a range of values of different variables. The gate width in each technology is characterized by the t0 and slope values (see equation 2). The values for a CMOSA inverter are t0 = 40 ps and slope = 23 ps/fanout. The values for a CMOSB inverter are 40% higher. This accounts for the change in the FETs in the technology domain. The change in the interconnects in the technology domain is accounted for by a new set of HIVE coefficients for capacitances, which get translated into a new AIM technology file. In the circuit domain, a shrink factor of 0.75 is applied to all wire dimenĆ sions (width, spacing, and length) and to the gate width and nonwire loads. The resultant scaling of wire capacitance, RC delay, and so on is taken care of in AIM and only the circuitĆdomain scalĆ ing parameters are supplied as inputs. The data in Figs. 12 and 13 shows the delay ratio (CMOSA/CMOSB) as a function 5000 Delay Ratio 0.85 0.83 Wire Length ( m) 4000 0.81 3000 2000 0.79 1000 0.77 25 50 75 100 125 150 Gate Width (Cin, m) 175 200 Delay ratio in going from CMOSB to CMOSA with 0.75× wire and FET shrink, space = 2.4 m, width = 2 m. Hewlett-Packard Company 1995 0.60 0.7 0.8 0.9 Wire Shrink Dimensions 1.0 Total delay scaling in going from CMOSB to CMOSA. of wire space, wire width, wire length, and gate width. Fig. 12 shows that delay ratios are better for large wire space and wire width. Large wire space is often not available because of pitch limitations, while large wire widths can increase total delay. Large wire lengths are detrimental to delay scaling as are small FETs. AIM can generate these concise reference charts showing the dependence of delay scaling on various important parameters. The improvement in the delay is not significant for the wire dominated basic blocks considered in this paper. However, it is incorrect to assume that it is only the wire RC delay that is the cause of the problem. The reason is that when the wire dimensions scale down, the FET widths also scale down, reducing the drive to the wires. Further, even though the wire length reduction is beneficial to capacitance, wire spacĆ ing reduction increases interline capacitance. Also, fringing effects undermine the linear capacitance reduction expected from simplistic scaling of wire width. The resistance of the scaled wire is constant if the thickness stays the same. The net result is that both the gate delay and the wire delay do not scale well. AIM allows one to examine the delay ratio of a typical basic block with independently varied scaling factors for FET and wire scaling. Fig. 14 shows the ratio of CMOSA to CMOSB delay as a function of wire shrink dimensions. If the FETs are kept unscaled and only the wires are shrunk, the delay ratio is 0.63. This substantial improvement would also be obtained for basic blocks that do not have significant wire loading. However, it is incorrect to expect this number when a whole chip is shrunk and the critical path consists of many wireĆ dominated basic blocks. Fig. 14 illustrates this scenario when the FETs are shrunk by 0.75×. The delay ratio is now only 0.78, a 23% increase over the previous case. This illustrates the importance of the capacitive load of the wire. AIM can be used to examine each net of a chip design to flag those nets that are susceptible to poor delay scaling if they are shrunk. These nets could either be redesigned or special cases made to keep the selected FET widths unscaled in a shrink. This can lead to guidelines for design for shrinkability." In the meantime, the statement can be made that the ultimate techĆ nologically capable delay improvement is not possible in a pure shrink strategy. February 1995 HewlettĆPackard Journal AIM has been presented as a comprehensive framework to understand and optimize the performance of basic blocks in VLSI critical paths. The interconnect is modeled with highly accurate expressions that account for many secondĆorder effects, and the gate driving the interconnect has been inĆ cluded as a full participant in the analyses. The design space is large because of the many variables in both the technology and circuit domains. This has been managed with a simple but accurate analytical delay model. The implementation in Mathematica provides quick and efficient analyses of many different types of technology and circuit variables. The examples shown have illustrated only some of the capaĆ bilities of AIM. The myth of much lower capacitance for upĆ per levels of metal has been shown to be unfounded. A visual insight into the relative influence of wire width and spacing on wire capacitance has been provided. The imporĆ tance of the optimization of wire width has been demonĆ strated and its dependence on various parameters has been correlated with simple analytical equations. It has been shown that metal widths are often made larger than necesĆ sary and some minimum width rules may preclude optimal February 1995 HewlettĆPackard Journal delay. A reference chart for circuit designers showing delay versus wire length and gate size has been demonstrated. It has been shown that upper levels of metal are not necessarily the best choice even for long wires. Algorithmic shrinking of chips from one technology to the next has been shown to suffer a substantial penalty in wire dominated basic blocks. The gate capacitive delay scales as poorly as does the wire RC delay. The author would like to thank Gene Emerson for his encouragement, support, and guidance. Thanks also to K.J. Chang and Soo Young Oh for developing HIVE. 1. K.C. Saraswat and F. Mohammadi, Effect of Scaling of InterconĆ nects on the Time Delay of VLSI Circuits," Vol. EDĆ29, no. 4, April 1982, p. 645. 2. T. Sakurai, Approximation of Wiring Delay in MOSFET LSI," Vol. SCĆ18, no. 4, August 1983, p. 418. 3. K.J. Chang, et al, Parametrized Spice Subcircuits for Multilevel Interconnect Modeling and Simulation," Vol. 39, no. 11, November 1992. Hewlett-Packard Company 1995