Document 12961208

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Based on a generic model of serial communication systems, this
architecture dramatically reduces the time needed to program functional
and in-circuit tests for devices with serial interfaces. It is implemented in a
new Serial Test Card and Serial Test Language for the HP 3070 family of
board test systems.
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† See references 3 and 4 for a complete description of ISDN and associated activation
procedures. Details of HDLC and other bit-oriented protocols can be found in references
5 and 6.
†† This is a simplified description of an ISDN basic rate frame. Actual frame length and content
vary depending on which reference point (S, U, etc.) is being considered.
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"+,2$% 1, %+!)" 1%" -" 2)&/&1&"0 ,# 0"/&) 1"01&+$ 21 $"+"/)
"+,2$% 1, " 20)" #,/ *+6 !&##"/"+1 16-"0 ,# 0"/&) 0
+! 0"/&) -/,1, ,)0 , &! &+ 1%" !"#&+&1&,+ ,# 02 % + / %&9
1" 12/" 4" ),,("! !""-"/ &+1, 1%" 1"01 -/,)"*0 !"0 /&"!
&+ 1%" )01 0" 1&,+ &+ + "##,/1 1, 2+!"/01+! 1%" #2+!*"+1)
+12/" ,# " % %&0 )"! 1, 1%" !"3"),-*"+1 ,# ,2/ $"+"/&
*,!") ,# 0"/&) ,**2+& 1&,+ 0601"*0 !"0 /&"! "),4
" !"0&$+"! ,2/ +"4 0".2"+ "/ / %&1" 12/" 20&+$ 1%&0 *,!")
0 $2&!" 0, "00"+1&))6 +6 &1 01/"* ,*-1&)" 4&1% 1%"
*,!") &0 ,*-1&)" 4&1% ,2/ / %&1" 12/" 2/ -/1& 2)/
,# 1%" / %&1" 12/" 40 1/$"1"! 1 1")" ,**
--)& 1&,+0 0, ,01-"/#,/*+ " 1/!"9,##0 --/,-/&1" 1,
1%1 */("1 %3" ""+ *!" %" *,!") +! 1%20 1%" / %&9
1" 12/" &0 *,/" $"+"/) +! ,2)! 1%",/"1& ))6 " &*-)"9
*"+1"! &+ ,1%"/ 460 #,/ ,1%"/ 0"/&) 1"01 */("10
%" #,)),4&+$ 1"/*0 /" 20"! 1%/,2$%,21 1%&0 0" 1&,+
• *"+0 ,# 1/+0#"//&+$
&+#,/*1&,+ #/,* ,+" -) " 1, +,1%"/
• ,**2+& 1&,+ 0601"* 1%1
"+ ,!"0 &+#,/*1&,+ &+1, !&$&1) 0&$+)0 +! 1/+0#"/0 1%&0
"/2/6 "4)"119 (/! ,2/+)
•
•
•
•
3"/6 0"/&) &1 01/"* -,00"00"0 1%" #,)),4&+$ #,2/
-/,-"/1&"0
%60& ) 0-" &#& 1&,+0
6*,) 06+ %/,+&71&,+ )$,/&1%*0
/*&+$ )$,/&1%*0
,$& ) %++") &!"+1&#& 1&,+ *2)1&-)"5&+$
Physical Specifications. %" -%60& ) 0-" &#& 1&,+0 !"0 /&"
1%" ")" 1/& ) -/,-"/1&"0 ,# 1%" &1 01/"* 1%" +2*"/ ,# ),$&
)"3")0 !"#&+"! +! +6 ,1%"/ -/,-"/1&"0 /")1"! 1, 1%" -%60& 0
,# 1/+0#"//&+$ 1%" &1 01/"* #/,* ,+" -) " 1, +,1%"/
Symbol Synchronization Algorithms. &+ " 0"/&) &1 01/"* &0
&+%"/"+1)6 ,*-,0"! ,# &10 1%"/" *201 " 46 ,# !"*/9
1&+$ 1%" &1 ,2+!/&"0 4&1%&+ 1%" &1 01/"* !"3& "
!"0&$+"! 1, &+1"/-/"1 1%" &1 01/"* 4,2)! 20" 06*,) 06+9
%/,+&71&,+ )$,/&1%* 1, ), 1" 1%" &1 ,2+!/&"0 %" 06+9
%/,+&71&,+ -/,-"/16 ,# 1%" &1 01/"* &0 "&1%"/ " !"!& 1"! 0&$+) -1% #,/ ), (&+$ &0 -/,3&!"! ,/ 06*,) 06+ %/,+&71&,+ &+#,/*1&,+ &0 "+ ,!"! 4&1%&+ 1%"
0"/&) &1 01/"*†
Framing Algorithms. /4 0"/&) &1 01/"* &0 -)" ,#
1/+0#"//&+$ 3"/6 )&11)" &+#,/*1&,+ ,/ "5*-)" &+/6 &1
01/"* + /"-/"0"+1 ,+)6 ,+" ,# 14, 011"0 1 +6 $&3"+
*,*"+1 ,/ ,+ ,/ ,## ,4"3"/ &# 1&*" /"#"/"+ " &0
-/,3&!"! 4&1% 1%" &1 01/"* + &+!& 1&,+ ,# 4%"+ 1%" &1
01/"* 801/10 1%"+ &10 + " 00"*)"! &+1, )/$"/ 2+&10
-)" ,# //6&+$ *,/" &+#,/*1&,+ 61"0 4,/!0 *"09
0$"0 "1 %&0 &0 1%" -2/-,0" ,# #/*&+$ 1, -/,3&!" † Asynchronous protocols are also considered implicitly clocked. In that case the symbol rate is
defined as part of the bit stream symbol synchronization algorithm.
 Hewlett-Packard Company 1995
Start
Bit
IFF
Stop
Bit
Data
Start
Bit
IFF
Stop
Bit
Data
Bit
Processor
IFF = Interframe Fill Pattern
63')77-2+ %2 @
&-8
786)%1
6)*)6)2') 43-28 73 8,) &-87 3* 8,) 7)6-%0 786)%1 '%2 86%27*)6
136) '3140)< -2*361%8-32
;,)8,)6 % 4368 -7 %2 -2498 4368 36 %2 398498 4368 %8% %0;%=7
*03;7 -283 %2 -2498 4368 %2( 398 3* %2 398498 4368
!,)6) %6) 8;3 8=4)7 3* *6%1-2+ 6%1-2+ '%2 &) )-8,)6
explicit % ()(-'%8)( 7-+2%0 4%8, *36 *6%1-2+ -7 463:-()( 36
implicit *6%1-2+ -2*361%8-32 -7 )2'3()( ;-8,-2 8,) 7)6-%0 &-8
786)%1 2 -140-'-8 *6%1-2+ %0+36-8,1 1%= -2(-'%8) *6%1-2+
97-2+ )-8,)6 % bunched *6%1-2+ 4%88)62 36 % distributed *6%1@
-2+ 4%88)62 &92',)( 4%88)62 -7 1%() 94 3* % +6394 3*
'328-+9397 &-87 (-786-&98)( 4%88)62 -7 1%() 94 3* % +6394
3* &-87 -28)674)67)( %132+ 8,) (%8% &-87
8,)6 6)59-6)1)287 %6) ()8)61-2)( &= 8,) 7)6-%0 &-8 786)%1
83 ;,-', 8,) 4368 %88%',)7 * 8,) &-8 786)%1 -7 )<40-'-80=
'03'/)( 97)7 %2 )<40-'-8 7=1&30 7=2',632->%8-32 %0+36-8,1
8,) 4368 1978 ,%:) % clock interface -1-0%60= -* 8,) &-8
786)%1 97)7 %2 )<40-'-8 *6%1-2+ %0+36-8,1 8,) 4368 1978
,%:) % frame synchronization interface !,)7) -28)6*%')7
1%= '327-78 3* 32) 36 136) 4,=7-'%0 7-+2%07 8,%8 *03; )-8,)6
-283 36 398 3* 8,) 4368 !,) -140)1)28%8-32 ()8%-07 '%2 &)
()8)61-2)( &= 789(=-2+ 8,) &-8 786)%1 74)'-*-'%8-327 %2( 8,)
86%27*361%8-32 %0+36-8,1
!,) 8-1) -28)6:%0 &)8;))2 8,) )2( 3* 32) *6%1) %2( 8,)
&)+-22-2+ 3* 8,) 2)<8 -7 '%00)( 8,) interframe gap !,-7 +%4
1%= &) )-8,)6 >)63@0)2+8, *6%1)7 %6) &%'/@83@&%'/ 36 232@
>)63@0)2+8, * -8 -7 232>)63@0)2+8, 8,) -28)6*6%1) +%4 -7
*-00)( ;-8, %2 interframe fill (IFF) pattern.
Logical Channel Identification. %2= 7)6-%0 &-8 786)%17 7-1908%@
2)3970= '%66= 136) 8,%2 32) -2()4)2()28 03+-'%0 ',%22)0 3*
-2*361%8-32 $) 7%= 8,%8 8,)7) &-8 786)%17 %6) multiplexed 36
hierarchical * 8,) -2()4)2()28 03+-' ',%22)07 %6) ):)6 83
&) 6)'3:)6)( *631 % 1908-40)<)( &-8 786)%1 8,)6) 1978 &) %
1)%27 3* 92-59)0= -()28-*=-2+ )%', -2(-:-(9%0 03+-'%0 ',%2@
2)0 !,) 1908-40)<-2+ 7',)1) 74)'-*-)7 8,) 1)8,3( 97)( 83
1908-40)< 8,) 03+-'%0 ',%22)07 %2( 1%= &) '%8)+36->)( %7 )-8,)6
explicit 36 implicit
$-8, )<40-'-8 1908-40)<-2+ )%', *6%1) '328%-27 % +6394 3*
-2*361%8-32 *631 )%', 1908-40)<)( 03+-'%0 ',%22)0 !,)
*6%1) &392(%6= 463:-()7 % 6)*)6)2') *36 8,) &-8 +6394-2+7
!-1) (-:-7-32 1908-40)<)( ! ,-+,;%=7 79', %7 8,37)
*392( 32 8)0)'311 0-2) '%6(7 %2( 8,) @&97 %6)
)<%140)7 3* )<40-'-80= 1908-40)<)( &-8 786)%17
$-8, -140-'-8 1908-40)<-2+ )%', *6%1) '328%-27 % +6394 3*
-2*361%8-32 *631 320= 32) 3* 8,) 1908-40)<)( 03+-'%0 ',%2@
2)07 2*361%8-32 *631 38,)6 03+-'%0 ',%22)07 1%= *3003; -2
79&7)59)28 *6%1)7 2 8,-7 '%7) 03+-'%0 ',%22)0 -()28-*-'%8-32
-7 )2'3()( -2 8,) &-8 786)%1 *36 )<%140) 8,) %((6)77 *-)0(
3* %2 *6%1) 36 38,)6 4%'/)8->)( (%8%
!,) .3& 3* % &-8 463')7736 -7 83 '32:)68 32) &-8 786)%1 -283
%238,)6 %''36(-2+ 83 731) 74)'-*-)( %0+36-8,1 &-8 463')7@
736 8,)6)*36) ,%7 8;3 (-78-2'8 4634)68-)7 4368 ()*-2-8-327 %2(
86%27*361%8-32 %0+36-8,17
Port Definitions. &-8 463')7736 -28)6*%')7 83 &-8 786)%17
8,639+, 32) 36 136) ports 378 &-8 463')77367 ;-00 ,%:) %2
input port %2( %2 output port &98 731) ;-00 ,%:) 320= 32)
36 8,) 38,)6† %', 4368 1978 ,%:) % data interface %2(
1978 3* '3967) 1%8', 8,) 4,=7-'%0 74)'-*-'%8-327 3* 8,) &-8
786)%1 !,) (-6)'8-32%0 7)27) 3* 8,) (%8% -28)6*%') ()8)61-2)7
† These are called sources or sinks and occur at the ends of a communication system. This is
where the information sent back and forth in the serial bit stream is ultimately generated or
analyzed.
 Hewlett-Packard Company 1995
3+-'%0 ',%22)0 +6394-2+ %0+36-8,17 (3 238 (-6)'80= %**)'8
8,) 6)59-6)1)287 3* 8,) 4368 %08,39+, 8,)= 1%= -2*09)2')
8,) ()7-+2 3* 8,) '03'/ -28)6*%') 36 )<%140) % &-8 463')7@
736 ()7-+2)( 83 ()1908-40)< % 03+-'%0 ',%22)0 *631 % 1908-@
40)<)( &-8 786)%1 '390( &) -140)1)28)( -2 32) 3* 7):)6%0
;%=7 2) 1)8,3( 1-+,8 97) +%8)( '03'/ 7-+2%07 '03'/
)(+)7 320= 3''96 ;,)2 &-87 *631 8,) 03+-'%0 ',%22)0 3* -28)6@
)78 %6) 398498 *631 8,) (%8% -28)6*%') 238,)6 1)8,3( 1-+,8
97) % '328-29397 '03'/ all &-87 *631 8,) 36-+-2%0 &-8 786)%1
%6) 398498 %8 8,) (%8% -28)6*%') %2( +)2)6%8) % 7)4%6%8)
?(%8% :%0-( 7-+2%0 ;,)2 &-87 *631 8,) 03+-'%0 ',%22)0 3*
-28)6)78 %6) 46)7)28 %8 8,) 398498 (%8% -28)6*%')
Transformation Algorithms. 86%27*361%8-32 %0+36-8,1 7-140=
()*-2)7 8,) *92'8-32 83 &) 4)6*361)( &= 8,) &-8 463')7736
!,) &-8 463')7736 1978 1%2-490%8) 8,) -2'31-2+ &-8 786)%1
-2 ;,%8):)6 1%22)6 -7 2)')77%6= 83 1%/) -8 '32*361 83 8,)
6)59-6)1)287 3* 8,) 398+3-2+ &-8 786)%1
7-140) )<%140) ;-00 ,)04 83 '0%6-*= 8,) *92'8-327 3* &-8
463')77367 %2( &-8 786)%17
-+ 7,3;7 %2 )<%140) 3* 8,) +)2)6-' 13()0 %440-)( 83 %
7-140) %7=2',632397 '31192-'%8-32 7=78)1 !,) &-8 786)%1
32 8,) 0)*8 -7 8,) -2'31-2+ &-8 786)%1 "7-2+ '32:)28-32%0
8)61-2303+= -8 ;390( &) ()7'6-&)( %7 %2 %7=2',632397 &-8
786)%1 97-2+ 32) 78%68 &-8 %2( 32) 7834 &-8 23 4%6-8= ',)'/@
-2+ %2( %2 )-+,8@&-8 (%8% *-)0( !,) ()*-2-8-32 97-2+ 8,)
+)2)6-' 13()0 ;390( &) 731)8,-2+ 0-/) 8,-7
,=7-'%0 4)'-*-'%8-327
3+-' 0):)07 #308%+) 0):)07 @
@ 0):)07 03+-' ,-+, :3087
03+-' 03; :3087
=1&30 =2',632->%8-32 0+36-8,1
!=4) 140-'-8 /23;2 7=1&30 6%8)
=1&30 %8) 4)6 7)'32(
6%1-2+ 0+36-8,1
!=4) 140-'-8 &92',)( *6%1-2+ 4%88)62
6%1-2+ %88)62 ? %8 0)%78 32) 7834 &-8 36 &-8
*3003;)( &= 8,) 78%68 &-8
)&69%6= );0)88@%'/%6( 3962%0
Interframe Gap: = 0 symbols
IFF Pattern: 1"
Logical Channel Identification:
Type: Explicit (none really, since there is a single
eightĆbit data field)
The bit processor receives this bit stream on the data interĆ
face of its input port. As shown in Fig. 1, the job of this parĆ
ticular bit processor is to generate a clocked, synchronous
version of this bit stream on its output port. Here is the defiĆ
nition of the bit stream output from the bit processor (the bit
stream on the right side of the figure):
Physical Specifications:
Logic levels: 2
Voltage levels: Standard TTL levels
Symbol Synchronization Algorithm:
Type: Explicit
Clock Rate: 9600 Hz
Framing Algorithm:
Type: Implicit, bunched framing pattern
Framing Pattern: 10" (at least one stop bit or IFF bit
followed by the start bit)
Interframe Gap: = 0 symbols
IFF Pattern: 1"
Logical Channel Identification:
Type: Explicit
Notice that the framing algorithm and logical channel identiĆ
fication specifications have not changed. The bit processor
has merely generated a clock signal synchronized to the inĆ
coming bit stream. In this case another bit filter upstream of
this one could further transform the bit stream and perhaps
extract the data field. Since the output bit stream uses an
explicit clock, it is not really necessary to specify the clock
rate. Another bit processor that conforms to our generic
model should be able to accept the bit stream knowing only
that there is an explicit clock signal. Any practical implemenĆ
tation, however, will have a finite clock rate specification, so
it is a good idea to specify all such performance requirements
as part of the bit stream description.
The definition of the bit processor in our example looks
like this:
Input Port:
Data Interface: Required. See bit stream definition for
physical requirements.
Clock Interface: Not required, bit stream is implicitly
clocked.
Frame Sync Interface: Not required, bit stream is
implicitly framed.
Output Port:
Data Interface: Required. Standard TTL output
specifications.
Clock Interface: Required, bit stream is explicitly
clocked. The interface consists of a single clock
output signal meeting standard TTL logic
specifications.
Frame Sync Interface: Not required, bit stream is
implicitly framed.
February 1995 HewlettĆPackard Journal
Transformation Algorithm:
1. Use a combination of the given baud rate, an internal
highĆspeed clock, and data signal transitions to locate bit
centers.
2. Sample the input data at the bit centers and retransmit on
the output data interface. Transmit the sampling clock on the
output clock interface.
The actual algorithm would probably need to be more soĆ
phisticated, but this simple example illustrates the process of
mapping a real communication system onto the generic
model. A more complex example is given in Fig. 2.
The example just given was quite simple but can serve to
illustrate an important feature of the model. As mentioned
before, another bit processor upstream of the one described
might further transform the bit stream, perhaps aligning itself
to the framing markers and extracting the data field. The data
field could then be passed to yet another bit processor, and
so on. We call this feature of the model . Using
this idea, we can conceptually break up a serial communicaĆ
tion system into smaller, simpler pieces consisting of a series
of bit processors connected by a series of serial bit streams.
Modularity also aids the processing of hierarchical bit
streams. The functions of demultiplexing and logical bit proĆ
cessing can be divided among more than one bit processor.
As we have seen, realĆworld bit streams and communication
systems can be described by carefully specifying each propĆ
erty of the generic model. In other words, the model can
effectively mimic any serial communication system. A seĆ
quencer architecture that exactly implements the generic
model would therefore be easily programmed to test serial bit stream or protocol.
We knew of course that a variety of constraints (the laws of
physics, for example) would limit our ability to implement
the model exactly. We also knew an abstract model that
could not be implemented well enough to solve real test
problems would be useless, so we revisited the test probĆ
lems described earlier. We examined each test problem,
looking for issues that might affect the way in which we
chose to implement the model.
Complex Physical (Electrical) Interfaces. The model handles this
quite easily. One simply describes the characteristics on a
sheet of paper. An actual implementation, however, is quite
different. We decided early on that it was not feasible to
implement hardware compatible with any possible electrical
interface! Instead, we chose to implement hardware of sevĆ
eral different classes, each class capable of handling a family
of related physical bit streams.
Multiple Interfaces Operating at Unrelated Bit Rates. The generic
model does not address this issue, although the model can
be used to describe each individual interface. We decided
that this implied a multichannel architecture in which each
channel was capable of operating essentially independently
of the others.
 Hewlett-Packard Company 1995
Framing Bits
Clock
Bit Processor
(Personality Module)
B1 Bits
Frame
Sync
B1 Bits
D Bits
Data
Physical Specifications: CCITT I.430 (3-Level Logic)
Symbol Synchronization: Implicit
Framing: Implicit, Distributed Pattern
IFF Length = 0
Logical Channel Identification: Explicit
B1
Algorithm: Sync to symbols and frame.
Regroup bits and transmit synchronously.
B2
D
B1
Physical Specifications: Binary TTL
Symbol Synchronization: Explicit
Framing: Explicit
IFF Length = 0
Logical Channel Identification: Explicit
Clock
Clock
Bit
Processor
(Filter)
Bit Processor
(Channel Splitter)
Data
Algorithm: Use frame
sync signal to locate
D bits and transmit
them upstream.
Serial Test
Sequencer
D D D D D D D D D D D
Physical Specifications: Binary TTL
Symbol Synchronization: Explicit
Framing: Implicit, bunched
pattern = 01111110
IFF Length > = 0 Symbols
IFF Pattern: 1
Logical Channel Identification: Implicit
(channel ID embedded in data field)
Frame
Sync
Data
Data Packet
Algorithm: Sync to framing pattern
(01111110) and transmit synchronous
frame sync bounding the frame.
Check for correct frame check
sequence. Extract data packet and
frame check sequence and transmit
upstream.
Frame Check Sequence
Physical Specifications: Binary TTL
Symbol Synchronization: Explicit
Framing: Explicit
IFF Length = 0
Logical Channel Identification: Explicit
process XDLC_receive
receive into Data, into FCS
if Data = TEI_assignment_packet then
call Process_TEI
end if
receive into Data, into FCS
.
.
.
end process
Serial Test Language Fragment
,)--#(! ( 5/- "((&
&.")/!" )/, ),#!#(& !)& 1- .) '% .-. 0&)*'(.
-., ( -#, 1 &-) ,&#4 .". '/&.#"((& )(5
/,,(. ,"#../, )/& ,'.#&&3 #(,- .-. .",)/!"5
*/. ), 2'*& &)(! #. ,,), ,. .-. )/& ,/(
-#'/&.()/-&3 )( && "((&- ) '/&.#"((& Nondeterministic Bit Streams. ( ." ')& (3 -),. ) &/&5
.#)( ), $/-.'(. ) #( ),'.#)( #( ." #. -.,' #- -*#5
# 3 ." .,(- ),'.#)( &!),#."' .")/!". .", 1,
.1) ,- ) #'*&'(..#)( .". )/& . 3 ."##--/ #,-. 1 .")/!". #. '#!". -)'.#'- (--,3 ),
( &!),#."' .) -- #( ),'.#)( ,)' )." ." .,(-'#.
( ,#0 #. -.,'- -#'/&.()/-&3 "#- #'*&# ."
( .) *,)-- )." #. -.,'- 1#."#( ." -' #. *,)-5
-), )(&3 1 %(1 .". (3 ./& #'*&'(..#)( ) #. *,)--), 1)/& "0 &#'#.- -) 1 1(. .) & .)
- ), "#( #. *,)--),-
Bit Streams with Embedded Clocks. /, -)&/.#)( .) ." *,)5
&' ) )'*&2 *"3-#& #(., - **&#- .) ."#- *,)&' 1&& -.- ) # ,(. ",1, " ./( .) &-- ) '5
&)% -"'-
 Hewlett-Packard Company 1995
Hierarchical Bit Streams. #,,"#& #. -.,'- #'*&3 '/&.#5
*&2#(! -) 1 %(1 .". )/, #'*&'(..#)( ( .) !)) . "(&#(! '/&.#*&2 #. -.,'- "#- !#( #'*&#
." ( ), -& #. *,)--),-
" ,"#../, .". 0(./&&3 ',! ,)' ."- )(-#5
,.#)(- #- -")1( #( #! " ,"#../, #- '/&.#"((&
#( (./, " #!/, -")1- -#(!& "((& ) ." ,"#.5
./, #( ." (., 1#." $(. "((&- )0 ( &)1
" "((& #- -#!( .) .." .) -#(!& #. -.,' )
." " "((& ) ." ,"#../, )(.#(- .1) #( ),'.#)(
-)/,--#(%- && ( .3*#&
**&#.#)( " 1)/& *,)-- #(*((. -/"(5
(&- &)!#& "((&- ) ." #. -.,' ( ,#& -. (5
!/! " &)!#& "((& #- && ( #- )(5
.,)&& 3 ,/((#(! )( ." "( ,+/#, 3
." .-. *,)!,' ,-)/,- ,)' $(. *,)--#(!
"((&- ( &-) .." .) ." #. -.,' *,)0##(! /*
.) )/, -/-.,'- ), " #. -.,'
,/,3 1&..5%, )/,(&
Adjacent Processing Channel
Personality Module
To DUT
Interface
Circuitry
Reconfigurable
Bit Processor
(RBP) 3
Reconfigurable
Bit Processor
(RBP) 1
Serial Test
Sequencer
(STS)
Reconfigurable
Bit Processor
(RBP) 4
Reconfigurable
Bit Processor
(RBP) 2
Serial Test
Sequencer
(STS)
Reconfigurable
Bit Processor
(RBP)
Adjacent Processing Channel
7.2,0* 463(*77.2, (-&22*0 3+ 8-* !*6.&0 "*78 &6) !" +36 8-* '3&6) 8*78 +&1.0=
396 (-&22*07 3+ 8-* &6(-.8*(896* &6* .140*1*28*) 32 8-*
!*6.&0 "*78 &6) !" &2) 94 83 !"7 (&2 '*
.278&00*) .2 & 7=78*1
7 7-3;2 .2 ., *&(- !" 463(*77.2, (-&22*0 .7 (31>
437*) 3+ & 7*6.*7 3+ '.8 463(*77367 (322*(8*) '= 7*6.&0 '.8
786*&17 "-* '.8 463(*77367 &6* .140*1*28*) ;.8- 8-*
%
7*6.*7 3+ +.*0)>463,6&11&'0* ,&8* &66&=7 7
+631 %% 314&2= 2 .14368&28 +*&896* 3+ 8-* %
7*6.*7 .7 8-*.6 >'&7*) (32+.,96&'.0.8= "-* %
(&2 '*
463,6&11*) 32>8-*>+0= .2 8-* 7=78*1 73 23 46*463,6&11*)
7 &6* 2**)*) "-.7 +*&896* &003;7 8-* 86&27+361&8.32
&0,36.8-1 3+ & '.8 463(*7736 83 '* (-&2,*) 32 8-* +0= &2)
1&/*7 8-*7* )*:.(*7 .)*&0 +36 8-.7 &440.(&8.32 "-* 86&27>
+361&8.32 &0,36.8-17 &6* .140*1*28*) '= (.6(9.87 .27.)* 8-*
%% )*:.(*7 "-*= &6* 238 6*&00= *.8-*6 -&6);&6* 36 73+8>
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(*7736 (&00*) & reconfigurable bit processor 36 2 &)).>
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2K 8-Bit RAM
Downstream
Receive Port
Downstream
Transmit Port
Upstream
Receive Port
XILINX XC3042
Field-Programmable
Gate Array
(FPGA)
Upstream
Transmit Port
2K 8-Bit RAM
† The XC3000 series of parts is structured as an array of D-type flip-flops fed by Boolean function generators. This structure makes them well-suited for state machine and random logic
designs, but unsuitable for applications requiring a lot of storage elements.
*'69&6= *;0*88>&(/&6) 3962&0
*(32+.,96&'0* '.8 463(*7736 &6(-.8*(896*
 Hewlett-Packard Company 1995
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CS
RBP
STS
CS
RBP
STS
PM
CS
STS
CS
STS
PM
STS
CS
PM
CS
RBP
CS = Channel Splitter
PM = Personality Module
RBP = Reconfigurable Bit Processor
STS = Serial Test Sequencer
 Hewlett-Packard Company 1995
STS
CS
RBP
RBP
STS
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†† The choice of a factor of ten as a goal was somewhat arbitrary because the actual throughput improvement depends on the number of DUT channels. An eight-channel DUT might be
tested only eight times faster, whereas a sixteen-channel DUT might be tested sixteen times
faster.
††† In-circuit testing refers to methods for testing the various components of a DUT separately
while they are in place on the board. This form of testing is based on the assumption that
testing all components and connections between components ensures that the DUT as a
whole has been properly tested. This form of testing produces excellent fault diagnosis to
the failing component for repair. Functional testing refers to methods for testing a DUT by
† This part of the design consisted mostly of discrete logic gates and flip-flops, so it was quite
emulating the system environment into which it will later be integrated. Many DUTs have an
similar in character to the RBP circuitware designs. Experience has shown that these types of
edge connector interface, so this is also commonly called edge connector functional testing.
designs are more prone to design defects than higher-level, “cookbook” designs.
*'7:&7> *<1*99?&(0&7) 4:73&1
 Hewlett-Packard Company 1995
serial;Count1,R1_frames
Board Test BASIC
(BT-BASIC)
serial clock IOM_clock is 2048 events
events every 61.03515625n internal
connect clk1 to ”DCL”
connect clk2 to ”2048”
at event 0 set clk1 to ”1100”
at event 0 set clk2 to ”11110000”
end serial clock
Test Statement
Mixed Test
Analog Test
Language
(ATL)
Vector Control
Language
(VCL)
Serial Test
Language
(STL)
758&785( 2) 7(67,1* /$1*8$*(6
(19,5210(17 68332576 '(9(/230(17 2) # $1' ! 7(676
,* ,//8675$7(6 7+,6 62)7:$5( 6758&785(
// 7(;78$/ 6285&(6 $5( &203,/(' %()25( (;(&87,21 !+( 7(67 ,6
7+(1 (;(&87(' )520 7+( !> (19,5210(17 %< 86( 2) 7+(
test 67$7(0(17 !> ,6 $/62 86(' 72 &21752/ 7(67 5(6285&(6
/,.( 32:(5 6833/,(6 7(67 6<67(0 23(5$725 ,17(5)$&(6 7(67
5(68/76 &$3785( $1' 62 21
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! :$6 '(6,*1(' 63(&,),&$//< )25 7(67,1* 6(5,$/ ,17(5)$&(6
!<3,&$//< 7+(6( ,17(5)$&(6 5(48,5( 7+( )2//2:,1* &$3$%,/,7,(6
,03/( )/(;,%/( ,1387287387 // 6(5,$/ &$1 %( 6(*0(17('
,172 $ &2//(&7,21 2) %,76 &$//(' !+( 6,=( 2) 7+( )5$0(
9$5,(6 '(3(1',1* 21 7+( $33/,&$7,21
5$0( $1' %,7 0$1,38/$7,21 )($785(6 ,1&/8',1* &203$5,621
02',),&$7,21 )250$77,1* $1' &21&$7(1$7,21
203/(; &21',7,21$/ &216758&76 7+$7 (;(&87( ,1 5($/ 7,0(
25 0$1< 6(5,$/ 35272&2/6 7+,6 0($16 %(,1* $%/( 72 3(5)250
72 67$7(0(176 :,7+,1 0,&526(&21'6
833257 )25 &219(56,21 2) )5$0( '$7$ 72 $1' )520 180(5,&
'$7$ 7<3(6 $1< 35272&2/6 5(48,5( 180(5,& 352&(66,1* 2)
6,*1$/6 25 180(5,& &21752/
833257 2) 08/7,3/( !6 5811,1* &21&855(17/< (08/$7,1* $
6,1*/( 6(5,$/ %,7 675($0 25 08/7,3/( 6(5,$/ %,7 675($06
!5,**(5,1* &$3$%,/,7,(6 %(7:((1 &21&855(17 352&(66(6
,( 6(5,$/ 7(67 6(48(1&(56 $1' 7+( (;,67,1* ',*,7$/
6(48(1&(5
81>7,0( &21752/ 2) ! 3(5621$/,7< 02'8/(6 $1'
5(&21),*85$%/( %,7 352&(66256
;75(0(/< )/(;,%/( 6(783 2) ! 3(5621$/,7< 02'8/(6 $1'
5(&21),*85$%/( %,7 352&(66256 6 (: 3(5621$/,7,(6
$1' 3(5621$/,7< 02'8/(6 +$9( %((1 '(6,*1(' $)7(5 ,1,7,$/
352'8&7 5(/($6( !+( 86(5 ,17(5)$&( ,6 '(6,*1(' 72 $&&(37
7+(6( :,7+ 0,1,080 62)7:$5( 5(:25. $1' :,7+287 ',6785%,1*
(;,67,1* &86720(5 7(676
$6< 352*5$00,1* 2) 7+( &/2&. 6,*1$/ 6285&(6 21 7+( !
!+(6( &/2&. 6,*1$/ 6285&(6 $5( 86(' 72 6,08/$7( 7+( %,7 $1'
)5$0,1* &/2&.6 )281' 21 0$1< 6(5,$/ ,17(5)$&(6
$&+ 6(5,$/ 7(67 )25 $ 3$57,&8/$5 "! ,6 &217$,1(' :,7+,1 21(
6285&( ),/( !+,6 6285&( ),/( &21752/6 $// 2) 7+( !6 5(48,5('
)25 7+$7 7(67 !+( 180%(5 2) 7(676 '(3(1'6 21 7+( /(9(/ 2)
',$*1267,&6 '(6,5(' %< 7+( 86(5 (1(5$//< 7+( 86(5 :,// :5,7(
08/7,3/( 7(676 72 (;(5&,6( 7+( "! )8//<
// 0$-25 81,76 2) 7+( 6(5,$/ 6285&( &2'( $5( 25*$1,=(' $6
%/2&.6 $&+ 81,7 %(*,16 :,7+ $ 67$57,1* %/2&. 67$7(0(17 $1'
,6 7(50,1$7(' :,7+ $1 (1',1* %/2&. 67$7(0(17 !+,6 *5($7/<
 Hewlett-Packard Company 1995
stream IOM2_Master type ”synchronous”
connect ”tx_clock” to ”2048”
connect ”tx_data” to ”DD”
transmit length unknown
substream TX_All
filter ”xdlc CRC-CCITT”
transmit bits all
end substream
end stream
stream IOM2_Slave type ”synchronous”
connect ”rx_clock” to ”2048”
connect ”rx_data” to ”DD”
set ”rx_clock edge” to ”falling”
receive length unknown
substream RX_All
receive bits all
filter ”xdlc CRC-CCITT”
end substream
end stream
process TX_All
loop
transmit ”\h5555”
transmit ”\haaaa”
end loop
end process
process RX_All;Count1,R1_frames
dim AAAA$[16]
loop
receive into AAAA$,”\hxxxx”
exit if AAAA$ = ”\hAAAA”
end loop
Count = 0
loop
receive ”\h5555”,”\hxxxx”
receive ”\hAAAA”,”\hxxxx”
Count = Count + 1
exit if Count = Count1
end loop
R1_frames = Count
initiate trigger digital
end process
1 (;$03/( 2) $ (5,$/ !(67 $1*8$*( ! 352*5$0
6,03/,),(6 3$56,1* $1' '5$0$7,&$//< ,03529(6 (5525 ',$*1267,&
0(66$*(6
!+( 29(5$// 6758&785( )25 $ 6(5,$/ 7(67 ,6 ,//8675$7(' ,1 7+(
(;$03/( 6+2:1 ,1 ,* !+( 6(5,$/ 67$7(0(17 serial;Count1,R1_frames ,6 86(' 72 '(),1(
9$5,$%/(6 3$66(' 72 25 )520 7+( 7(67 (;(&87,21 (19,5210(17
!> !+,6 $//2:6 )/(;,%,/,7< ,1 &+$1*,1* 7(67 (;(&87,21
3$5$0(7(56 :,7+287 1((',1* 72 5(&203,/( 25 ,167$1&( 7+(
86(5 &$1 3$66 ,1 7+( 180%(5 2) 6(&21'6 $ %,7 (5525 5$7(
7(67 ,6 72 %( (;(&87('
!+( 237,21$/ 6(5,$/ &/2&. %/2&. serial clock IOM_clock … 352>
*5$06 7+( ! &/2&. 6285&(6 72 287387 63(&,),& &/2&. 6,*1$/
3$77(516 $&+ &/2&. 6(&7,21 &21752/6 7+( )285 6<1&+521286
&/2&. 5(6285&(6 )281' 21 21( ! !+(6( &/2&. *(1(5$7256
&$1 %( 6<1&+521,=(' 72 $1 ,17(51$/ 25 $1 (;7(51$/ &/2&.
6285&( !+( &/2&. 6,*1$/6 &$1 +$9( 9$5,$%/( /(1*7+6 5$1*,1*
)520 72 3$77(51 &+$1*(6 &$//(' (9(176 !+( /$5*(
180%(5 2) (9(176 3529,'(6 $ 9(5< )/(;,%/( )250$7 )25 '(),1,1*
(%58$5< (:/(77>$&.$5' 2851$/
(97831 (03(/ &2) +6&1* 7=2( 7.,2&07 #-* ;.)8- 3+ *&(*:*28 .7 )*+.2*) .2 2&237*(32)7 36 1.(637*(32)7
#-* transmit frame length &2) receive frame length 78&8*1*287 &6* 97*)
83 (&4896* 8-.7 .2+361&8.32 #-.7 1&= '* 92/23;2 ;-.(- .7
&003;*) &7 & /*=;36) 36 & 291'*6 '*8;**2 &2) #-.7 .2+361&8.32 .7 97*) '= 8-* (-&22*0 740.88*6 (.6(9.8;&6*
&7 .8 .27*687 36 *<86&(87 '.87 +631 8-* 786*&1
#-* 786*&1 '03(/ stream IOM2_Master type “synchronous” .7 97*) 83
)*+.2* 8-* 4-=7.(&0 (-&6&(8*6.78.(7 3+ 8-* 7*6.&0 '.8 786*&1 &2)
46383(30 83 8-* (366*7432).2, 4*6732&0.8= 13)90* #-*6* &6*
8-6** 4*6732&0.8= 13)90* 8=4*7 ## " "$" &2) "
$$" #-* " 4*6732&0.8= 13)90*7 &6* 97*) 74*(.+.(&00=
+36 (322*(8.32 83 " .28*6+&(*7 #-* ## 4*6732&0.8= 13)?
90* .7 & +0*<.'0* (300*(8.32 3+ 463,6&11&'0* ##?:308&,*
0*:*0 )6.:*67 &2) 6*(*.:*67 97*) 83 .28*6+&(* 83 ,*2*6.( ##?
0*:*0 7*6.&0 '.8 786*&17 #-* 786*&1 8=4* )*8*61.2*7 8-* 4*6?
732&0.8= 13)90*7 13)* 3+ 34*6&8.32 2 8-* &'3:* (31?
1&2) 8-* /*=;36) “synchronous” 463,6&17 8-* 4*6732&0.8=
13)90* '.8 463(*7736 83 *<4*(8 &2 *<40.(.80= (03(/*) '.8
786*&1 #-.7 8=4* 3+ 7*6.&0 '.8 786*&1 6*59.6*7 & ## 4*6732?
&0.8= 13)90* 2 *6636 ;390) '* 7.,2&0*) .+ 8-.7 /*=;36)
;*6* 97*) &2) & ## 4*6732&0.8= 13)90* ).)28 *<.78 #-*
*0*(86.(&0 0*:*07 3+ 8-* 4*6732&0.8= 13)90*7 &6* +.<*) '98 8-*
786*&1 46383(307 &6* 463,6&11&'0* #-* *<&140* .2 ., .7
&2 *<40.(.80= (03(/*) &2) .140.(.80= +6&1*) '.8 786*&1 #-*6*?
+36* 8-* ## 4*6732&0.8= 13)90* 97*7 8;3 7.,2&0 0.2*7 83
6*(*.:* )&8& rx_data &2) rx_clock #-* *<40.(.8 +6&1.2, 7.,2&0
0.2* rx_frame_sync .728 6*59.6*) '= 8-* '.8 463(*7736 '*(&97*
8-* +361&8 -&7 8-* +6&1.2, .2+361&8.32 *1'*))*) .2
8-* &(89&0 )&8& 86&271.88*) .++*6*28 ## 13)*7 &6* 97*) 83
6*463,6&1 8-* '.8 463(*7736 83 *190&8* & :&6.*8= 3+ 7*6.&0
46383(307 6&2,.2, +631 7=2(-632397 # .28*6+&(*7 83
&7=2(-632397 .28*6+&(*7 0./* !"?
#-.7 0*&)7 97 83 8-* 2*<8 '03(/ 7869(896* 8-* &(- 786*&1 (&2 -&:* '*8;**2 32* &2) +396 79'786*&17
#-* 79'786*&17 &6* )*+.2*) &7 & '03(/ 7869(896* ;.8-.2 *&(786*&1 '03(/ #-* 79'786*&1 463,6&17 8-* (-&22*0 740.88*6 83
8&6,*8 74*(.+.( '.87 ;.8-.2 8-* +6&1* &(- 79'786*&1 (&2
6*(*.:* &2) 86&271.8 '.87 +631 ;.8-.2 *&(- 786*&1 +6&1* #-*
'.87 8&6,*8*) '= 8-* (-&22*0 740.88*6 &6* 8-*6*+36* *.8-*6 *<?
86&(8*) 36 .27*68*) .283 8-* 786*&1 +6&1* &(- 79'786*&1 -&7
&2 &773(.&8*) 7*6.&0 8*78 7*59*2(*6 (&00*) & 773(.?
&8*) 79'786*&17 &2) 463(*77*7 -&:* 8-* 7&1* 2&1* #-*
79'786*&1 )*+.2*7 ;-.(- '.87 3+ 8-* +6&1* &6* 4&77*) 83 36
6*(*.:*) +631 8-* 463(*77 #-* 463(*77 (328&.27 8-* &(89&0
463,6&1 97*) 83 (328630 8-* '.8 :&09*7
+ 8-* 786*&1 +6&1* 0*2,8- .7 /23;2 8-*2 *&(- 79'786*&1 .7
)*+.2*) &7 & 4368.32 36 &00 3+ 8-* 786*&1 +6&1* &68.(90&6 '.87
.2 8-* 786*&1 +6&1* &6* *291*6&8*) +631 83 8-* +6&1*
0*2,8- #-* 97*6 8&,7 (*68&.2 786*&1 '.87 +36 8-* 79'786*&1 83
86&271.8 36 6*(*.:* '= 97* 3+ 8-* 86&271.8 36 6*(*.:* '.87
78&8*1*287 transmit bits all transmit bits 1 to 8 receive bits all 908.40*
86&271.8 36 6*(*.:* '.87 78&8*1*287 &((9190&8* 8&,,*) '.87
00 8-*7* '.87 &6* (32(&8*2&8*) '= 8-* "# -&6);&6* .2
36)*6 '.8 83 '.8 2 &2) 86*&8*) &7 & +6&1* '= 8-* 463(*77
&773(.&8*) ;.8- 8-&8 79'786*&1
#-* 13)* 3+ 8-* " 4*6732&0.8= 13)90*7 (&2 '* (-&2,*)
&7 ;*00 36 *<&140* 8-* " "?'97 13)90* (&2 7.190&8*
8*61.2&0 *59.41*28 36 & 2*8;36/ 8*61.2&836 #-* &9831&8.(
" 7=2(-632.>&8.32 7*59*2(*7 &6* ).++*6*28 )*4*2).2, 32
8-* " 13)* 7*0*(8*) #-* 13)* 8=4* 6*463,6&17 8-*
4*6732&0.8= 13)90*7 (.6(9.8;&6* 83 (32+361 83 ).++*6*28
786*&1 6*59.6*1*287
+ 8-* 786*&1 +6&1* 0*2,8- .7 92/23;2 '*(&97* .8 1978 '*
6*(3:*6*) +631 8-* '.8 786*&1 &7 .7 8-* (&7* 7-3;2 .2 ., 8-*2 8-* 463,6&11*6 1978 )*+.2* & 6*(32+.,96&'0* '.8 463?
(*7736 83 86&27+361 8-* '.8 786*&1 #-.7 .7 .)*28.+.*) .2 8-*
79'786*&1 '03(/ &7 & +.08*6 78&8*1*28 36 '03(/ filter “xdlc CRCCCITT” "*8 78&8*1*287 (&2 '* 97*) 83 (328630 8-* +.08*6 .2
19(- 8-* 7&1* ;&= &7 7*8 78&8*1*287 &6* 97*) 83 (328630 8-*
4*6732&0.8= 13)90* .2 8-* 786*&1 '03(/
#-* 463,6&11*6 (322*(87 8-* 4*6732&0.8= 13)90* 83 8-*
$# '= 97.2, 8-* (322*(8 78&8*1*28 connect “tx_data” to “DD”
#-.7 78&8*1*28 4-=7.(&00= (037*7 8-* (366*(8 "# 6*0&=7 83
(322*(8 & 4*6732&0.8= 13)90*7 6*7396(*7 83 8-* $# #-*
4*6732&0.8= 13)90*7 6*7396(*7 &6* 1908.40*<*) 96.2, 8-*
8*78 ,*2*6&8.32 463(*77 8-* 7=78*1 73+8;&6* ;.00 &9831&8.?
(&00= )*8*61.2* 8-* 348.1&0 (322*(8.32 1*8-3) 83 8-* $#
#-.7 (322*(8.32 1*8-3) .7 8-*2 97*) 83 '9.0) 8-* (366*(8
+.<896* .28*6+&(* 83 8-* $#
96 ,*2*6.( 13)*0 &003;7 .2+.2.8* 0*:*07 3+ '.8 786*&1 -.*6&6?
(-= #-* "# -&6);&6* 79443687 8;3 0*:*07 786*&1 &2) &
7.2,0* 0&=*6 3+ 79'786*&17 )).8.32&0 0*:*07 (&2 '* *190&8*)
.2 8-* 7*6.&0 0&2,9&,* #-.7 -&7 238 463:*) 833 6*786.(8.:*
7.2(* 1378 46383(307 6*59.6* 23 136* 8-&2 8;3 0*:*07 !*+*6
83 ., +36 &2 *<&140* 3+ -3; 8-.7 ;36/7
908.40* 79'786*&17 (&2 6*(*.:* 8-* 7&1* '.87 '98 320= 32*
79'786*&1 (&2 86&271.8 & 4&68.(90&6 '.8 79'786*&1 1&=
-&:* 23 '.87 '*.2, 86&271.88*) 36 6*(*.:*) #-.7 (&4&'.0.8= .7
97*) 83 (6*&8* & 463(*77 8-&8 7.140= (3286307 38-*6 463(*77*7
&(- 4*6732&0.8= 13)90* 13)* -&7 & 7*8 3+ 463,6&11&'0*
+*&896*7 #-*7* &6* (3286300*) '= 97* 3+ 7*8 78&8*1*287 set
“rx_clock edge” to “falling” #-* 7*8 78&8*1*28 .7 59.8* ,*2*6.(
set “mode description” to <value>
#-* <value> 4&6&1*8*6 (&2 '* & 291*6.( 36 786.2, .)*28.+.*6
0./* “enabled” &(- 13)* -&7 & 74*(.+.( 7*8 3+ +*&896*7 + &
+*&896* .7 238 *<40.(.80= 7*8 8-*2 & )*+&908 :&09* .7 97*)
= )*+.2.8.32 +631 396 ,*2*6.( 7*6.&0 46383(30 13)*0 *&(786*&1 ;.00 -&:* & 7869(896* 3+ '.87 (&00*) & +6&1* +6&1* 3+
'.87 .7 (328.293970= 36 32 )*1&2) 86&271.88*) 36 6*(*.:*)
*4*2).2, 32 8-* 46383(30 ;* 1&= 36 1&= 238 /23; 8-*
+6&1* 0*2,8- *68&.2 7*6.&0 46383(307 -&:* 8-* +6&1* 0*2,8*1'*))*) .2 8-* &(89&0 786*&1 3+ 03,.(&0 '.87 .7 &2
*<(*00*28 *<&140*
*'69&6= *;0*88? &(/&6) 3962&0
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7 78&8*) 46*:.3970= *&(- 79'786*&1 -&7 &2 &773(.&8*) 463?
(*77 process RX_All;Count1,R1_frames &(- 463(*77 6*46*7*287 &2
.2)*4*2)*28 463,6&1 8-&8 .7 *<*(98*) (32(966*280= ;.8- &00
38-*6 463(*77*7 )*+.2*) .2 & 4&68.(90&6 7*6.&0 7396(* 463,6&1
%&6.&'0*7 4&77*) .283 8-* 7*6.&0 8*78 &6* 79'7*59*280= 4&77*)
83 .2).:.)9&0 463(*77*7 #-* "# 463(*77 78&8*1*287 ;*6*
13)*0*) &+8*6 #?" #-*6*+36* 8-* 78&8*1*287 &2)
7869(896*7 &003;*) .2 "# 463(*77*7 .2(09)*
+?8-*2 (32).8.32&07
3,.(&0 34*6&8367
77.,21*28
334*<.8 .+*2) 0334 (327869(8
 Hewlett-Packard Company 1995
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6#3065*/&4 8*5) %"5" 4$01*/( $0/530-
*5 &3303 3"5& 5&45 '6/$5*0/4
6.&3*$ '6/$5*0/4
$$&44 50 453&". "/% '*-5&3 '&"563&4 5)306() $0/530- "/%
45"564 '6/$5*0/4
*54 50 #& 53"/4.*55&% 03 3&$&*7&% "3& '03."55&% "4 " %"5"
5:1& $"--&% " 3".& %"5" $"/ #& 4503&% */ " 7"3*"#-&
A$ 03 "4 " $0/45"/5 46$) "4 10001 "$) '3".& 7"3*"#-& *4
4*.1-: " -*/&"3 "33": 0' 1"$,&% #*54 30. " 130(3"..*/(
1&341&$5*7& 5)& '3".& 7"3*"#-& *4 53&"5&% -*,& " 453*/( %"5"
5:1& "$) '3".& 7"3*"#-& )"4 " ."9*.6. -&/(5) %&$-"3&% #:
5)& dim 45"5&.&/5 )& %&'"6-5 -&/(5) *4 #*54
"5" *4 53"/4.*55&% #: 5)& 53"/4.*5 45"5&.&/5 transmit “\h5555”, A$
03 3&$&*7&% */50 5)& 130$&44 #: 5)& 3&$&*7& 45"5&.&/5 receive
“\h5555”, into A$
-- 130$&44 '3".&4 "3& #6''&3&% */5&3/"--: 8*5)*/ 5)& 4&3*"5&45 4&26&/$&3 )&4& #6''&34 "--08 5)& 4&3*"- 5&45 4&26&/$&3
50 $0/5*/6& 50 &9&$65& 5)& 130(3". "/% /05 #& 5*&% %*3&$5-:
50 5)& 53"/4.*5 03 3&$&*7& 3"5&
-- 453*/( 01&3"5*0/4 -*,& 46#453*/( $0/$"5&/"5*0/ &26"-*5:
*/4&35*0/ "/% %&-&5*0/ "3& 4611035&% 8*5) 5)& '3".& %"5"
5:1& "$) #*5 0' " '3".& 803,4 +645 -*,& " $)"3"$5&3 */ "
453*/( )& 64&3 $"/ 64& 7"3*064 /05"5*0/4 #*/"3: 0$5"- )&9<
"%&$*."- %&$*."- 03 50 "44*(/ " 7"-6& 50 " '3".&
7"3*"#-& */$& 453*/( 01&3"5*0/4 8&3& .0%&-&% "'5&3 5)04& */
< 130(3"..&34 '".*-*"3 8*5) -"/(6"(&4 $"/
26*$,-: -&"3/ '3".& 01&3"5*0/4
/ 130$&44 "-40 46110354 */5&(&3 3&"- */5&(&3 "33": "/%
3&"- "33": %"5" 5:1&4 0/7&34*0/ #&58&&/ */5&(&34 "/%
'3".& %"5" 5:1&4 *4 4611035&% )&4& %"5" 5:1&4 "3& 64&% 50
4611035 $0.1-&9 $0/530- "-(03*5).4 "/% %*(*5"- 4*(/"- 130<
$&44*/( 0' %"5" /& "11-*$"5*0/ 3&26*3*/( 5)*4 $"1"#*-*5: *4
5&45*/( "/"-0( -*/& $"3%4 */& $"3%4 */5&3'"$& 46#4$3*#&3
&26*1.&/5 46$) "4 " 1)0/& 50 5)& 16#-*$ %"5" /&5803,
:1*$"- 5&454 3&26*3& " 4*(/*'*$"/5 ".06/5 0' %*(*5"- 4*(/"130$&44*/( '03 5&45*/( "/"-0(<50<%*(*5"- 53"/4.*44*0/ 53"/4'&3
'6/$5*0/4
*.&<03%&3 4&26&/$& $0/530- #&58&&/ 130$&44&4 "/% 5)&
%*(*5"- 4&26&/$&3 *4 )"/%-&% #: 64& 0' -&7&-<4&/4*5*7& /".&%
53*((&34 )& 53*((&3*/( .&$)"/*4. )"4 #&&/ *.1-&.&/5&%
64*/( " 4*.1-& ."*-#09 "1130"$) )& 130$&44 4&/%*/( "
53*((&3 1-"$&4 5)& "113013*"5& 53*((&3 /6.#&3 */ *54 "44*(/&%
."*-#09 30$&44&4 3&$&*7*/( 53*((&34 "3& 50-% */ 8)*$) ."*-<
#09 "/% '03 8)*$) /6.#&3 50 -00, )*4 *.1-&.&/5"5*0/
"--084 "/: 130$&44 50 4&/% 03 3&$&*7& " 53*((&3 50 03 '30.
"/: 05)&3 130$&44 5 "-40 "--084 .6-5*1-& 130$&44&4 50 3&<
$&*7& 5)& 4".& 53*((&3 &/ %*''&3&/5 53*((&34 $"/ #& 4&/5 50
"/: 05)&3 130$&44 %&'*/&% */ 5)& 4&3*"- 4063$& / "%%*5*0/ 50
*/5&3130$&44 53*((&3*/( 5)& 4:45&. 46110354 53*((&3*/( 50 "/%
'30. 5)& 1"3"--&- %*(*5"- 4&26&/$&3 03 &9".1-& *( 4)084
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 Hewlett-Packard Company 1995
Process A
Process B
Trigger from B.5
Wait for Trigger
Initiate Trigger 5
Initiate Trigger 4
Trigger from Digital.2
End Process
Trigger from A.4
Loop
Receive A$
Exit if Triggered
End Loop
End Process
HP 3070 Digital
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† 125 s is an important number in telecommunications applications because it corresponds to
the basic 8-kHz frame rate used throughout the network.
†† Usually in under 15 seconds. The largest serial test to date takes 44 seconds to compile.
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† This tool inserts probes into the source code that allow reporting of coverage of particular
execution paths within a program.
 Hewlett-Packard Company 1995
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')3/22'4 !:(2/8./4- 536'4= # #954+ Microcomputer Interfacing, **/854?&+82+= !:(2/8./4536'4= 4) .57','8 The Handbook of Data Communication and
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$+89 .'22+4-+ HewlettĆPackard internal communication HP-UX is based on and is compatible with Novell’s UNIX operating system. It also complies
with X/Open’s* XPG4, POSIX 1003.1, 1003.2, FIPS 151-1, and SVID2 interface specifications.
UNIX is a registered trademark in the United States and other countries, licensed exclusively
through X/Open Company Limited.
X/Open is a trademark of X/Open Company Limited in the UK and other countries.
Motif is a trademark of the Open Software Foundation in the U.S.A. and other countries.
 Hewlett-Packard Company 1995
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