"$ ! Designing with a system focus and extracting as much performance and
functionality as possible from available technology results in a highly
integrated graphics chip that consumes very little board area and power
and is 50% faster and five times less expensive than its predecessor.
# ! •
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Memory
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Cache
General System Connect (GSC) Bus
Graphics
Subsystem
LASI Chip
(I/O)
Monitor
Graphics
Chip
Video
RAM
Frame
Buffer
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† A window accelerator is the hardware that provides the images seen on the workstation
monitor. In particular, an accelerator is geared toward speeding up environments such as
the X Window System. The window accelerator enables the fast movement of windows on
the screen, scrolling of text, painting of window borders and backgrounds, and so on.
02), %7,%44;!#+!2$ /52.!,
System Memory
System Memory
Frame Buffer
Frame Buffer
Frame Buffer
A
B
(a)
(b)
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x = Not Affected
Frame Buffer
A
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Video Block
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Controller
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Function
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Color
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Table #1
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Red
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To Monitor
Color
Lookup
Table #2
Data
Formatter
Frame Buffer Controller
To Random Ports
From Video Ports
Frame Buffer
Random Port
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(2M Bits)
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(2M Bits)
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Optional Frame Buffer Memory
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3
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2
1
0
1
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0
1
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4
2
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6
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6
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57.1 *<1*99@&(0&7) 4:73&1
 Hewlett-Packard Company 1995
Graphics Subsystem,
Date of Introduction,
and HP 9000 Models
Bus Interface and
Macro Function Unit
Data Formatter and
Frame Buffer Controller
CRX/GRX
March 1991
720/730/735
Video Block
Xtal
Frame Buffer
RAM
Color Lookup
Table + DAC
with Cursor
Increasing
Density
C
September 1991
705/710
Xtal
Color Lookup
Table + DAC
with Cursor
C
August 1992
715/725
PhaseLocked
Loop
Color Lookup
Table + DAC
with Cursor
HC
January 1994
712
Graphics
Chip
• Printed circuit board area is a significant system cost. The
elimination of a large number of chips not only reduced the
printed circuit board area from about 60 in2 for the CRX to
14 in2 for the graphics subsystem in the Model 712, but
allowed the graphics to be integrated directly onto the
motherboard, eliminating connectors, a bulkhead, and other
mechanical components.
• Power consumption for the graphics subsystem in the Model
712 is only six watts. This low power consumption reduces
power supply capacity and cooling requirements and thereĆ
fore cost.
• Manufacturing costs associated with parts placement, test,
and rework are proportional to the number of discrete comĆ
ponents in a system. The graphics chip and and other chips
in the Model 712 include JTAG (IEEE 1149.1) capability and
signature generators to reduce the cost of printed circuit
board test.
Optional
VRAM
The evolution of HP's
graphical user interface (GUI)
accelerator.
Increased clock rates are possible because of the elimination
of chipĆtoĆchip synchronization delays, pad delays, and
printed circuit board trace delays. This compounds the bandĆ
width benefit of wider buses. HP's CMOS26B technology
allows the bus interface, macro function unit, and frame
buffer controller blocks of the graphics chip to operate at 80
MHz while the three DACs and two color lookup tables of
the video block operate at 135 Mhz.
Intelligent systemĆlevel design also made major contributions
to performance. A simple example is the block transfer comĆ
mands which are responsible for transferring data from sysĆ
tem memory to the graphics chip and its frame buffer. A
special mode was introduced to the memory and I/O conĆ
troller in the PA 7100LC which allows fast sequential doubleĆ
word transfers without incurring the overhead of two singleĆ
word transfers. This simple change boosted block transfer
performance by 50%.
Several factors made this high level of integration practical.
Besides designing with a systemĆlevel focus, the other
First, improved VLSI capabilities such as increased FET denĆ
driving philosophy was to extract as much performance and
sity, decreasing wafer costs and the availability within HP of
utility as possible from available technology. A good example
video DAC technology. Secondly, the desktop availability of
of this is the use of the advanced features available in the
design and simulation tools capable of handling a model of
latest 2MĆbit and 4MĆbit VRAMs. HP has been instrumental in
over 300,000 gates and 500,000 transistors. VLSI design and
proposing and driving many of these enhancements within
verification were accomplished on HP 9000 Series 700 workĆ
the JEDEC committee over the last few years. The more imĆ
stations using Verilog, Synopsys, and many inĆhouse IC deĆ
portant features include:
velopment tools. The performance of the workstations alĆ
• Page mode. This feature eliminates the need to send redunĆ
lowed the gateĆlevel simulation of entire video frames (1/60
dant portions of the pixel address when writing into the
s of operation) of over 1.2 million pixels, which was the first
frame buffer. The result is that many operations can write a
time this was accomplished within HP.
pixel in as little as 37.5 ns versus the more typical 70 ns (see
Fig. 10). The key here is that these operations must occur
within a page of VRAM or a significant penalty is incurred.
The integration described above has also resulted in signifiĆ
By default this page is long and narrow, which is good for
cant performance benefits. The two major reasons for the
block move and block transfer operations but bad for ranĆ
performance benefits are wider buses and increased clock
domly oriented vectors and rectangles. To achieve a better
rates.
performance balance, we made use of the next feature.
Wider buses are possible between blocks when they are on • Stop register/split transfer. This feature allows the frame
buffer to be organized in pages that are more square than
the same piece of silicon. Wider buses allow better commuĆ
long and narrow. Moving to this organization improves ranĆ
nication bandwidth at a given clock rate, with very little cost
dom vector and small rectangle performance significantly
impact. A good example on the graphics chip is the much
while only slightly reducing large horizontal primitive
improved communication between the macro function unit
performance (see Fig. 11).
and the data formatter which once existed as separate chips.
 Hewlett-Packard Company 1995
April 1995 HewlettĆPackard Journal
Page Mode
First Pixel
Second Pixel
Third Pixel
Fourth Pixel
Time
Nonpage Mode
11 Cycles
137.5 ns
First Pixel
Table I
Summary of the Graphics Chip’s Performance
11 Cycles
137.5 ns
3 Cycles
37.5 ns
for Each
Pixel
Second Pixel
11 Cycles
137.5 ns
Total
20 Cycles
250 ns at 80 MHz
Third Pixel
11 Cycles
137.5 ns
Fourth Pixel
11 Cycles
137.5 ns
Total
44 Cycles
550 ns at 80 MHz
6 144=;<:)<176 7. <0- 8-:.7:5)6+- 158:7>-5-6< 87;;1*4=;16/ <0- 8)/- 57,- <7 ?:1<- 81@-4; 16<7 <0- .:)5- *=..-: #01; -@C
)584- +758):-; <0- 8-:.7:5)6+- 7. -)+0 57,- ?0-6 2=;< .7=:
81@-4; ):- <:)6;.-::-, <7 <0- .:)5- *=..-:
• 47+3 ?:1<- ; 5-6<176-, -):41-: 78-:)<176; ;=+0 ); <-@<
)6, :-+<)6/=4): .144 .:-9=-6<4A :-9=1:- 764A 76- 7: <?7 +747:;
<7 *- ;-4-+<-, 76 ) 8-:C81@-4 *);1; 7: <01; :-);76 %!;
8:7>1,- ) 57,- >1) ) ;16/4- *1< 16 ?01+0 ) 81@-4; +747:
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+747: ;<7:-, 16 <0- %!; #01; <:)6;4)<-; 16<7 )6 × 8-:.7:C
5)6+- 158:7>-5-6< .7: <0-;- <A8-; 7. 78-:)<176;
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1<; <0-7:-<1+)4 0):,?):- 4151< <7 1<; 8-:.7:5)6+- 16 CB
)6, CB 7,-4 ?7:3;<)<176; )6, <0- 7,-4 !' #0- .16)4 :7? 16 #)*4- '5):3 1; )6 16,=;<:AC;<)6,):,
5-<:1+ <0)< 1; )6 )>-:)/- 7. ;->-:)4 0=6,:-, ' &16,7? "A;C
<-5 <-;<;
Benchmark
Hardware
Limit
Model
712/80
Model
712/60
CRX
720
47+3 <:)6;.-: C*1<
81@-4;; .:)5- *=..-: <7
;A;<-5 5-57:A
47+3 <:)6;.-: C*1<
81@-4;; ;A;<-5 5-57:A
<7 .:)5- *=..-:
47+3 57>- 81@-4;;
.:)5- *=..-: <7 .:)5*=..-: *A 81@-4;
%-+<7:;; C81@-4 '
+75841)6<
#-@< +0):)+<-:;; *A
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3
3
3
!-+<)6/4-;; *A 81@-4;:-+<)6/4-
3
3
3
D
'5):3
-A76, 158:7>16/ 8-:.7:5)6+- )6, ,:78816/ +7;< ;=*;<)6C
<1)44A 1< ?); )6 1587:<)6< /7)4 <7 16+4=,- =;-.=4 6-? .=6+C
<176)41<A 16 <0- /:)801+; +018 -47? ):- ;75- 7. <0- 57:1587:<)6< ),,1<176;
Software Video Support. 6- 7. <0- ,-;1/6 /7)4; .7: <0- 7,-4
?); <7 *- )*4- <7 84)A )6, >1,-7 ;-C
9=-6+-; ?1<07=< -@8-6;1>- 0):,?):- )++-4-:)<176 #0:7=/0
+):-.=4 )6)4A;1; 7. <0- ,-+7,16/ 8:7+-;; 1< *-+)5- +4-): <0)<
<01; ?); 87;;1*4- )< .=44 .:)5- :)<-; )6, 01/0 >1;=)4 9=)41<A
=;16/ ) +75*16)<176 7. <0- .7447?16/ )4/7:1<051+ )6, /:)801+; -60)6+-5-6<;
7<- <0)< <0- /:)801+; +018; 0):,?):- 4151< 1; ;1/61.1+)6<4A
• !-?:1<16/ <0- ;<)6,):, ,-+7,- )4/7:1<05; <7 5)3- <0-5 );
01/0-: <0)6 <0- 7,-4 ;A;<-5 8-:.7:5)6+- 4151<; #01;
-..1+1-6< ); 87;;1*40-),:775 5-)6; <0)< .=<=:- ;A;<-5; ?1<0 01/0-: 4->-4; 7.
•
,,16/ 3-A 16;<:=+<176; <7 <0- $ 8-:.7:5)6+- 7: ->-6 57:- 01/04A <=6-, ;7.<?):- ,:1>-:;
•
584-5-6<16/ ($%C<7C! +747: ;8)+- +76>-:;176 16 <0?144 *- +)8)*4- 7. ->-6 *-<<-: ?16,7? ;A;<-5 8-:.7:5)6+-
/:)801+; +018
With Stop Register
Without Stop Register
Page Is
256 Pixels Wide by
8 Pixels High
Page Is
1024 Pixels Wide by
2 Pixels High
Page
Page
Page
Page
Page
Page
Page
Page
Page
Page
Total Cycles to
Draw a 10-Pixel Vector:
11+(4x3)+11+(4x3) = 46
8:14 -?4-<<C )+3):, 7=:6)4
Total Cycles to
Draw a 10-Pixel Vector:
11+(11+3)+(11+3)+(11+3)+(11+3)+11 = 78
58:7>16/ 8-:.7:5)6+?1<0 .:)5- *=..-: 8)/-; <0)< ):57:- ;9=):- <0)6 476/ )6,
6)::7?
 Hewlett-Packard Company 1995
Graphics Chip
True Color
Primitive or
Bitmap Data
24 Bits
HP Color
Recovery
Encode
Monitor
HP Color
Recovery
Decode
8 Bits
24 Bits
Color
Lookup
Table and
DAC
Analog RGB
8 Bits
Frame Buffer
(8 Bits per Pixel)
The HP Color Recovery
pipeline.
YUV encoding is used in many video formats. It allocates
proportionately more bits to encode the brightness or lumiĆ
nance (Y) of the image, and fewer bits to represent the color
(UV) in the image. Since the human eye is more sensitive to
brightness than color, this is an efficient scheme. However,
since the graphics chip's frame buffer is stored in RGB forĆ
mat, a conversion from YUV to RGB is necessary.
applications. The graphics chip solves this problem in a maĆ
jority of cases by providing two 256Ćentry color maps. For
most interactions in which the user is focused on a single
application and the window manager, this completely elimiĆ
nates the resource contention and results in a visually stable
screen (see Fig. 13).
This conversion is a good example of an operation that was
relatively expensive in software (a 3ĆbyĆ3 16Ćbit matrix multiĆ
ply) but simple to do in the the graphics chip hardware. This
simple addition alone improves video playback performance
by as much as 30% and helps enable full 30Ćframe/s
320ĆbyĆ288Ćpixel resolution MPEG playback on a Model
712/80.
•
•
•
•
•
•
HP Color Recovery. The graphics chip incorporates a new disĆ
play technology called HP Color Recovery. Using a lowĆcost
8Ćbit frame buffer and HP Color Recovery, the graphics chip
can display images that are in many cases visually indistinĆ
guishable from those of a 24Ćbit frame buffer costing three
times more. This feature is useful for the following applicaĆ
tion areas:
Visual multimedia (JPEG, MPEG, etc.)
Shaded mechanical CAD models
Geographical imaging system
Document image management
Visualization
HighĆquality business graphics.
A block diagram of the HP Color Recovery pipeline is shown
in Fig. 12.
The HP Color Recovery encoding scheme causes no loss of
performance for rendering operations and is related to tradiĆ
tional ordered dithering. Dithering is widely used to approxiĆ
mate a large number of colors with an 8Ćbit frame buffer and
is also available in the graphics chip.
The HP Color Recovery decode is much more sophisticated
and based on advanced signal processing techniques. This
circuitry cycles at 135 MHz and achieves over 9 billion opĆ
erations per second. HP Color Recovery is described in more
detail in the article on page 51.
Multiple Color Lookup Tables. Typically, entryĆlevel workstation
and personal computer graphics subsystems have had only a
single color lookup table with a limited number of entries,
usually 256. In the X Window System this results in the anĆ
noying flashing of backgrounds or window contents when a
new application is started that takes colors from existing
 Hewlett-Packard Company 1995
True Color
Image
•
•
•
•
Software Programmable Resolutions. One of the problems of
past workstation graphics subsystems is that they operate at
a fixed video resolution and refresh rate. This has posed
problems in configuring systems at the factory and during
customer upgrades. The graphics chip incorporates an adĆ
vanced digital frequency synthesizer that generates the
clocks necessary for the video subsystem. This synthesizer,
based on HP proprietary digital phaseĆlocked loop technolĆ
ogy, allows software configurability of the resolution and
frequency of the video signal. Thus, alternate monitors can be
connected without changing any video hardware. Currently
supported configurations include:
640 by 480 pixels 60 Hz, standard VESA timing
800 by 600 pixels 60 Hz
1024 by 1024 pixels 75 Hz and flat panel
1280 by 1024 pixels 72 Hz.
As new monitor timings appear, the graphics chip can simĆ
ply be reprogrammed with the parameters associated with
the new monitor.
We created the graphics chip with the philosophies of systemĆ
levelĆoptimized design and optimal use of technology. This
enabled us to meet our goals of very low manufacturing
cost, leadership performance at our cost point, architectural
compatibility, and introduction of some important new
functionality.
This paper briefly summarizes the work of many dedicated
and creative members of the graphics chip development team
in the graphics hardware and software laboratories in Fort
Collins and the Integrated Circuits Business Division. Many
thanks to Harry Baeverstad, Tony Barkans, Raj Basudev,
Dale Beucler, Rand Briggs, Joel BuckĆGengler, Mike Diehl,
Ales Fiala, Randy Fiscus, Dave Maitland, Bob Manley, Dave
McAllister, Peter Meier, John Metzner, Brian Miller, Gordon
Motley, Donovan Nickel, Cathy Pfister, Larry Thayer, Brad
Reak, Cal Selig, James Stewart, and Gayvin Stong for their
exceptional efforts.
April 1995 HewlettĆPackard Journal
(a)
+),-&.+* "/1""*
.&*$(" *! )0(/&,(" +(+- (++'0,
/(". *" +(+- (++'0,
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 Hewlett-Packard Company 1995