! ! & !!
In the HP 9493 LSI test system, CMOS delay verniers replace the usual
bipolar technology and are integrated with digital circuitry to produce a
high-performance timing generator in a single monolithic CMOS VLSI
formatter chip. This solution achieves bipolar-equivalent resolution, skew,
and jitter performance with significantly lower power, cost, and circuit
board space.
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To/From Sequencer
Fail
Logger
Memory
Manager
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Vector
Memory
ACCEL2 Chip
Formatter Logic
Comparator
Logic
Driver
Logic
Timing
Generator
Receiver
Formatter
Multiplexer
To/From Pin Electronics
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Master Clock
PCL
K
reload
Counter
Data
Vernier
Data
Counter
Clock
MC
data
14-bit Counter
Last Flip-Flop
CE1
Digital Section
C
E
Delay
Vernier
FE Out
(To Formatter
and Receiver)
Analog Section
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32)?,%0* 8,) 97)6?463+6%11%&0) 6)73098-32
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78)4 7->) 6)59-6)7 136) 43;)6
Table I
System Requirements for the Delay Vernier
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% ()0%= 0-2) %6',-8)'896) 291&)6 3* ()0%= 0-2) -140)1)2?
8%8-327 ,%:) &))2 6)4368)( #,)7) -2'09() 6%14)( '314%6%?
8367
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-+ Specification
Absolute
Relative
Typical CMOS
±
47°
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± 47
1$
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±°
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617
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27
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*-2)( %7 ()0%= :%6-%8-32 *36 % 7)6-)7 3* )(+)7 4634%+%8-2+
(3;2 8,) 0-2) ;-8, %00 )<8)62%0 -2*09)2')7 '3278%28 #,) 8,-6(
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8,) ',-4 #,-7 4%8, 3''967 32 8,) (6-:) 7-() "-2')
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8,) 4%8, 8,-7 %003;7 8,) 74)'-*-'%8-327 83 &) '314%6)( ;-8,
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7/); 8)14)6%896) ()4)2()2') %2( .-88)6 4)6*361%2') *36 8,)
',-4 %6) 7-+2-*-'%280= &)88)6 8,%2 78%2(%6( "
()7-+2 46%'8-')7 ;390( =-)0(
286-27-' ()0%= -7 7-140= 8,) ()0%= 8,639+, 8,) ()0%= :)62-)6
;-8, 8,) ()0%= 7)88-2+ %8 1-2-191 8 -7 ()7-6%&0) 8,%8 8,-7
CE In
08,39+, 8,) 1908-40)<)( ()0%= 0-2) %6',-8)'896) 6)59-6)7
0)77 43;)6 %2( 7-0-'32 %6)% -8 ;390( 6)59-6) 8,) 0-2) 83 &)
1%() 94 3* )0)1)287 3* (-**)6)28 ()0%=7 74)'-*-'%00= %
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0-2) 1%= ,%:) 2320-2)%6-8-)7 8,%8 '%2238 &) '366)'8)( &= %
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1%8',)7 8%44)( ()0%= 0-2) 7',)1) +6)%80= 6)(9')7 8,)
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()0%= 0-2) 7869'896) -+ &
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;-6)(?OR '-6'9-8 7)0)'87 8,) )(+) %8 :%6-397 43-287 %032+ 8,)
0-2) 463:-(-2+ % 8-1-2+ %(.9781)28 83 % 6)73098-32 3* 32)
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6)59-6)( 4988-2+ %2 )<86% (911= 03%( 32 8,) 8%4 %8 8,) )2(
3* 8,) 0-2) 83 )59%0->) 8,) '%4%'-8-:) 03%( 32 %00 8%4 -24987
)74-8) 8,)7) 1)%796)7 ,3;):)6 %2 %'89%0 ',-4 ;-00 ,%:)
FE Out
1T
2T
4T
(a)
CE In
FE
FE
FE
CE
CE
Multiplexer
FE = Fine Element (Variable)
CE = Coarse Element (Fixed)
(b)
FE Out
% 908-40)<)( ()0%= 0-2)
& #%44)( ()0%= 0-2)
'83&)6 );0)88? %'/%6( 3962%0
Metal-oxide-semiconductor or MOS technology is known to be inferior in noise
performance to bipolar or junction FET (JFET) technology. For example, a CMOS
operational amplifier has two to three orders of magnitude worse noise performance than a bipolar or JFET-input operational amplifier. How about jitter? Jitter
can be defined as a timing uncertainty or noise. If the device is so noisy, won’t the
noise affect its jitter performance? We tried to clarify this question by a theoretical
calculation.
The jitter is evaluated at the mid-transition point of the output of the inverter (Fig. 2).
We assume that the input has already reached the Vdd voltage. Q1 completely
turns off and Q2 discharges the load capacitance Cl.
Fig. 3 shows the equivalent circuit of the flicker and Johnson noise model, where
vj represents the Johnson noise of the equivalent resistance of Q2 and vf represents the input flicker noise.
Major noise sources in a CMOS device are flicker noise and Johnson noise. To
the simple CMOS inverter circuit shown in Fig. 1, we applied a noise model and
analyzed the thermal jitter.
In
Vdd
Q1
In
Out
dt
Q2
Out
Cl
dv
midpoint
GND
Fig. 1. Simple CMOS inverter with load capacitance Cl.
Point of Jitter Analysis
Fig. 2. Jitter evaluation point.
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Bias
Input
Output
Variable
Capacitance
Digital
Control
.$ '4 ' ( )/
Id
0.25
vj
2m
Cl
0.20
T jit (ps rms)
vf
Vdd
Gate
Length
L = 3m
0.30
Out
Q2
GND
0.15
1m
0.10
Fig. 3. Noise jitter model.
0.05
We calculated the voltage noise Vn and the slew rate dV/dt at the output and
estimated the jitter Tjit as
0
0
V
T jit + n .
dVńdt
5
10
15
20
25
30
Gate Width W (m)
Fig. 4. Calculated CMOS inverter jitter.
Fig. 4 shows the result of calculations for various gate lengths L and gate widths
W. Tjit does not exceed 0.3 ps rms even with the worst-case device. A series of 50
such inverters will only produce 2.1 ps rms jitter. While not perfectly accurate, this
analysis provides valuable insight.
coherent with the timing edges. This means we will see the identical coupling
waveform at every test cycle and it won’t cause any jitter.
Another jitter source is coupling noise. This is considered to be a dominant source
of jitter in standard CMOS design. In the ACCEL2 design, we avoided subdividing
the test period or PCLK signals because subharmonics cause periodic jitter. When
the ACCEL2 chip is generating a periodic waveform, all coupling sources are phase
Masaharu Goto
Design Engineer
Hachioji Semiconductor Test Division
* #)/ *,** +'' #/ # % ) ++,) .*
&*% &) # %) +/ &%* )+ &%* * *% % +
#/ # % &%+ %* +.#- #/ #$%+* % *,''&)+ %
), +)/ ) #/ #$%+* ) ,* &) % !,*+$%+
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)(, ) +& %)+ -% #/ ) *+&) % #&&"0,'
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& &% &)* #$%+ &,+',+ & + + ) % #/
#$%+ * ')*%+ +& *-% &)* #/ #$%+* .&*
TIMEDATA [3:7]
RAM
Coarse Registers
Decoder
1
2
3
Register
Register
Register
Register
Register
Register
Register
4
5
6
7
8
9
10
11
Delay Elements
MC
TIMEDATA [0:2]
Multiplexer
CE1
FE Out
CE
CE1
D
Last Flip- Q
Flop 1
CE
Register
D
Last Flip- Q
Flop 2
Delay Element
12
Ref
FE
D
Ref
Phase Q
Detector
PHD Out
PHD Out
MC
(a)
Sweep
Tmc
(b)
#/ -)% ) # )+ &% + $ % .-&)$*
+&) .#++0") &,)%#
).,.9&1 8*99.3,8 &7* &)/:89*) ):7.3, (&1.'7&9.43 94 ,*9 & )*1&>
&8 (148* 94 38 &8 5488.'1* ):22> *1*2*39 &9 9-* *3) 4+
9-* 1.3* .8 :8*) 94 14&) 9-* +.3&1 *1*2*39
"-* )*1&> 1.3* .8 )7.;*3 '> & +1.5@+145 <.9- 89&'.1.?*) 5745&@
,&9.43 )*1&> "-.8 1&89 +1.5@+145 .8 )7.;*3 '> & 84@(&11*) (4&78*
*),* 8.,3&1 ,*3*7&9*) '> & (4:39*7 .3 9-* ).,.9&1 8*(9.43
"-* (14(0 +47 9-* 1&89 +1.5@+145 .8 & 2&89*7 (14(0 9-&9 .8 ':++@
*7*) &3) ).897.':9*) *=(1:8.;*1> 94 9-* )*1&> ;*73.*7 8*(9.43
4+ 9-* (-.5 "-.8 &5574&(- 7*24;*8 /.99*7 43 9-* (4&78* *),*
(&:8*) '> 34.8* ,*3*7&9*) .3 9-* ).,.9&1 8*(9.43 4+ 9-* (-.5
"4 2.3.2.?* .98 4<3 (4397.':9.43 94 /.99*7 &3) 80*< 9-* 1&89
+1.5@+145 .8 )*8.,3*) 94 -&;* & 8-479 (14(0@94@4:95:9 )*1&>
"-* 2:19.51*=*7 8*1*(98 43* 4+ *.,-9 9&58 &143, 9-* )*1&> 1.3*
94 '* ).7*(9*) 94 9-* 4:95:9 "-* 2:19.51*=*7 *1*2*398 &7*
8.251* 9<4@.35:9 NOR ,&9*8 <-48* 4:95:98 &7* (433*(9*) .3
& <.7*)@OR &77&3,*2*39 &3) ':++*7*) '> & +.3&1 .3;*79*7
"-.8 (.7(:.9 .8 )*8.,3*) 94 -&;* 2.3.2:2 5745&,&9.43 )*1&>
<.9-4:9 :3):1> 14&).3, 9-* '&8.( )*1&> *1*2*398 #8.3, 9-.8
&77&3,*2*39 9-* 5745&,&9.43 )*1&> ;&7.*8 +742 842* 2.3.@
2:2 .397.38.( )*1&> ". 94 ". 38 &)/:89&'1* .3 @58 .3@
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,.;*3 '>
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"-:8 9-* 4;*7&11 .397.38.( )*1&> 4+ 9-* 1.3* .8 38
#8*) 431> ):7.3, (&1.'7&9.43 &7* &3 &)).9.43&1 )*1&> *1*2*39
&3) & 85*(.&1 +1.5@+145 (&11*) 9-* 5-&8* )*9*(947 <-.(- .8
)*8.,3*) +47 2.3.2:2 8*9:5 9.2* &3) .8 :8*) 94 )*9*(9 &
2&9(- '*9<**3 9-* 2&89*7 (14(0 +7*6:*3(> &3) 9-* )*1&>
9-74:,- 9-* )*1&> 1.3* "-* 45*7&9.43 4+ 9-.8 &)).9.43&1
(&1.'7&9.43 (.7(:.97> .8 )*8(7.'*) '*14<
"-* 8>89*2 :8*8 & -.,-@6:&1.9> +7*6:*3(> 8>39-*@
8.?*7 &8 & 2&89*7 (14(0 84:7(* 2&89*7 (14(0 +7*6:*3(>
+742 0? 94 ? (&3 '* 574,7&22*) .3 @2.(74-*79?
89*58 <.9- *=97*2*1> 14< /.99*7 &3) -.,- +7*6:*3(> 89&'.1.9>
"-.8 97&381&9*8 94 8:'5.(48*(43) 2&89*7 (14(0 5*7.4) "2(
574,7&22&'.1.9> "-*7*+47* <* )*(.)*) 94 :8* 9-* 2&89*7
(14(0 5*7.4) "2( &8 & 9.2.3, 7*+*7*3(* +47 1.3*&7.9> (&1.'7&@
9.43 8*(43) 1&89 +1.5@+145 )*1&>8 9-* CE 8.,3&1 '> 43* 2&8@
9*7 (14(0 5*7.4) 94 (7*&9* Ref *(&:8* 1&89 +1.5@+145 &3) 1&89
+1.5@+145 &7* .)*39.(&1 &3) &7* 94,,1*) '> 9-* 8&2* MC 9-*
9.2* .39*7;&1 '*9<**3 CE1 &3) Ref .8 *6:&1 94 "2( <-.(- <*
(&3 &7'.97&7.1> (439741 +742 38 94 8 ., ' 8
)*8(7.'*) &'4;* 9-* .397.38.( )*1&> 4+ 9-* )*1&> ;*73.*7 .8
38 *(&:8* 38 .8 9-* 8-479*89 (4397411&'1* 9.2* .39*7@
;&1 <* 3**)*) 94 5:9 &349-*7 )*1&> *1*2*39 &+9*7 FE "-.8
*1*2*39 &))8 &349-*7 38 94 9-* (&1.'7&9.43 5&9- 7*8:19.3,
.3 & @38 2.3.2:2 )*1&> 8*99.3, "-.8 .8 <.9-.3 9-* 7&3,*
4+ (439741 4+ 9-* 2&89*7 (14(0 5*7.4) "2( "-* 9<*1+9- )*1&>
*1*2*39 .8 431> :8*) +47 1.3*&7.9> (&1.'7&9.43 "4 57*;*39 &3
.3(7*&8* .3 .397.38.( )*1&> &3) 9.2.3, 80*< FE )4*8 349 ,4
9-74:,- 9-.8 *1*2*39
(94'*7 *<1*99@&(0&7) 4:73&1
"-* 1.3*&7.9> (&1.'7&9.43 574(*88 +47 *&(- .3).;.):&1 )*1&>
;*73.*7 (438.898 4+ 9-7** 5&798 '.&8 (&1.'7&9.43 +.3*
)*1&> 1440@:5 9&'1* (&1.'7&9.43 &3) (4&78* 7*,.89*7
(&1.'7&9.43
.789 &11 )*1&> *1*2*398 &7* 574,7&22*) 94 & )*+&:19 ;&1:*
"-* '.&8 8*99.3, .8 9-*3 (&1.'7&9*) 94 &)/:89 *&(- *1*@
2*39 )*1&> 94 &5574=.2&9*1> 38 74(*88 ;&7.&9.43 .8
74:,-1> (&1.'7&9*) 4:9 '> 9-.8 89*5 !*(43)1> 9-* +.3* )*1&>
1440@:5 9&'1* .8 (&1.'7&9*) +47 &))7*88*8 94 9
&))7*88 9-* 2&89*7 (14(0 +7*6:*3(> .8 8*9 94 ?
"2( 38 &3) 9-* )&9& <-.(- .8 &551.*) 94 9-*
+.3* )*1&> *1*2*398 .8 .3(7*2*39*) :39.1 9-* )*1&> 9-74:,9-* 9-7** +.3* *1*2*398 *6:&18 9-.8 ;&1:* 9 9-* 3*=9 &))7*88 "2( .8 .3(7*2*39*) '> 58 &3) 9-* )&9&
;&1:* .8 &,&.3 .3(7*2*39*) 94 (&:8* 9-* ;*73.*7 )*1&> 94
2&9(- 9-* (14(0 5*7.4) "-.8 .8 7*5*&9*) 9.2*8 94 (&1.'7&9*
&11 &))7*88*8 <.9- @58 7*841:9.43 "-.7)1> *&((4&78* )*1&> *1*2*39 .8 (&1.'7&9*) 89&79.3, <.9- 9-* +.789
(4&78* *1*2*39 &))7*88 .8 8*1*(9*) 9-* 8*(43) 2:19.@
51*=*7 9&5 .8 8*1*(9*) &3) "2( .8 8*9 94 38 <-.(- .8 38 247* 9-&3 9-* ;&1:* :8*) 94 (&1.'7&9* &))7*88 "-*
(4&78* *1*2*39 7*,.89*7 ;&1:* .8 .3(7*2*39*) :39.1 9-* )*1&>
2&9(-*8 9-.8 (14(0 5*7.4) 11 9-* 7*2&.3.3, (4&78* *1*2*398
&7* (&1.'7&9*) .3 & 8.2.1&7 2&33*7 <.9- 9-* 2&89*7 (14(0 5*@
7.4) .3(7*&8*) '> 38 +47 *&(- 8:((*88.;* *1*2*39 "-*
(4&78* *1*2*39 (&1.'7&9.43 (425*38&9*8 +47 81.,-9 ;&7.&9.438
.3 9-* 2:19.51*= )*1&> 9-74:,- ;&7.4:8 9&58 .3 &)).9.43 94
(&1.'7&9.3, 9-* )*1&> *1*2*39 .98*1+
"-* (-.5 (439&.38 & (&1.'7&9.43 8*6:*3(*7 '14(0
(&11*) 9-* (&1.'7&9.43 14,,*7 <-.(- 8:5*7;.8*8 9-* 5*7@5.3
5&7&11*1 9.2.3, (&1.'7&9.43 "-* (&1.'7&9.43 14,,*7 .3(7*2*398
).,.9&1 9.2.3, )&9& +47 9-* 9-7** 5-&8*8 4+ (&1.'7&9.43 )*@
8(7.'*) &'4;* :39.1 9-* 5-&8* )*9*(947 4:95:9 4+ 9-* 5&79.(:@
1&7 9.2* ;*73.*7 (-&3,*8 89&9* 9 9-* 8*99.3, 9-&9 (&:8*8 9-*
5-&8* )*9*(947 94 (-&3,* 9-* (&1.'7&9.43 14,,*7 89458 .3(7*@
2*39.3, 9-* 9.2.3, )&9& &3) 14,8 9-* ;&1:* 4+ 9-* ).,.9&1 .35:9
:7.3, *&(- (&1.'7&9.43 45*7&9.43 9-* (&1.'7&9.43 14,,*7 (&3
&;*7&,* :5 94 5:18*8 94 57*;*39 4((&8.43&1 34.8* +742
9*72.3&9.3, 9-* 2*&8:7*2*39 57*2&9:7*1> 3 &)).9.43 94
(&1.'7&9.3, 9-* )*1&> ;*73.*78 9-* (&1.'7&9.43 14,,*7 5*7+4728
49-*7 8>89*2 (&1.'7&9.43 &3) )*80*<.3, 45*7&9.438 +9*7 &11
(&1.'7&9.43 14,,*7 45*7&9.438 &7* (4251*9*) 9-* 9*89*7 (43@
97411*7 7*&)8 9-* 14,,*) ;&1:* 94 ,*9 9-* 2*&8:7*2*39 7*@
8:198 !.3(* &11 9.2.3, ;*(947 ,*3*7&947 (-&33*18 .3 9-* 8>8@
9*2 (&3 45*7&9* .3 5&7&11*1 (425:9*7 4;*7-*&) .8 82&11 &3)
<* (&3 5*7+472 +:11 1.3*&7.9> (&1.'7&9.43 4+ & @5.3 8>89*2
<.9-.3 8*(43)8
%-.1* 9-* 54<*7 ).88.5&9.43 4+ &3 )*;.(* 7*2&.38 &5@
574=.2&9*1> (4389&39 +47 &11 45*7&9.3, (43).9.438 & !
)*;.(* (-&3,*8 .98 54<*7 (438:259.43 )7&89.(&11> '*9<**3
9-* 89&9.( &3) )>3&2.( 89&9*8 "-.8 .8 '*(&:8* 9-* 54<*7 7*@
6:.7*) 94 (-&7,* &3) ).8(-&7,* .39*73&1 (&5&(.9&3(*8 <-*3
9-* 34)*8 &7* 94,,1.3, &9 & -.,- +7*6:*3(> .8 2:(- ,7*&9*7
9-&3 9-* 89&3)'> 1*&0&,* 54<*7 "-.8 )>3&2.( 54<*7 ;&7.&@
9.43 .8 & 574'1*2 <-*3 .39*,7&9.3, 57*(.8.43 &3&14, (.7(:.98
&3) & 1&7,* &24:39 4+ ).,.9&1 14,.( 4394 & 8.3,1* ! $!
(-.5 5*7&9.43 4+ 9-* &3&14, (.7(:.9 .8 4+9*3 8*38.9.;* 94
9*25*7&9:7* &3) /:3(9.43 9*25*7&9:7* (-&3,*8 (&:8*) '>
+4+8'22? /4 ! 25-/) *+9/-4 65=+8 */99/6':/54 /9 '2359:
685658:/54'2 :5 )25)1 ,8+7;+4)? "=5 54A)./6 )25)1 4+:=5819
*53/4':+ :.+ 25-/) 56+8':/54 :.+ 3'9:+8 )25)1 MCLK
'4* :.+ 6+8/5* )25)1 PCLK 853 ' 68+</5;9 *+9/-4 =+
,5;4* :.': :.+ *?4'3/) 65=+8 5, :.+ )./6 )5;2* (+ 8+'954A
'(2? 68+*/):+* ,853 :.+ ,8+7;+4)? 5, :.+9+ :=5 )25)19 ".+
MCLK ,8+7;+4)? /9 685-8'33+* (? :.+ :+9:+8 )54:8522+8 '4*
9:'?9 )549:'4: *;8/4- )8/:/)'2 56+8':/54 95 :.+ MCLK *+6+4A
*+4: 65=+8 )'4 (+ )'2);2':+* (? :.+ :+9:+8 )54:8522+8 PCLK /9
'4 +>:+84'2 *':' /46;: 2':).+* (? MCLK /: /4/:/':+9 ' :+9: 6+A
8/5* +)';9+ 8+9+'8). 54 );9:53+8 4++*9 /4*/)':+* :.': :.+
'(/2/:? :5 ).'4-+ :.+ 2+4-:. 5, :.+ :+9: 6+8/5* 54 :.+ ,2?
=5;2* (+ ' ;9+,;2 ,+':;8+ :.+ PCLK ,8+7;+4)? )'4 ).'4-+ ':
'4? :/3+ *;8/4- )8/:/)'2 56+8':/549 ".+8+,58+ :.+ PCLK *+A
6+4*+4: 65=+8 )'445: (+ +9:/3':+* (? :.+ :+9:+8 )54:8522+8
"5 )536+49':+ ,58 *?4'3/) 65=+8 <'8/':/54 =/:.5;: '4?
/4)8+'9+ /4 :5:'2 65=+8 */99/6':/54 =+ *+9/-4+* ' 9:':+
3')./4+ :.': 85;-.2? 354/:589 :.+ '35;4: 5, '):/</:? /4 :.+
25-/) )/8);/:8? '4* *?4'3/)'22? :;849 '4 54A)./6 65=+8 )53A
6+49':/54 .+':+8 54 '4* 5,, /- ' /9 ' )54)+6:;'2 9).+A
3':/) */'-8'3 5, :.+ *?4'3/) 65=+8 )536+49':/54 )/8);/:
'4* /- ( /22;9:8':+9 :.+ 68/4)/62+ 5, 56+8':/54 #.+4 :.+
:+9: 9?9:+3 /9 45: /4 ;9+ '4* MCLK /9 45: 8;44/4- MCSTAT /9
8+9+: MCSTATN : :./9 :/3+ :.+ $ 8+-/9:+8 <'2;+ /9 ,+* :5
:.+ .+':+8 ".+ $ 8+-/9:+8 /9 685-8'33+* (? :.+ :+9:+8 )54A
:8522+8 '9 ,5225=9
$ 6)3'> 3)3'>
=.+8+ 6)3'> /9 :.+ PCLK *+6+4*+4: 65=+8 ': :.+ 3'>/3;3
PCLK ,8+7;+4)? ,6)3'> 45: 9.5=4 /4 /- ( '4* 3)3'> /9
:.+ MCLK *+6+4*+4: 65=+8 ': :.+ 3'>/3;3 MCLK ,8+7;+4)?
,3)3'> : :./9 353+4: :.+ *?4'3/) 65=+8 */99/6':/54 5,
:.+ )./6 /9 @+85 ".+8+,58+ :.+ 9;3 5, :.+ *?4'3/)
65=+8 '4* :.+ .+':+8 65=+8 /9 9/362? $ 6)3'> 3)3'>
".+ :+9:+8 )54:8522+8 9+:9 :.+ % '4* & <'2;+9 9;). :.':
%+ǒ
&+
6)3'> )
6)3'>
3)3'>Ǔ
, 3)3'> * , 3)
, 3)3'>
, 3)
, 3)3'>
#.+4 MCLK 9:'8:9 8;44/4- ': ,8+7;+4)? ,3) MCSTAT *+:+):9
:./9 )54*/:/54 '4* MCSTATN (+)53+9 +)';9+ PCLK /9 45:
:5--2/4- PCSTAT /9 8+9+: PCSTATN '4* %& /9 ,+* :5 :.+
.+':+8 ?4'3/) 65=+8 /4 :./9 9:':+ /9 9.5=4 '9 3)*?4 /4
/- ( ".+ 9;3 5, :.+ *?4'3/) 65=+8 '4* :.+ .+':+8
65=+8 /9 +7;'2 :5 6)3'> 3)3'>
#.+4 PCLK :8'49/:/549 PCSTATN (+)53+9 ,58 MCLK )?)2+9
=./). /9 +7;'2 :5 :.+ 3/4/3;3 PCLK /4:+8<'2 '4* :.+4 8+:;849
:5 ;8/4- :./9 6+8/5* 5, MCLK )?)2+9 :.+ & <'2;+ /9
Z Register
Y Register
X Register
PCL
K
6
PCSTAT
6
6
PCSTATN
Generator
MCLK
Gate
6
Adder
6
MCSTAT
Generator
SET
RST Q
0
MCSTATN
1
Multiplexer
6
Y Register
Strobe
Heater
(a)
Reserve Power
Period Clock Dependent Power
Y
Power
*?4'3/) 65=+8 <'8/':/54 )'4 (+ ' 3'058 95;8)+ 5, /4'));A
8')? ".+ )./6 )54:'/49 -':+9 5, ! 25-/)
'254- =/:. 68+)/9/54 *+2'? <+84/+89 ".+ *?4'3/) 65=+8
<'8/':/54 /4.+8+4: /4 :.+ 25-/) )'445: (+ 4+-2+):+* 58 '
-/<+4 6')1'-+ :.+83'2 8+9/9:'4)+ :.+ 0;4):/54 :+36+8':;8+
='9 +9:/3':+* :5 <'8? (? ° (+)';9+ 5, *?4'3/) 65=+8
<'8/':/54 <+4 =/:. :.+ 8+*;):/54 5, *+2'? :+36+8':;8+ 9+4A
9/:/</:? ',,58*+* (? :.+ );9:53 :/3+ <+84/+8 *+9/-4 :./9 <'8/A
':/54 =/22 ;4'))+6:'(2? *+-8'*+ :.+ 9?9:+3 :/3/4- '));8')?
".+ *?4'3/) 65=+8 )536+49':/54 )/8);/: ='9 *+<+256+* :5
952<+ :./9 685(2+3
Ppcmax
X
Z
Pmcmax
Pmcdyn
Master Clock
Dependent
Power
fmc
Frequency
fmcmax
(b)
' ?4'3/) 65=+8 )536+49':/54 )/8);/: ( 5=+8
8+2':/549./69
-':+* 5,, "./9 *+)8+'9+9 :.+ .+':+8 65=+8 (? '4 '35;4:
+7;'2 :5 :.+ *?4'3/) 65=+8 )549;3+* (? ' 9/4-2+ PCLK
)?)2+ ".+8+,58+ :.+ 9;3 5, :.+ *?4'3/) 65=+8 '4* :.+
.+':+8 65=+8 8+3'/49 6)3'> 3)3'> 8+-'8*2+99 5, :.+ PCLK
,8+7;+4)?
#.+4 MCLK /9 9:566+* (? :.+ :+9:+8 )54:8522+8 MCSTAT /9
8+9+: /33+*/':+2? ',:+8='8*9 95 45 9/-4/,/)'4: 65=+8 -2/:).
=/22 5));8
4 :./9 ='? :.+ :5:'2 65=+8 )549;36:/54 5, :.+ )./6 /9
1+6: )549:'4: "./9 9).+3+ -8+':2? /3685<+9 9?9:+3 :/3/4'));8')?
/- 9.5=9 :.+ 8'= ;4)'2/(8':+* /4:+-8'2 4542/4+'8/:? 5,
:.+ :.8++ ,/4+ +2+3+4:9 3+'9;8+* 54 :.+ )./6 ".+
):5(+8 +=2+::A ')1'8* 5;84'2
Table II shows the measured temperature coefficient of the
propagation delay through the delay vernier circuitry and
CMOS formatter block. As the table shows, the ACCEL2
delay vernier is about three times better than the custom
CMOS formatter circuit. This temperature stability perforĆ
mance is equivalent to bipolar time verniers. In the ACCEL2
chip the overall temperature coefficient was measured as
30 ps/°C.
–1
Nonlinearity (31-ps LSB)
0.5
–0
–0.5
–1
Table II
Temperature Coefficient of Propagation Delay
–1.5
–2
0
20
40
60
80
100
Fine Data
Uncalibrated fine delay element linearity.
fine element nonlinearity is approximately +1.5 LSB of 31Ćps
raw resolution.
Fig. 9 shows calibrated delay vernier linearity. This curve
covers the entire digital input range of 0 to 255, with a correĆ
sponding delay range of 0 to 16 ns. The nonlinearity is exĆ
pressed in terms of the system LSB of 62 ps. As the curve
shows, the linearity calibration guarantees less than ±1 LSB
of integral nonlinearity in the system timing resolution over
the entire delay range.
Jitter measurement was done using an HP 54121T digitizing
oscilloscope with the delay line set at the maximum value of
16 ns. The measured jitter was 3.3 ps rms. Removing the
intrinsic jitter of the HP 54121T (evaluated to be 1.2 ps rms)
resulted in an estimated ACCEL2 jitter of less than 3.1 ps
rms. This is about 0.01% of the path delay, which is one to
two orders of magnitude better than typical digital designs
and better than the specification by a factor of three (see
Table I).
Nonlinearity (62.5-ps LSB)
1
0.5
0
0.15%/°C of path delay
Delay Vernier
0.058%/°C of path delay
Total Critical Path
30 ps/°C
Measurements were also made of the power supply depenĆ
dence of the delay of a critical timing path . The propagation
delay was extremely stable as the Vdd voltage changed.
Integration of delay verniers with formatter logic in the cusĆ
tom VLSI chip ACCEL2 was the key to achieving a lowĆcost,
lowĆpower LSI test system design. By moving the delay lines
onĆchip, the cost and power of the timing system were reĆ
duced by nearly an order of magnitude while at the same
time providing ECLĆequivalent timing performance.
The design was accomplished by a cooperative effort of the
Integrated Circuits Business Division Fort Collins Design
Center and the Hachioji Semiconductor Test Division. We
would like to thank Albert Gutierriz and Chris Koerner for
designing a major part of the delay vernier. Gary Pumphrey
of the Colorado Springs Division contributed key ideas used
in the design of the delay element. Keith Windmiller managed
the project and provided guidance and direction. Barbara
Duffner designed the highĆperformance CMOS formatter and
kept track of many other details during the course of the projĆ
ect. Koh Murata and Kohei Hamada designed the surroundĆ
ing system of the chip. We would also like to thank Larry
Metz and Charles Moore for their invaluable consulting for
the advanced CMOS analog design.
–1.5
–1
0
50
100
150
Delay Data
Calibrated delay vernier linearity.
CMOS Formatter
October 1994 HewlettĆPackard Journal
200
250
300
1. T.I. Otsuji and N. Naumi, A 3Ćns Range, 8Ćps Resolution Timing
Generator LSI Utilizing Si Bipolar Gate Array," Vol. 26, no. 5, May 1991, pp. 806Ć811.
2. T. Ormond, Delay Lines Take on Timing Tasks," December 1991, pp. 108Ć112.
3. C.F.N. Cowan, J.W. Arthur, J. Mavor, and P.B. Denyer, CCD Based
Adaptive Filters: Realization and Analysis," Vol. ASSPĆ29, no. 2, April
1981, pp. 220Ć229.