COMPUTER ARCHITECTURE PROJECT PROPOSAL
COST-BENEFIT ANALYSIS FOR THREAD
SCHEDULING ON ACMP
Anoop Ramakrishna (anoopr) | Kartikeya Goyal (kartikey) | Tejas Chopra (tchopra)
OBJECTIVE
To do a cost benefit analysis of popular thread scheduling algorithms on an Asymmetric Core
Multiprocessor, having multiple large cores and to come up with a smarter scheduling algorithm
to improve throughput
MOTIVATION
Asymmetric Cores target Amdahl's serial bottleneck. ACMPs with ACS target serialization of
execution in multiple threads which share a critical section. In case of multiple independent
critical sections or independent critical sections and serial sections, the problem is of how to
schedule the serial or critical section code to the larger cores. A scheduling policy based on more
rigorous heuristics may provide greater throughput.
RELATED WORK
Much work has been done in the design of Scheduling Algorithms for multicore processors, but
relatively less work has been put forth in Asymmetric Multicore Processors. The technical paper
listed [1] looks at the performance of two scheduling algorithms, namely “Longest Job to Fast
Processor First” (JFPF) and “Longest Critical Job to Fast Processor First” (CJFPF). The study
was carried out on a 2 socket Quad Core Intel Xeon, using speed-step to emulate an AMP.
Work on Accelerating Critical sections in ACMPs [2] was the main motivation factor for this
project as it deals with the very real problem of serialization due to critical sections and provides
a platform for work on scheduling algorithms for the same.
PLAN OF ACTION
1. Modeling an Asymmetric Core of a given specification
a. Initially we plan to use a SCMP and modify one of the cores to provide higher
performance and incorporate Asymmetry. Motivation for this comes from [1].
b. We are using BLESS/ATLAS simulator to model the ACMPs.
2. Applying known scheduling algorithms to the architecture and evaluating performance
and limitations.
COMPUTER ARCHITECTURE PROJECT PROPOSAL
a. We look at the impact of the introduced Asymmetry on some scheduling
algorithms such as LJFPF, CJFPF and others discussed in [1] and [3].
3. Having done extensive evaluation of data from our analyses, we intend to work out
heuristics to be able to develop an algorithm by possibly modifying one of the better
algorithms in a way that we feel would amount to a better throughput.
EXPERIMENTAL METHODOLOGY
The simulator we intend to use i.e. BLESS/ATLAS, which is a component and trace driven
simulator. It will provide us with reconfigurable modules to emulate asymmetric behavior in
multi-core architecture. As a preliminary approach, the larger core will be modeled as a
frequency-scaled version of the smaller cores. This abstraction of an ACMP will initially let us
test scheduling algorithms and evaluate performance benefits achieved out greater processing
power. We are looking at other definite methods to model asymmetry, which may involve
modifying memory topology or the functional capability of the larger core or a combination of
these.
RESEARCH PLAN
Our project essentially involves simulating an Asymmetric Chip-Multi Processor, hence our
preliminary research would be targeted towards techniques that can be employed to create such
an environment like frequency scaling of the cores, using a bigger core, allocating more cache to
one of the cores. The benefit of each of the approaches would be studied and an appropriate
approach will be taken. By milestone 1 we intend to have started testing different scheduling
algorithms on the architecture that we build. This cost – benefit analysis is the primary motive of
our project. We hope to have extensive results on the same by Milestone 2, whereupon we wish
to develop our own rules of thumb and purport an algorithm of our own.
REFERENCES
[1]Asymmetry Aware Scheduling Algorithms for Asymmetric Multiprocessors, Nagesh
Lakshminarayana, Sushma Rao, Hyesoon Kim, School of Computer Science, Georgia Institute
of Technology
[2]Accelerating Critical Section Execution with Asymmetric Multicore Architectures, Suleman,
Mutlu, Qureshi, Patt
[3] Parallel Task Scheduling on Multicore Platforms, James Anderson, John Calandrino