International Journal of Engineering Trends and Technology (IJETT) – Volume 16 Number 3 – Oct 2014
Analysis & Simulation Results of Energy
Efficient One-Bit Hybrid-CMOS Full Adder Cells
Sushil B. Bhaisare1, Dr. S. Shriramwar2
1
Assistant professor in Electronics & communication Department, Nagpur University, ITMCOE, Nagpur, India.
2
Assistant professor in Electronics & communication Department, Nagpur University, PCE, Nagpur, India.
Abstract—The goal of our work is to examine the performance
of One-bit Hybrid-CMOS full adder cells. As Full Adder circuit
is a commonly used in multimedia processors architecture, we
evaluate these circuits in different Hybrid –CMOS logic Styles
for mainly parameter like Power consumption. To achieve a
good-drivability, noise-robustness, and energy efficient
operations for deep-sub micrometer, we explore Hybrid-CMOS
style design [1]. All the circuits have obtained various power
consumption, at various capacitive loads values. Different
circuit structures and input patterns are used for simulation.
Simulation of all circuits has done in T-Spice at 0.18um CMOS
process Technology.
Due to lowering of supply voltages, it arises a problem of
increasing delay and decreasing power- delay products. It
degrades drivability of cells designs with different logic
styles [1].
Keywords— Hybrid CMOS logic styles, deep-sub micrometer
Many previously adders are suffered from the problem of
low swing and high noise when operated at low supply
voltages. The analysis and simulation are proposed for these
full adder circuit have operated successfully at low Vdd’s
with good driving capability and noise robustness.
technology, energy efficient, Delay & PDP.
I.
INTRODUCTION
Adder is a basic element of microprocessors. It is used in
ALU, in Memory generation circuit, etc. Full adders circuits
are used to perform the complex arithmetic operations like
addition,
subtraction,
multiplication,
division
&
exponentiation. Hence we evaluate the overall performance
and complexity of these circuits at transistor level.
Enhancing the performance of the full adders can
significantly affect the whole system performance [1].
To execute an arithmetic operation, a circuit can consume
very low power by clocking at extremely low frequency but
it may increases the propagation delay of a circuit [3].
Reducing the number of and magnitude of the circuit
capacitances, and reducing the spurious transitions in the
output signals are some of the techniques used at the circuit
level to reduced the power consumption [4].
The remainder of the paper is organised as follows. Section
II gives a brief survey of previous work in which logic styles
are compared. Section III consists of simulation and analysis.
Section IV includes graphical comparisons and results and
Section V gives a conclusion and VI has a references.
II. PREVIOUS WORK
It includes scaling of supply voltage, process tolerances,
Power consumption, Delay, Power-Delay Product and
driving capability factors. Actually, various logic styles
favour one of the aspect at the expense of the other factor.
In this, One-bit Hybrid Full adder circuits are examined for
higher speed, less power consumption, higher performance
and reliability by scaling VDD’s towards deep submicrometer technology. Hybrid-CMOS logic styles have a
higher degree of design freedom to target a desired
performance.
Reduction of the Vth and scale down the supply voltages are
the most eminent ways to reduce power consumption.
However Sub-threshold leakage current increases
exponentially when Vth are reduced. At low threshold
voltages, leakage power becomes a issue. At deep submicrometer technology, the advantages of lower VDD’s will
be of no use because of increased leakage power.
ISSN: 2231-5381
A sixteen-transistor CMOS 1-bit full adder cell uses the low
power designs of the basic XOR and XNOR gates pass
transistors, and transmission gates. The cell offers higher
speed and lower power consumption than standard
implementation of the 1-bit full adder cell.
Eliminating an Inverter from the critical path accounts for its
high speed, while reducing the number and magnitude of the
cell capacitances, in addition to eliminating the short-circuit
power component accounts for its low power consumption
[4].
The sum and carry generation circuits of the proposed full
adders are designed with hybrid logic styles. To operate at
ultra-low supply voltages, the pass logic circuit that
cogenerates the intermediate XOR and XNOR outputs has
been improved to overcome the switching delay problems.
Some survival cells in standalone operation at low voltage
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International Journal of Engineering Trends and Technology (IJETT) – Volume 16 Number 3 – Oct 2014
may fail when cascaded in a larger circuit, either due to the
lack of drivability or unsatisfactory speed of operation [6].
On the other hand, dynamic logic facilitates the realization
of fast, small and complex gates. However, this advantage is
gained at the expense of parasitic effects such as load sharing,
A new six-transistor XOR-XNOR cell is designed that does which makes the design process hazardous. Charge leakage
not suffer from the threshold voltage drop in MOS transistors, necessitates frequent refreshing, reducing the operational
but at the same time uses fewer transistors compared to frequency of the circuit.
existing designs. However, more designs effort is needed for At the circuit design level, considerable potential for power
the sizing of the transistors. This new cell can easily be savings exists by means of proper choice of a logic style for
adopted for low voltage operations as long as the supply implementing combinational circuits. This is because all the
voltage is not allowed to fall below 2|Vtp|, [7].
important parameters governing power dissipation—
switching capacitance, transition activity, and short-circuit
In terms of generality and ease of use, as well as voltage and currents—are strongly influenced by the chosen logic style
transistor scaling has considerable advantages of CMOS [10].
logic designs versus other design style such as CPL
especially when cell-based designs are targeted. These logic
a) Impact of logic styles :
styles are compared to the others in terms of some important
parameters such as the number of MOS networks, the Output The logic style used in logic gates basically influences the
driving capabilities, the presence of input/output decoupling, speed, size, power dissipation, and the wiring complexity of
the need of signal rails, and finally the robustness with a circuit.
respect to voltage scaling & transistor sizing [9].
The circuit delay is determined by the number of inversion
levels, the number of transistors in series, transistor sizes (i.e.,
Recently reported logic style comparisons based on full channel widths), and intra- and inter cell wiring capacitances.
adder circuits claimed complementary pass transistor logic Circuit size depends on the number of transistors and their
(CPL) to be much more power efficient than complementary sizes and on the wiring complexity.
CMOS. However, new compassions performed on more Power dissipation is determined by the switching activity and
efficient CMOS circuit realizations and a wider range of the node capacitances (made up of gate, diffusion, and wire
different logic cells, as well as the use of realistic circuit capacitances), the latter of which in turn is a function of the
arrangement demonstrate CMOS to be superior to CPL in same parameters that also control circuit size.
most cases with respect to speed, area, power dissipation, and
power-delay products. The complementary CMOS is the Finally, the wiring complexity is determined by the number
logic style of choice for the implementation of arbitrary of connections and their lengths and by whether single-rail or
combinational circuits if low voltage, low power, and small dual-rail logic is used. All these characteristics may vary
PDP are of concern [10].
considerably from one logic style to another and thus make
The simultaneous generation of XOR and XNOR outputs by the proper choice of logic style crucial for circuit
pass logic is advantageously exploited to a novel performance.
complementary CMOS stage to produce full-swing and Robustness with respect to voltage and transistor scaling as
balanced outputs so that adder cells can be cascaded without well as varying process and working conditions, and
buffer insertion. The increase in transistor count of the compatibility with surrounding circuitries are important
complementary CMOS stage is compensated by its reduction aspects influenced by the implemented logic style.
in layout complexity.
2
αn. Cn + Vdd.
iscn
The driving cell must provide not only full-swing voltage Pdyn=V dd . fclk.
n
n
outputs but also sufficient current to the driven cell.
Otherwise the performance of the circuit will be degraded
dramatically or non operative under low supply voltage. For According to formulae the dynamic power dissipation of a
digital CMOS circuit
the adder cells of TFA and TGA, they cannot be cascaded
depends on the supply voltage Vdd, the clock frequency fclk
without additional buffers attached to the outputs of each cell
, the node switching activities αn , the node capacitances Cn ,
[11].
the node short-circuit currents iscn, and the number of nodes
.
A reduction of each of these parameters results in a reduction
III. SIMULTION AND ANALYSIS
of dissipated power. However, clock frequency reduction is
Different logic styles can be investigated from different point only feasible at the architecture level, whereas at the circuit
of view. Pseudo NMOS technique is straightforward, yet it level frequency is usually regarded as constant in order to
compromises noise margin and suffers from static power fulfil some given throughput requirement. Thus, some
dissipation. Pass transistor logic style is known to be a general logic style requirements for low-power circuit
popular method for implementing some specific circuits such implementation can be stated at this point.
as multiplexers and XOR-based circuits, like adders.

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International Journal of Engineering Trends and Technology (IJETT) – Volume 16 Number 3 – Oct 2014
In VLSI chips [11], electrical energy is converted to heat
energy during operation. The rate at which energy is drawn
from the power supply and converted into heat is the power
dissipation.
For digital CMOS circuits there are two main sources of
power dissipation, dynamic power and static power.
Dynamic power is the power dissipated in the circuit due to
the current flowing while charging or discharging the circuit
node capacitors during transistor switching.
Dynamic power depends on the input pattern applied to
circuit which will cause its transistors either to switch
(consume power), or keep their previous state (no power
consumed).While the static power is the power dissipated
while the circuit is in steady state.
The total power is the sum of the two components,
P avg = P dynamic + P static
The Boolean expression for Sum and Cout for one-bit Full
adder circuit is as follows [1].
S = A xor B xor Cin
S= H xor Cin Where H= A xor B
Cout = A.H’ + Cin.H
This provides a full-swing operation and can operate at low
voltages also. A hybrid-CMOS full adder can be broken
down into three modules. Module I comprises of either a
XOR or XNOR circuit or both. This module produces
intermediate signals that are passed onto Module II and
Module III that generate Sum and Cout outputs, respectively.
The proposed Hybrid full adder circuit can be decomposed
and analysed in three sub modules.
Module-1:
Proposed XOR-XNOR circuit Based on CPL logic using
only one inverter.
Cross-coupled pMOS transistors guarantees Full swing
operation and reduce short circuit current.
Module-2:
Module-2 is a transmission-function implementation of
XNOR function to generate the Sum’ followed by an inverter
to generate Sum. This provides good driving capability to the
circuit. Due to the absence of supply rails there are no short
circuit currents. The circuit is free from the problem of
threshold loss and has the lowest PDP.
Module-3:
Module-3 employs the hybrid-CMOS output stage with a
static inverter at the output. This circuit has a lower PDP as
compared to the other existing designs. The static inverter
provides good driving capabilities as the inputs are
decoupled from the output. Due to the low PDP of module II
and module III, the new adder is expected to have low power
consumption.
The transistors have a channel length of 0.18um and a
channel width of 360nm for NMOS and 720nm for PMOS
using (1.8-0.8V) logic.
All input signals have a rise time and a fall time of 100 ps.
During a simulation session, a single power measurement is
taken by averaging the instantaneous power over a period of
three pattern cycles starting from the beginning of the second
cycle to the end of the fourth cycle.
Propagation delay is the time between the fastest input signal
and the output signal. We use the first rising edge of all
signals at the beginning of the second pattern cycle. The
critical propagation delay is the value of the highest delay
measured for the Cout and Sum output for the different
patterns with a specific load and frequency.
The test vectors for stimulus have been:
A = {00001111}
B = {00110011}
Cin = {01010101}
These test vectors represent all possible combinations of
inputs A, B, and Cin in full adders.
The average power consumption is determined based on an
average power supply current at frequency 50 MHz (input
change every 20ns) over the entire sequence of data inputs
represented by the test vectors. These three parameters
(average power consumption, Delay and power efficiency)
have recorded under varying supply voltages (1.8-0.8V) and
variable output load capacitance.
The following are the resulted waveforms for all the circuit
extracted and simulated in TSPICE which shows the correct
functionality.
Measurement result summary
avgpower = 1.5842e-006
delaytime = 8.3024e-011
Module- 1
Module- 2
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Module- 3
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International Journal of Engineering Trends and Technology (IJETT) – Volume 16 Number 3 – Oct 2014
Parsing
0.02 seconds
Setup
0.01 seconds
DC operating point
0.01 seconds
Transient Analysis
0.30 seconds
Overhead
1.58 seconds
----------------------------------------Total
1.92 seconds
consumption at different loads and at the supply voltage
ranges (1.8-0.8V).
Fig1:Graphs for Average Power Consumtion at fixed 1.8V at
Different loads.
IV. RESULT
The following are the resulted Graphs for all the circuit
extracted and simulated in TSPICE which shows Power
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International Journal of Engineering Trends and Technology (IJETT) – Volume 16 Number 3 – Oct 2014
Fig 2:Graphs for Average Power Consumtion at fixed 1.6V
at Different loads.
Fig 3:Graphs for Average Power Consumtion at fixed 1.4V
at Different loads.
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Fig 4:Graphs for Average Power Consumtion at fixed 1.2V
at Different loads.
Fig 5:Graphs for Average Power Consumtion at fixed 1V at
Different loads.
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International Journal of Engineering Trends and Technology (IJETT) – Volume 16 Number 3 – Oct 2014
Fig 6:Graphs for Average Power Consumtion at fixed 0.8V
at Different loads.
V. CONCLUSION
We mainly concentrate to calculate Power consumption at
different power supplies ranges (0.8-1.8V) for all mentioned
full adder circuits seperately. The circuits were simulated in
T-spice at different Vdd’s, at 50Mhz,25degree celcius.
By varying supply voltages, the power consumptions of
Hybrid-CMOS full adder cell are reduced but as the load
increased, the power consumption are increased at very small
factor.
VI. REFERENCES
[1] Sushil B. Bhaisare, sonalee P. Suryawanshi, Sagar P. Soitkar, “Design of
Low Power One-Bit Hybrid-CMOS Full Adder Cells” (IJETT) Volume4Issue5- May 2013.
[2] Sumeer Goel, Shilpa gollamadi,Ashok kumar and Magdy Bayoumi ,
“ On The Design of Low Energy- Hybrid CMOS 1 Bit Full Adder Cell”
IEEE 2004.
[3] Vahid Foroutan, Keivan Navi,and Majid Haghparst, “ A New Low
Power Dynamic Full adder Cell Based on Majority Funcion”IEEE2008.
[4] Ahmed M. Shyms and Magdy A. Bayoumi “A Novel High-Performance
1-bit Full Adder Cell”IEEE vol.47 No.5,May 2000.
[5] Ahmed M. Shams, and Magdy A. Bayoumi “A Novel Low-power
Building Block CMOS for Adders”.IEEE1998
[6] Ahmed M.Shams,Tarek K. Darwish, and Magdy A. Bayoumi
“Performance Analysis of Low –power 1-bit CMOS Full Adder Cell”.IEEE
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[7] Summer goel,shilpa gollamundi,ashok kumar and Magdy Bayoumi “ On
the design of low-energy Hybrid CMOS 1-bit Full Adder Cell”.2004 IEEE
[9] Bart R. Zeydel, Dursun Baran, IEEE, and Vojin G. Oklobdzija. “EnergyEfficient Design Methodologies:
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[10] Pooja Mendiratta1& Garima Bakshi. “ A Low-power Full-adder Cell
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[11] A. Shams, and M. Bayoumi, “Performance Evaluation of 1-Bit Adder
Cells”.1999 IEEE.
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