International Journal of Engineering Trends and Technology (IJETT) – Volume 12 Number 1 - Jun 2014
Area & Power Efficient LDPC Decoder
Shubham singh1, Nagendra sah2
(1Student and 2supervisor, ECE department, PEC University of technology Chandigarh, India)
ABSTRACT: In this paper we represent an efficient
LDPC decoder for which we simply utilize matrix
multiplication technics. The basic LDPC decoder has
very simple structure, for decoding a string of input is
given as an array, which is processed with an Hmatrix. This gives a decoded output data and
transmitted through communication system. By
direct multiplication we save significant amount of
area and power which is the primary objective of the
paper. At the same time simulation time is less and
coding is short and precise. The decoder designed
here can detect and correct the errors of the
incoming, encoded data signal of 12 bits length. For
simulation we have used Xlinx 14.2 suit and coding
language is Verilog.
Keywords: Matrix multiplication, LDPC decoder, area
and power reduction.
I.INTRODUCTION
In information theory, a low-density parity-check
(LDPC) code is a linear error correcting code, a
method of transmitting a message over a noisy
transmission channel,[1][2] and is constructed
using a sparse bipartite graph. LDPC codes are
capacity-approaching codes, which means that
practical constructions exist that allow the noise
threshold to be set very close (or even arbitrarily
close on the BEC) to the theoretical maximum the
Shannon limit for a symmetric memory less
channel. The noise threshold defines an upper
bound for the channel noise, up to which the
probability of lost information can be made as
small as desired. Using iterative belief propagation
techniques, LDPC codes can be decoded in time
linear to their block length. LDPC codes are also
known as Gallager codes, in honour of Robert G.
Gallager, who developed the LDPC concept in his
doctoral dissertation at the Massachusetts Institute
of Technology in 1960,[3][4].
II.LDPC DECODER
Representations for LDPC codes basically there are
two different possibilities to represent LDPC codes.
Like all linear block codes they can be described
via matrices. The second possibility is a graphical
representation. Matrix Representation Let’s look at
an example for a low-density parity-check matrix
first. The matrix defined in equation (1) is a parity
check matrix with dimension n ×k for a (8, 4) code.
We can now define two numbers describing this
matrix. Wr for the number of 1’s in each row and
Wc for the columns. For a matrix to be called lowdensity the two conditions Wc <<n and Wr<< m
must
ISSN: 2231-5381
H=
01011001
1 1 1 0 0 10 0
00100111
10011010
(1)
In this matrix, each row represents one of the three
parity-check constraints, while each column
represents one of the six bits in the received code
word. Code words can be obtained by putting the
parity-check matrix H into this form [P T | In-k ]
through basic row operations which is called
generator matrix G. Finally, by multiplying all
possible n-bit strings by G, all valid code words are
obtained[5].
The marked path c2 - f1 - c5 - f2 - c2 is an example
for a short cycle. Those should usually be avoided
since they are bad for decoding performance. Be
satisfied, In order to do this, the parity check matrix
should usually be very large, so the example matrix
can’t be really called low-density.
Figure 1: Tanner graph corresponding to the parity
check matrix in equation (1).
2.1.LDPC’s architecture: The circular matrix
permutations that are required for aligning the
message vectors associated with the sub matrices of
a parity-check matrix to the PEs. The Gamma FU is
used to subtract extrinsic value from the current bit
value. In the Alpha-beta FU the minima search and
LLR accumulation operations of the min-sum
algorithm are performed. The new extrinsic value is
recombined with the bit value in the DALU FU.
LMEM is again used as intermediate storage [6]
[7].
Fig 2 data path –LDPC mode
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International Journal of Engineering Trends and Technology (IJETT) – Volume 12 Number 1 - Jun 2014
III.IMPLEMENTATION
In this present paper, a Low-Density Parity Check
decoder is implemented using VERILOG coding
technique. The decoder designed here can detect
and correct the errors of the incoming, encoded
data signal of 12 bits length. For simulation,
synthesis and timing analysis Xlinx 14.2.
Fig 4: waveform for LDPC decoder
Fig 3Symbol for LDPC decoder (Technology
schematic)
4.2 Technology Schematic: This schematic is
generated after the optimization and technology
targeting phase of the synthesis process. It shows a
representation of the design in terms of logic
elements optimized to the target Xilinx device or
"technology”. Viewing this schematic allows us to
see a technology-level representation of our HDL
optimized for a specific Xilinx architecture, which
help us to discover design issues early in the design
process.
To achieve good performance, LDPC codes should
have the following properties:
(a) Large code length: The performance improves
as the code length increases, and the code length
cannot be too small (at least 1K)
(b) Not too many small cycles: Too many small
cycles in the code bipartite graph will seriously
degrade the error-correcting performance.
(c) Irregular node degree distribution: It has been
well demonstrated that carefully designed LDPC
codes with irregular node degree distributions
remarkably out perform regular ones [8].
IV. EXPERIMENTAL RESULTS:
The experiment results are divided into six parts.
Which are simlutaion results as waveform,
technology schematic, RTL schematic, utilization
of resourses , area in terms of LUTs & delay and
cell usage(gates). Steps for simulation in any
coding is development of the algorithm to be
coded..Once the algorithm is ready, coding is
started and different modules are developed. These
modules are independently checked for errors and
later they are assembled to form the exact code.
The whole code is also checked for errors and logic
is checked by simulating the code
4.1 Simulation results: Simultaion is done on
ISIM P.28xd, where 12 bit data is decoded into 6
bit data with help verilog code, for which total
memory usage is 244556 kilobytes. By entering
any value in input array we can obtain decoded
data.
ISSN: 2231-5381
Fig 5: technology schematic-1 for LDPC decoder
4.3 RTL schematic: After the HDL synthesis
phase of the synthesis process, we can display a
schematic representation of our synthesized source
file. This schematic shows a representation of the
pre-optimized design in terms of generic symbols,
such as adders, multipliers, counters, AND gates,
and OR gates, that are independent of the targeted
Xilinx device.
Fig 6: RTL Schematic for LDPC decoders
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International Journal of Engineering Trends and Technology (IJETT) – Volume 12 Number 1 - Jun 2014
4.4 Utilization of resourses : In any design the
utilization of resourses is most important, it defines
the utility of device. For LDPC design made by me
utilization is as follows:
Fig 7. Critical Path
Table 3. Usage of Function blocks
4.6 Cell usage in terms of gates: Following table
gives the usage of gates , flipflpos and I/O buffers.
B
E
L
S
Table 4. Resourse summary of usage of cells
4.5 SYNTHESIS: It is the final step in the design
procedure. Once the code is simulated, synthesis is
done. If the simulated code is not synthesisable,
corrections have to be done to synthesis the code.
4.5.1Area in terms of LUTs and delay: Area of
any design can be measured in terms of LUTs. The
following Table shows the results obtained during
the synthesis of the code which is developed to
implement the LDPC decoder.
A
N
D
2
A
n
d
3
I
N
V
O
R
2
X
O
R
2
F
F
s
L
D
P
C
I
O
B
U
F
F
1
8
I
B
U
F
F
O
B
U
F
F
1
20 1 5 1 14 6 6
1
6
1
3 2 6
2
5
Table 5.usage of fates. Flipflops and I/O buffer
V.APPLICATION OF LDPC DECODER
1.
2.
3.
4.
5.
6.
G.hn/G.9960 (ITU-T Standard for
networking over power lines, phone lines
and coaxial cable)
802.3an (10 Giga-bit/s Ethernet over
Twisted pair)
CMMB(China
Multimedia
Mobile
Broadcasting)
DVB-S2 / DVB-T2 / DVB-C2 (Digital
video broadcasting, 2nd Generation)
DMB-T/H (Digital video broadcasting)
WiMAX (IEEE 802.16e standard for
microwave communications) [9] [10].
VI.CONCLUSION AND FUTURE SCOPE
Table 1 area, delay, PI and Po counts
table 2. Performance summary of LDPC decoder
ISSN: 2231-5381
The decoder for LDPC codes is implemented with
the use of the bipartite graph. This graph is
obtained from the given ’H’ matrix. The code is
first simulated and then synthesised to obtain
detailed analysis of the decoder designed. We
observed that, a high throughput LDPC decoding
architectures should exploit the benefit of parallel
decoding algorithms while reducing the
interconnection complexity. The partially parallel
architecture is a good trade-off between throughput
and hardware cost. The fully parallel LDPC
decoding architecture can achieve high decoding
throughout, but it suffers from large hardware
complexity caused by a large set of processing
units and complex interconnections. A practical
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International Journal of Engineering Trends and Technology (IJETT) – Volume 12 Number 1 - Jun 2014
solution of area efficient decoders is to use the
partially parallel architecture in which a PU is
shared for a several rows or columns. It is
important in the partially parallel architecture to
determine the rows or columns to be processed in a
PU and their processing order. The dependencies
between rows and columns should be considered to
minimize the overall processing time by
overlapping the decoding operations.
REFERENCES:
[1]. David J.C. MacKay (2003) Information theory, Inference
and Learning Algorithms, CUP, ISBN 0-521-64298-1
[2]. Todd K. Moon (2005) Error Correction Coding,
Mathematical Methods and Algorithms. Wiley, ISBN 0-47164800-0
[3]. Larry Hardesty (January 21, 2010). "Explained: Gallager
codes".MIT News. Retrieved August 7, 2013.
[4]. R.G. Gallager, “Low density parity check codes,” IRE
Trans. Inform. Theory, vol. IT-8, pp. 21–28, Jan. 1962.
[5].http://en.wikipedia.org/wiki/Low-density_parity-check_code
[6]. S. Kunze, E Matuˇs, G. Fettweis, T. Kobori.“Combining
LDPC, TURBO and VITERBI Decoder: Benefits and cost”,
978-1-4577-1921-9©2011©IEEE.
[7]. Ashima sood, shubham singh, nagendra sah,“comparative
study of LDPC decoders and Viterbi decoders”,vol2 issue 3
IJSRD may 2014.
[8].Hao Zhong and Tong Zhang, “JOINT CODE-ENCODERDECODER DESIGN FOR LDPC CODING SYSTEM VLSI
IMPLEMENTATION”, ISCAS 2, page 389-392. (2004).
[9]. Li-Hsieh Lin and Kuei-Ann Wen, “A Novel Application of
LDPC-Based Decoder for WiMAX Dual-mode Inner Encoder”,
2- 9600551-5-2© 2006 EuMA
[10]. Ashima sood, shubham singh, nagendra sah,“comparative
study of LDPC decoders and Viterbi decoders”,vol2 issue 3
IJSRD may 20
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