International Journal of Engineering Trends and Technology (IJETT) - Volume4Issue5- May 2013
Clock Gating for Dynamic Power Reduction in
Synchronous Circuits
Dr. Neelam R. Prakash1, Akash2
E&Ec Department, PEC University of Technology,
Chandigarh, India.
Abstract — In this paper clock gating technique is presented
for low power VLSI (very large scale integration) circuit design.
Clock in digital circuits is used for synchronization of various
components. Clock power is a major source of dynamic power
consumed in synchronous circuits. Clock-gating is a well-known
technique to reduce clock power. In clock gating clock to an idle
block is disabled. Thus significant amount of power consumption
is reduced by employing clock gating. In this paper a 4-bit
synchronous counter is designed using clock gating. Simulation is
performed on Xilinx ISE design tool. Experimental result shows
that the clock gating technique significantly improves total
dynamic power consumption. It is observed that approximately
11% of dynamic power is saved.
Keywords—Gated clock, low power design, synchronous
counter.
I. INTRODUCTION
II. POWER CONSUMPTION IN SEQUENTIAL CIRCUITS
Average power dissipated in a digital circuit is given as.
Reducing power consumption in very large scale
integrated circuits (VLSI) design has become an interesting
research area. Most of the portable devices available in the
market are battery driven. These devices impose tight
constraint on the power dissipation. Reducing power
consumption in such devices improves battery life
significantly. Due to lesser advancement in battery
technology, low power design has become more challenging
research area. Power consumed in a digital circuit is of two
types. (1) Static power and (2) Dynamic power. Static power
consists of power dissipated due to leakage currents whereas
dynamic power consists of capacitive switching power and
short circuit power. In VLSI circuit clock signal is used for the
synchronization of active components. Clock power is a major
component of power mainly because the clock is fed to most
of the circuit blocks, and the clock switches every cycle. Thus
the total clock power is a substantial component of total power
dissipation in a digital circuit [4]. Clock-gating is a wellknown technique to reduce clock power. In a sequential circuit
individual blocks usage depends on application, not all the
blocks are used simultaneously, giving rise to dynamic power
reduction opportunity. By clock gating technique, clock to an
idle portion is disabled, thus avoiding power dissipation due to
unnecessary charging and discharging of the unused circuit. In
clock gating clock is selectively stopped for a portion of
ISSN: 2231-5381
circuit which is not performing any active computation [3].
Local clocks that are conditionally enabled are called gated
clocks, because a signal from the environment is used to gate
the global clock signal [2].
In this paper a CMOS clock gated synchronous counter has
been proposed. Section II explains various types of power
dissipated in a synchronous circuit. In section III previous
work in the field of clock gating has been discussed in section
IV clock gating technique is given for a synchronous latch,
and in section V a synchronous counter is designed employing
gated clock. A comparison of gated and non gated clock
circuit is also given in this section.
P average = P dynamic + P short-circuit + P leakage + P static (1)
P average is the average power dissipation, P dynamic is
the dynamic power dissipation due to switching of transistors,
P short-circuit is the short-circuit current power dissipation
when there is a direct current path from power supply down to
ground , P leakage is the power dissipation due to leakage
currents, P static and is the static power dissipation
Fig.1 Sources of power consumption in digital circuits
a) Static Power
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International Journal of Engineering Trends and Technology (IJETT) - Volume4Issue5- May 2013
Static power is the power dissipated by a gate when it is
inactive or idle. Ideally, CMOS (Complementary Metal Oxide
Semiconductor) circuits dissipate no static (DC) power since
in the steady state there is no direct path from Vdd to ground.
b) Dynamic Power
Dynamic power is the power dissipated during active
state due to switching activity of input signal [5]. In other
words, dynamic power dissipation is caused by the charging.
Since an input can change without necessarily resulting in logic
transition in the output, dynamic power can be dissipated even
when an output doesn’t change its logic state. This component
of dynamic power dissipation is the result of charging and
discharging parasitic capacitances in the circuit. Dynamic
power dissipation in a circuit is given as.
PD = α CL VDD2 f
(2)
Where α is the switching activity, f is the operation
frequency, CL is the load capacitance,
VDD is the supply voltage.
technique in reducing clock power in high performance
microprocessors.
Another example of a linear feedback shift register
employing clock gating is presented in [2]. An LFSR is used
for pseudo-random bit generation.
IV. CLOCK GATING TECHNIQUE
Clock power is a major component of power mainly
because the clock is fed to most of the circuit blocks, and the
clock switches every cycle. Thus the total clock power is a
substantial component of total power dissipation in a digital
circuit. Clock-gating is a well-known technique to reduce clock
power. By clock gating technique, clock to an idle portion is
disabled, thus avoiding power dissipation due to unnecessary
charging and discharging of the unused circuit. In clock gating
clock is selectively stopped for a portion of circuit which is not
performing any active computation. This is done by using a
signal from the environment. An example of gated clock is
shown in figure.
c) Short-Circuit Power
The short-circuit power consumption, P short-circuit, is
caused by the current flow through the direct path existing
between the power supply and the ground during the transition
phase.
d) Leakage Power
The PMOS and NMOS transistors used in a CMOS
logic circuit commonly have non-zero reverse leakage and subthreshold currents. These currents can contribute to the total
power dissipation even when the transistors are not performing
any switching action. The leakage power dissipation, P leakage
is caused by two types of leakage currents. a) Reverse-bias
diode leakage current. b) Sub threshold current through a
turned-off transistor channel
(a)
(b)
Fig. 2 (a) synchronous latch without clock gating, (b) gated clock
implementation in latch.
V. DESIGN EXAMPLE AND SIMULATION RESULTS
III. RELATED WORK
A low power 16-bit CMOS synchronous counter is
proposed [1] in which clock gating is used in carry
propagation circuit. 4 local clock generators have been used
for 16 flip flops, each feeding clock to a group of 4 flip flops.
Result shows that proposed design achieves power saving of
64% as compared to conventional design.
In [4] deterministic clock gating technique has been
introduced for a low power microprocessor design.
Deterministic clock gating is based on the observation that in a
pipeline model, usage of a circuit block in near future in
deterministically known a few cycles ahead of time. Using this
information, unused circuit blocks are clock gated. Results
show that deterministic clock gating is very effective
A 4 bit binary synchronous up counter using jk flipflop is
taken as design example in this paper. In a 4 bit up counter
LSB bit toggles for every clock cycle. Whereas higher bits
toggles only if all the lower bits are high as shown in truth
table.
Fig. 3 Truth table
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International Journal of Engineering Trends and Technology (IJETT) - Volume4Issue5- May 2013
A 4 bit synchronous up counter is shown in the figure.
Single clock is applied to all the flip flops of a synchronous
counter. Since the MSB flip flop of the counter is idle most of
the time, an unnecessary clock power is consumed by the
circuit. Therefore to reduce clock power, clock signal to the
flip flops at higher bit positions can be masked for the idle
duration. In this example of gated clock circuit, clock signal is
divided into four parts. LSB flip flop is given original clock
since it toggles for every clock cycle. In order to mask clock
signal to flip flops at higher bit positions during their idle
states, local clock signals are derived. These signals are GC1,
GC2, and GC3 as shown in Fig. 4 (b).
for simulation. Simulation results shows above 11% of
dynamic power saving.
(a)
(b)
Fig. 5. Xilinx XPower analyser results for (a) non clock gated and
(b) clock gated counter.
VI. CONCLUSION
(a)
In this paper a simple method to reduce dynamic power
consumption of sequential circuit is introduced. The proposed
scheme is based on clock gating technique. And gate based
clock gating is used in design example. Power calculation and
simulation is performed on VIRTEX7 family device using
Xilinx ISE design tool. Experimental result shows that clock
gating technique significantly reduces the dynamic power
consumption. Dynamic power of gated clock counter is 8mW
whereas without gated clock the dynamic power is 9mW.
In conclusion clock gating technique significantly reduces
dynamic power of sequential circuit, but may increase number
of logics, and hence area will increase.
(b)
REFERENCES
Fig. 4 (a) synchronous up counter without gated clock
(b) Counter using gated clock.
Design example is simulated on VIRTEX7 family device
using Xilinx ISE design tool. Power calculation is done by
Xilinx XPower analyser. Clock frequency of 50 MHz is used
ISSN: 2231-5381
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[3] Young-Won Kim, Joo-Seong Kim,Jae-Hyuk Oh, Yoon-Suk
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