International Journal of Engineering Trends and Technology- Volume4Issue3- 2013
Performance Analysis of FinFET Device at 60nm
I.Flavia Princess Nesamani#1, Rijo.P.C*2,
ECE Department, Karunya University, Government College Of Technology Coimbatore
Asst.Professor,PG Scholar, Principal
Abstract— A Double Gate (DG) FinFET device with High K
dielectric in 60nm is presented which provides high performance
compared to normal MOSFET device in terms of reduction of
leakage current. A less leakage current is reported with High-K
FinFET device when HfO2 used as High-k material with a
dielectric constant of 25. Sentaurus TCAD tool is used to find
the performance of the FinFET device.
Keywords— DIBL, SiO2, HfO2, DG , SS.
I. INTRODUCTION
In order to overcome lithography and performance gain
challenges, new device structure for next generation
technology have been proposed such as silicon on
insulator(SOI) MOSFET, double gate(DG) MOSFET. FinFET
is a type of double gate device and provides significant
advantages. Double gate FinFET is a promising candidate
because of its quasi-planar structure, excellent roll-off
characteristics, drive current and they are close to their root,
the conventional MOSFET in terms of layout and fabrication.
FinFET devices are explicitly mentioned in the ITRS roadmap
and have a good potential for scaling CMOS to 22 nm and
below[14].The distinct advantages of FinFET are,

Reduced channel and gate leakage currents.

High di-electric constant materials is used in
order to overcome tunneling[11].
The dimensions of the fin determine the effective channel
length and gate width of the device. In this the Source, drain
and channel were designed with silicon material. The TiN
material is used as gate because of its less sheet resistance and
reduced phonon scattering. The fin width is the effective body
thickness, and the fin height is the effective channel width. In
the on state, current flows between the source and drain along
the gated sidewall surfaces of the Si fin. Short-channel effects
(SCE) are suppressed by utilizing a thin body, i.e. by making
the fin very narrow, less than the channel length. Heavy
channel doping is not required for SCE control and hence can
be eliminated to minimize variations due to statistical dopant
fluctuation effects. To maintain proper switching
characteristics and to suppress the short channel effects of
MOS transistors, the downsizing on the gate length requires
an equal factor of decrease in the gate oxide thickness. As the
gate dielectric gets thinner, the gate voltage controls the
channel more effectively [3,5,7]. The effect of DIBL and
SS(Subthreshold Slope) also reduces with thinner gate oxide.
A quasi-linear decrease in DIBL and SS was observed with
varying gate oxide from 1.8nm to 1 nm. But in the case of
SiO2 as gate dielectric, gate leakage current occurs while
reducing the thickness of gate dielectric below 1.2nm.
Introduction of High-k dielectric helps to suppress the gate
leakage current when the scaling goes below 1.2nm
II. DEVICE DESIGN AND SIMULATION
METHODOLOGY
In this paper a 60nm FinFET device is designed for low and
High-k dielectrics. Here SiO2 and HfO2 are used as Low-K and
High-K materials respectively (Table.I). The gate Dielectric
thickness of 1.2nm is used. Ion, Ioff, DIBL and Subthreshold
Swing,Transit Frequency are analyzed using 3-D atomistic
technology computer-aided design mixed-mode simulations.
Sentaurus TCAD tool is used to find out the performance of
the devices.
Fig.1. DG FinFET Device
As shown in Fig.1 the source, drain and fin made up of
silicon material and gate is of TiN material. While using TiN
as gate material it reduces the tunneling current through base
and increase the current from source to drain[2]. Because of
independent gates a better control in the variation of threshold
voltage can be obtained.
TABLE I.DEVICE DESIGN SPECIFICATIONS
PARAMETERS
Length of the gate (Lg)
Gate oxide thickness (Tox)
Thickness of fin (Tfin)
Doping Concentration of source and drain
Doping Concentration for Channel
Dielectrics Used
ISSN: 2231-5381 http://www.internationaljournalssrg.org
DIMENSIONS
60nm
1.2nm
20nm
1e+20
1e+17
Sio2,Hfo2
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International Journal of Engineering Trends and Technology- Volume4Issue3- 2013
III.RESULTS AND DISCUSSIONS
The ON current (Ion) of the device can be defined as the flow
of carriers from source to drain when gate voltage (Vgs ) is
applied[6,8]. The transistor is turned ON when gate voltage
(Vgs) is greater than the threshold voltage(Vt), then there is a
channel is created between source and drain and current flow
occurs[9,10]. For Ion curve, the voltage applied to gate and
drain, 0.2V and 0.8V respectively. The Ioff current for the
device can be defined as the current which flows through the
device when it is in OFF condition.
In FinFETs trans-conductance, gm, is the change in the drain
current divided by the change in the gate or source voltage
with a constant drain or source voltage.
Transit frequency is the frequency at which the small signal
current gain of the device drops to unity, while the source and
drain terminals are held at ground. The transit frequency (fT)
can be calculated as
Cgs = ( WLCox)
fT = {(ε0 εr µn W) / (2∏ ToxLCgs)} (Vgs – VT )
where, µn = mobility of electron ε0 = permittivity of free
space(8.854×10-12 F/m), εr = relative permittivity (3.9 for SiO2
and 25 for HfO2 ), Tox=Oxide thickness, W = channel width, L
= channel length, Vgs= gate-source voltage, Vt = threshold
voltage, Cox = oxide capacitance.
The on current Ids for the device can be expressed as,
Ids=µn Cox Weff / Leff [(Vgs ─ Vth )Vds – V2ds/ 2]
µn= Mobility of electron. Cox = Oxide capacitance
Weff = Effective Channel Width. Leff = Effective Channel
Length.
Vgs = Gate to Source Voltage. Vth = Threshold
Voltage.Vds = Drain to Source Voltage.
The off current for the device can be obtained by putting gate
voltage Vgs =0. Here different voltages are given to gate and
drain in order to get the different current and same threshold
voltages. The voltage given to drain and gate is 0.8V and 0.2V
respectively. When the transistor is turned on (Vgs >Vth) a
channel is created which allows a relatively high current to
flow between the drain and source within the charge-carrier
effective mobility. The off current for the device found by
putting Vgs=0[8].
DIBL is defined as the secondary effect to a reduction of
threshold voltage at higher drain voltages.
DIBL= dVth/ dVd
TABLE III. ION & IOFF CURRENT
Dielectric
Sio2 is a low k dielectric and Hfo2 is a high-k dielectric. The
dielectric constant for the Sio2 and Hfo2 are 3.9 and 25
respectively.
TABLE IIV- DIBL & TRANSCONDUCTANCE
Dielectric
Thickness
SIO2
1.2nm
126
0.045
7
HfO2
1.2nm
120
0.03
19
Ion
current
(A/µm)
Ioff
Current
(A/µm)
Ion/ Ioff
ratio
SIO2
1.2nm
4.6e-06
4.76e-12
0.97e06
HfO2
1.2nm
1.4e-04
1.561e-11
0.89e07
Transit
Frequency
(MHz)
Table.III shows the on current and off current for the FinFET
device using Sio2 and Hfo2. It indicates that the High-K
dielectric ie. HfO2, provides high on current , less leakage
current and high Ion /Ioff ratio compared to the low-K dielectric
ie.,SiO2. Table IV Drain Induced Barrier Lowering (DIBL)
and Tranconductance of 60nm FinFET device. The DIBL is
the capacitance coupling between source and drain as a result
barrier lowering occurs at the suorce side and injects carriers
directly to the drain without gate control.The result shows that
because of High-K dielectric material the DIBL reduced
compared to Low-K dielectric material.
The High-K
dielectric improves the speed of operation of the device in
terms of tranit frequency. Also the transconductance provides
a better result in High-K dielectric material used FinFET.
III. CONCLUSIONS
Double gate FinFET is designed for technology 60nm
technology with various gate dielectrics of Sio2 and Hfo2
having dielectric thickness 1.2nm. By using the Hfo2 as the
gate dielectric reduction in leakage current and improvement
in performance is noted .Also the DIBL, Transit Frequency
and Transconductance at 60nm technology noted. Both are
high in case of High-k dielectric.
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