International Journal of Engineering Trends and Technology (IJETT) – Volume23 Number 2- May 2015
A novel design of multiple input multiple output
basedcommunication system using transceivers
Saran M.L.1, Dr. T.C. Manjunath2, Subiya Yaseen3, Harsha K.3
1, 2, 3, 4
Department of ECE, HKBKCE, Nagawara, Bangalore, Karnataka-560045, India
9916569248 9449820361 8892568292 9686846781
Abstract :-MIMO systems are widely used in baseband
communications and also play a major role in 4G technology.
FPGA based prototyping and implementations of MIMO
systems provide an environment for testing and development of
MIMO based communication systems. The proposed
FPGAbased MIMO system aims at developing a transmitter
system consisting of source, encoder, interleaver, modulator and
a receiver system consisting of ML detector, de-interleaver,
decoder system and a noisy wireless channel which is
represented by a wired channel to which error bits are given to
mimic the noise. The above modules are going to be developed
using Xilinx, simulated and integrated in to the FPGA kit. As a
scope of future work the implemented FPGA based MIMO
communication system can also be modified and extended to
calculate Bit error rate, SNR etc.
Keywords
–:2×2
Transmitter,Receiver
MIMO,
Antennas,
FPGA,
II. OBJECTIVE
The prime objective of the proposed work is to realize a
(2×2) MIMO system on a Field Programmable Gate Array.
The dissertation aims in developing an efficient software
simulation of transceiver system and a noisy channel. The
transmitter section would consist of two transmitters each
consisting of individual encoders, interleavers and
modulators. The receiver section will consist of two
individual receivers each having individual detectors,
demodulators and decoders. After the simulation, the MIMO
system is implemented on an FPGA where input in the form
of binary values would be given to the system through
switches or push buttons and output will be viewed on the
LED display present on the FPGA kit. The work also aims at
evaluating the delay involved in the communication and also
the number of bits involved during the delay time.
I. INTRODUCTION
III. PROPOSED WORK
Multiple Input Multiple Output(MIMO) Communication
System is a new and emerging technology and is expected
to play a very important role in 4G wireless systems.
MIMO systems provide higher bandwidth utilization and
longer range compared to the conventional single input
single output (SISO) technology [1]. FPGA prototyping
of MIMO provides an accelerated and repeatable test
environment in a laboratory setting[2][3].MIMO systems
have evolved rapidly as a generic technology of
communication in 4G wireless systems. It makes use of
multiple antennas both at the transmitter and the receiver
section to make excellent utilization of the available
bandwidth and to reduce the effects of fading and signal
loss[4]. This technique also helps us to increase the
number of bits transmitted i.e. bitrate.
This section will give a detailed description of what the
paper proposes and intents to do starting with a top level
conceptual block diagram of the completely integrated
2×2 MIMO system followed by a Transceiver level block
diagram that shows the transmitters and receivers in the
system.Then the transmitters and receivers are explained
in detail using individual block diagrams of transmitter
and receiver.
CLK
DOUT 1
RST
DIN 1
2×2
MIMO
DOUT 2
DIN 2
An important challenge for the MIMO technology would
be the design of the transmitter and receiver sections
which involves complex algorithms at both sections.The
design and testing part can be simplified by designing the
circuits using hardware description languages (HDL) and
Integrated Software Environment (ISE) which provides
accurate simulations of the design and then synthesizing
the design to an hardware accelerated environment such
as an FPGA [5].This type of prototyping of the MIMO
system will provide an excellent testbed under which
testing of MIMO can be done such as delay in
communication, bit error rate, SNR etc., can be
determined. FPGA prototyping provides verification of
physical layer design ideas and makes the designing more
economical.
ISSN: 2231-5381
Fig. 1: Top level view of integrated 2×2 MIMO communication system
The above figure 1 shows the integrated top level view of
the proposed 2×2 MIMO communication system with the
basic input and output pins. There are two inputs Din1
and Din2 other than the control inputs clock (Clk) and
Reset (Rst) at the input side and two outputs Dout1 and
Dout 2 at the output side.
The main objective of the dissertation work would be a
complete integration of the 2×2 MIMO system using less
number of logical blocks in the FPGA thus increasing its
efficiency and also reducing the delay time for
transmission of bits between the transmitters and the
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International Journal of Engineering Trends and Technology (IJETT) – Volume23 Number 2- May 2015
receivers. Above top level diagram can be split in to a
transceiver level diagram as shown below in figure 2.
from the transmitter are added with error bits to corrupt
the signal which normally happens in a noisy channel.
Now let us consider the individual blocks in detail
The Proposed Generic Transceiver Level Block Diagram
TRANSMITTER 1
CLK
2×1
MUX
TRANSMITTER 1
RECEIVER 1
DOUT 1
SOURCE 1
DIN 1
CONVOLUTION
ENCODER 1
PUNCTURING 1
INTERLEAVER 1
QAM
MODULATOR 1
INTERLEAVER 2
QAM
MODULATOR 2
ERROR
BITS
RST
DIN 1
TRANSMITTER 2
CLK
DIN 1
2×1
MUX
TRANSMITTER 2
RECEIVER 2
DOUT 2
SOURCE 2
DIN 2
CONVOLUTION
ENCODER 2
PUNCTURING 2
ERROR
BITS
RST
Figure 2: Generic Transceiver levelblock diagram of the proposed2×2
MIMO system
The proposed block diagram is explained as
follows…The block diagram of the 2×2mimo system
consisting of two transmitters and two receivers and a
multipath channel are shown in the figure 2. The
transmitter section comprises of a source an encoder that
performs encoding of the source symbols. The encoder is
followed by an interleaver which is used for error
correction during burst error scenarios in the channel.
The interleaver is followed by a modulator that modulates
the symbols and makes them suitable for transmission
through a noisy channel. The output bits from the
transmitter are added with error bits to corrupt the signal
which normally happens in a noisy channel. Two 2×1
MUX are used at the beginning of the receivers so that the
receivers can select only the signal associated for it and
reject the multipath signal.
The receiver section consists of a maximum likelihood
detector which generates an optimal estimate of the
transmitted symbols. The detector is followed by a deinterleaver that performs the inverse of interleaver and
finally a decoder decodes the symbols. The decoded bit
stream will represent the original data transmitted by the
transmitter.
A)TRANSMITTER
Figure 3: Detailed Block Diagram of the transmitter section
IV. PROJECT IMPLEMENTATION AND
SIMULATION REPORT
The dissertation work havecompleted the implementation
of the 2×2 MIMO transmitter module realized by 2 chains
of transmitters as shown in fig 6. Each transmitter
consists of convolution encoder, puncturing, interleaver
and 16-QAM modulator blocks.
A) MIMO Transmitter
MIMO transmitter produces multiple data streams
required for MIMO communication and the output ports
of the transmitter serves as antennas. A horizontal
Encoding (HE) scheme is selected at the transmitter side
with two individual transmitters encoding and
interleaving two independent data streams separately[5].
The implementation is carried out by using the Xilinx ISE
and Modelsim tools.
The Verilog HDL language is used for programming the
module. The figure 7 shows the top level module of the
implemented 2×2 MIMO module. The module has five
inputs
comprising
of
three
control
inputs
clock(clk),reset(rst), enable and two single bit data inputs
din1 and din2.Each transmitter produces two 16 bit
ouputs with a total of four outputs for the 2×2 MIMO
transmitter.
The figure 3 shows a detailed block diagram of the
transmitters which have been realized. The above figure
shows two transmitter sections with all the individual
blocks starting from the source till the modulator. The
two transmitters are necessary for achieving two inputs
i.e. multiple inputs for our 2×2 MIMO.
The transmitter section comprises of a source an encoder
that performs encoding of the source symbols. The
encoder is followed by an interleaver which is used for
error correction during burst error scenarios in the
channel. The interleaver is followed by a modulator that
modulates the symbols and makes them suitable for
transmission through a noisy channel. The output bits
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International Journal of Engineering Trends and Technology (IJETT) – Volume23 Number 2- May 2015
VI. CONCLUSIONS
This paper discusses the physical layer implementation of
a simple 2×2 MIMO communication system in an FPGA.
The paper mainly focuses on the transceiver part and
discusses the design of the complete 2×2 MIMO
transceiver blocks. The paper shows the implementation
of the MIMO transmitter along with the simulation
waveforms for the same.In the future, the aim would be to
implement the Receiver sections of the 2×2 MIMO
comprising of ML detector, decoder etc., which can be
used to detect and receive the data stream from the
transmitter section.
REFERENCES
[1]
Figure 4:MIMO Transmitter Snapshot
Each of the MIMO transmitters internally comprises of a
convolution encoder with a code rate of 1/3, thus
producing 3 bit codeword for one bit input.the output of
the convolution encoder is fed to a puncturing block with
a puncturing matrix length of 14. In the puncturing unit
based on the puncturing matrix contents few of the input
codewords are set to zeros and the other codewords are
transmitted as it is. The punctured convolution encoded
codewords are now interleaved by passing through an
interleaving unit implemented by the block interleaver.
The output of the interleaver is a 3 bit codeword. This
codeword is appended with a single bit zero and is fed to
the 16-Quadrature Amplitude Modulation(QAM) unit.
[2]
[3]
[4]
[5]
V.SIMULATION RESULTS
[6]
The above snapshot shows the complete simulation
waveforms of the SISO module.The important waveforms
from the above figure are the global clock(clk), reset (rst),
enable. Data input 1 (din1)shown in golden color with its
two 16 bit outputs rout1 and imout1 shown in golden
color. Data input 2 (din2) shown in blue color with its two
16 bit outputs rout2 and imout2 shown in blue colors.
[7]
[8]
AmirhosseinAlimohammad and Saeed FouladiFard, “FPGA-Based
Bit Error Rate Performance Measurement of Wireless Systems”,
IEEE Transactions On Very Large Scale Integration (VLSI)
systems, ISSN No:1063-8210,volume 22, Issue: July 2014,
Pages:1583-1592, 21 August 2013.
Numan, M.W, Islam, M.T., Misran.N., “An efficient FPGA-based
hardware implementation of MIMO wireless systems”
Communication Systems Networks and Digital Signal Processing
conference , ISBN: 978-1-4244-8858-2, pages: 152-156, 21-23
July 2010
Alimohammad, S. F. Fard, and B. F. Cockburn, “FPGAaccelerated baseband design and verification of broadband MIMO
wireless systems,” Proc. IEEE 1st Int. Conf. Adv. Syst. Testing
Validation, Sep. 2009, pp. 135–140.
Yu Heejung, Kyon Ghee song, KwhanghuynRyn “Design and
FPGA implementation of MIMO-OFDM based WLAN system”
Vehicular technology conference VTC-2006 spring IEEE 63,
volume 3, pages 1333-1338, 2006.
Paulraj.A.J, Gore.D.A, Nabar.R.U, Bolcskei.H, “An overview of
MIMO communications-a key to gigabit wireless”, Proceedings of
the IEEE, ISSN:0018-9219, volume: 92, pages: 198-218, 08 Nov.
2004.
Murphy.P, Lou.F, Sabharwal.A, Frantz.J.P , “An FPGA based
rapid prototyping platform for MIMO system”, Signal Systems and
Computer Conference 2004, Record of the 37 Asilomar conference
, volume 1, pages: 900-904, 2003.
Jan Meitzner, Robert Schober, Lutz Lampe, Wolf
Gang.H.Gerstecker, Peter.A.Hoer, ”Multiple antenna techniques
for wireless communication-A comprehensive literature survey”,
IEEE Communications survey and tutorials, volume 11, pages 87105, 2009.
Shreyakaushal ,Surabhisharma, “A 2×2 FPGA based Wrap tested
for coloured image transmission in MIMO systems”, International
journal of science and modern engineering, Volume 1, Issue 6,
ISSN:2319-6386, 2013.
Figure 5:simulation output of the 2×2 MIMO Transmitter
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