International Journal of Engineering Trends and Technology (IJETT) – Volume 21 Number 2 – March 2015
A Robust UART Implementation with Built in Self Test
K.Priyanka 1, M.Naga Raju 2, S.Ramya Krishna 3, M.Narendra 4, S.Neelima 5
1,2,3,4
5
UG Student, Electronics & Comm. Engineering, Gandhiji Institute of Sci. & Tech., Jaggaiahpet, A.P, India
Associate Professor& Head, Electronics & Comm. Engineering, Gandhiji Institute of Sci. & Tech., Jaggaiahpet, A.P, India
Abstract: Universal Asynchronous Receive/Transmit
(UART) has the objectives of firstly to satisfy specified
testability requirements, and secondly to generate the
lowest-cost
with
the
highest
performance
implementation. UART has been an important
input/output tool for decades and is still widely used.
The additional BIST circuit that increases the hardware
overhead increases designs time and size of the chip,
which may degrade the performance. This paper focuses
on the design of a UART chip with embedded BIST
architecture using simple LFSR with the help of VHDL
language. The paper describes the problems of (VLSI)
testing followed by the behavior of UART that includes
both transmitter and receiver section using VHISC
Hardware Description Language (VHDL). In this paper,
the simulation result is compared with previous work
and it has been seen that the result is promising and
helps to reduce timing constraints and overall power
dissipation.
Keywords— Detection, Fault, Intermittent, Reliability,
RISC, Microprocessor
in Self test Technique (BIST) is included in the
MECA and in each of Processing Element in
MECA.
I. INTRODUCTION
This project develops a built-in self-detection and
correction
(BISDC)
architecture
for
motion
estimation computing arrays(MECAs).Based on the
error detection & correction concepts of biresidue
codes, any single error in each processing element
in an MECA can be effectively detected and
corrected online using the proposed BISD and builtin self-correction circuits. Performance analysis and
evaluation demonstrate that the proposed BISDC
architecture performs well in error detection and
correction with minor area. In this Project the Built-
ISSN: 2231-5381
Figure 1: BIST Architecture
Thus by introducing the BIST Concept the testing is
done internally without Connecting outside testing
Requirements. So the area required is also reduces.
And in this Project the Errors in MECA are
Calculated and the Concept of Diagnoses i.e. Self
Detect and Self Repair Concepts are introduced.
The area results are compared with the MECA
without
BIST
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technique.
Fig.2
shows
the
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International Journal of Engineering Trends and Technology (IJETT) – Volume 21 Number 2 – March 2015
corresponding BISDC implementation. Signals
to the internal FPGA clock. A reset input is
TC1and TC2 are utilized to select data paths from recommended in case somehow the code gets stuck.
Cur. Pixel and Ref.pixel, respectively.
A transmit button for when we are ready to transmit
our data, and finally we need one output pin. Let’s
see the block diagram in Fig.3.
Figure 2: Block Diagram of Proposed MECA BISDC
The output of a specific PEi can be delivered to a
detector for detecting errors using the DC1 signal.
Moreover, the selector circuit is controlled by
signals SC1 and SC2 that receive data from a
specific PEi+1, and then export these data to the
Figure 3 UART Transimtter
next specific PEi or syndrome analysis and
corrector (SAC) for error correction. Based on the
Ok, for our state diagram, we know a few things
concepts of BIST and biresidue codes, this paper
already. We know that we need a clock to run some
presents a built-in self-detection/correction (BISDC) kind of counter, and we know that our transmitter
to
be
in two
different
architecture that effectively self-detects and self- will always need
corrects PE errors in an MECA.Notably, any array-
states, IDLE and TRANSMITTING.
based computing structure, such as the discrete
cosine transform (DCT), iterative logic array (ILA),
and finite-impulse filter (FIR), is suitable for the
proposed method to detect and correct errors based
on biresidue codes.
State machines will always have two
II. BLOCK DIAGRAM
imporant registers, state and nextstate. These make
First, let’s figure out what pin inputs and outputs
sure that you can transition between states in your
we need. In this case, I will use 8 switches to input
case statement. Next we have to choose the speed
8 bit data that will be sent across the serial
we want to transmit the data at. This is called the
communication output. A clock is a must to connect
baud rate. There are many baud rates and I will let
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International Journal of Engineering Trends and Technology (IJETT) – Volume 21 Number 2 – March 2015
you look them up if you want to, but I will use 9600,
which is pretty standard.
To have this baud rate, a counter is needed:
Counter = FPGA clock speed / baud rate;
In this example I have an FPGA clock speed of
50MHz, therefore my counter is 5208 for the baud
rate of 9600.
Registers - state, nextstate, counter, shiftregister.
inputs - data, clk, reset transmit.
output - TxD.
Is there anything more needed? Yes, more registers,
Why? We have a counter that will count up to a
certain number each time the 50MHz clock ticks,
Figure 4: State Diagram of BIST Transmitter
after it reaches that number, it will do something.
From above, the counter is 5208 for a baud rate of
9600.
We
have
11
bits,
so
we
need bit
counter register to count when we reach the
number of bits sent, so we can stop transmission.
We also need a clear register. This sets the
bitcounter back to zero so that the next transmission
can begin. Finally, a shift register is needed so the
program knows when to shift and prepare the next
bit on the serial line. Now we can start drawing
state diagrams. State Diagrams. Here is the state
diagram for the first part of the program. Anything
to the left of an if statement (the diamond shaped
box) means TRUE and to the right or bottom of the
if statement means FALSE. The transmitter starts in
the zero state, IDLE. Of course, the transmitter
cannot begin in the transmitting state. This is done
by setting your initial state register value to zero.
So what is happening in these boxes? The first box
shows what happens when the program first starts
running. Because no other boxes below reference
back to it, this will only happen when your program
starts. Load, shift and clear are set to zero. This is
because we do not want to shift the shift register
when the program is idling (not transmitting) and
send the wrong information over the serial line. We
also do not want to set the bit counter to zero as it
will not let us increase it when we are transmitting,
and we do not have any data to load from just yet.
In UART communications, the line is held high to
show that nothing is being transmitted (I am talking
about our output TxD). When the line goes low,
both
receiver
and
transmitter
know
that
transmission is about to begin. This is why our start
bit is always equal to zero. When communication is
ready to end, the line goes high again and the
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International Journal of Engineering Trends and Technology (IJETT) – Volume 21 Number 2 – March 2015
transmission stops. This is why the end bit is is sent until the most significant. This means that
always equal to one. The diagram tells us the
the receiver must account for this and know how to
following: We move to the IDLE state and see if
re-arange the data so that it is received in the
the input transmits is 1. This input can be as simple correct order. The state stays in TRANSMIT until it
as a physical switch we press to tell the program we
is equal to 10 and goes back to IDLE. But wait....
are going to transmit. If the transmit is zero, we go
where is the counter we need and all that other stuff?
back to the IDLE state and keep waiting until that
We are not done yet! This is just a state diagram of
switch is pressed. If it is pressed, and then transmit what we are supposed to do. Everything must run
is one and the program moves to the next state,
from the FPGA clock, therefore another "state
TRANSMIT.
diagram" must be created that lets us run the
Transmit just makes sure that the bit counter is not program from the clock and perform all of this
over 11. Remember, we have 11 bits, the start bit, 8 smoothly. So here it goes:
data bits, 1 parity bit and a stop bit. When the bit
First the system is reset. This can be a
counter reaches 11, it means that it has completed
physical switch that sets everything to factory
its task of transmitting. Shift is left high until then.
settings. This is in the case the program deadlocks
We can see that by the left statement of if (bit you can have the option to reset the system without
counter>=10). Remember in Verilog we count the
reprogramming the FPGA. After this, counter starts
zero state, so 10 actually mean 11. When we counting at each positive edge of the FPGA clock.
reached our goal of an 11 bit transmission, the clear
must go high; so to clear the bit counter back to
zero and get ready for the next transmission. Also
the next state must go back to IDLE so that it can
wait for the next time you push the button to
transmit data again. If bit counter is not greater or
equal to 10, naturally we must stay in TRANSMIT
mode and therefore the next State will be
TRANSMIT (1 in this case). Also, we must put
shift to 1 because we want to shift our shift register.
so the next bit can be shifted onto our TxD output
pin to be transmitted. This is done in TxD =
shiftreg[0]. NOTE - Transmission begins from the
least significant and as bits are shifted, one by one
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International Journal of Engineering Trends and Technology (IJETT) – Volume 21 Number 2 – March 2015
When the counter reaches 5208, it is ready xbee at commands: complete architectue of xbee is
to do something. 5208 is the number calculated to
discussed in the next chapter .but during the
get a 9600 baud rate depending on our FPGA clock
implementation the transmitter transmits the AT
speed. In other words, the counter is used to slow
command through uart With the exception of the
down the 50MHZ FPGA clock for our program to
first command (+++) all the following commands
work at 9600 baud. Also, above says 5027 plus zero
should be used while in AT Command mode and
state = 5208. At each time that the counter reaches
the user should press enter after typing the
5208 we set state to next State. Next State is always
command. It is important to remember that the user
changed in the above state diagram, Figure 2. The
should never press the enter key after typing the
reason for doing this is to make the program
Enter AT Command (+++). If you wait three
synchronous to the clock (or counter). Therefore the seconds while inside the AT Command mode the
transition from IDLE to TRANSMIT and vice versa terminal will automatically exit AT Command
only happens at each 5208 count of the counter.
mode and enter back into Chat mode. All other
Counter is also reset each time it reaches 5208 so
typed AT Commands must be followed by hitting
that it can start to count up to 5208 again and do the the enter key. All Commands, unless otherwise
same thing over and over again. NOTE - this state noted, are for Series 2 XBee units.
diagram shows if statements for shift and clear
unconnected. Actually shift, clear and load are
connected to the block statement that load is
connected to so they run simultaniously. Saying this,
At each time the counter reaches 5208 it will check
is load =1? shift = 1? clear = 1? If load = 1 the
rightshiftregister loads the data that is to be
transmitted. This is why, once the state goes from
IDLE to TRANSMIT, load goes high. It ensures
that data is loaded into the register and is ready to
lcd and led display:
be transmitted. When shift is high, rightshiftreg =
rightshiftreg>>1. This is a shift operator in verilog
and shifts the data right one time. Bitcounter is also
incremented once. This tells the program that one
bit was already sent.
the space detected is displayed on both led and
lcd .LCD dislay in 16 bit segment which is capable
of characters and strings .still detail operation are
mentioned in hardware information. fpga contains 8
bit display for on state of signal led glows.
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International Journal of Engineering Trends and Technology (IJETT) – Volume 21 Number 2 – March 2015
III.
SIMULATION RESULTS
For functioning of zigbee module an at command is
being transfered .the result show the strings but
Input clock:
ascii value of the command is transferred an finite
state machine is used to send the each ascii value
Figure 5: Topmodule resultant window
Figure 8: Finite state representation
Fig 5 shows that clock input is triggered for 10 ns
but in fpga implementation clock is 50 mhz .for
every rising edge of the clock pulse the module
initiate transmit or receive the data. DCETX is the
transmitting pin of uart. space is the total space
available for parking.reset is given for 20 ns to
make all states to initilize position and enable is
made zero for 10 ns for which module doesnt work
Figure 9: Transmitter module for uart communication
The bits are sent in a serial order with 9600 baud
rate.
condition.
Figure 6: Transmitting and receiving data
Fig 6 condition signal shows that the AT command
for zigbee module has been transferred and module
is ready to receive the reply from the module.
Figure 7: Transmitting AT command
Figure 10: RTL schematic of top module
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International Journal of Engineering Trends and Technology (IJETT) – Volume 21 Number 2 – March 2015
Author’s Profile
K.PRIYANKA
References
1.
is
a
Graduate student, persuing her
B.Tech in ECE specialization
in Gandhiji Institute of
Science & Technology. Her
interested areas are VLSI,
Signal processing. She is the
Team leader of this project.
M.NAGA RAJU is a Graduate
student, persuing his B.Tech in
ECE specialization in Gandhiji
Institute of Science &
Technology. His interested
area is VLSI.
Chun-lung Hsu, chang-Hsin Cheng, and Yu Liu,
“Built- in self-detection/correction Architecture for
Motion
Estimation
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systems, VOL.18, NO.2, February 2010, pp.319-324.
2.
Thammavarapu R.N Rao, Member, IEEE, “Biresidue
Error-Correcting Codes for Computer Arithmetic”,
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May 1970, pp.398-402.
3.
Meihua GU, Ningmei YU, Lei ZHU, Wenhua JIA,
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and
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H.264/AVC”, Journal of Computational Information
S.RAMYA
KRISHNA
Systems 7:4 (2011), pp.1310-1318.
4.
Zhong-Li He, Chi-Ying Tsui, Member, IEEE, KaiKeung Chan, and Ming L. Liou, Fellow, IEEE,
“Low-Power VLSI Design for Motion Estimation
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5.
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6.
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Razak, “A VHDL Implementation Of UART Design
with BIST capability”
7.
Dr.
T.V.S.P.
Gupta,
Y.
S.RAMYA KRISHNA is a
Graduate student persuing her
B.Tech in ECE specialization
in Gandhiji Institute of
Science & Technology. Her
interested area is Signal
processing.
M.NARENDRA is a Graduate
student persuing his B.Tech in
ECE specialization in Gandhiji
Institute of Science &
Technology. His interested
area is VLSI.
S.NEELIMA is working as
Associate professor & Head
for ECE Dept. in Gandhiji
Institute of Science &
Technology. She has guided
several students in the field of
VLSI and Signal Processing,
VLSI Nano technology.
Kumari,M.Asok
Kumar”UART realization with BIST architecture
using VHDL” International Journal of Engineering
Research and Applications (IJERA) ISSN: 22489622 www.ijera.com Vol. 3, Issue 1, January February 2013, pp.636-640
8.
M.S.
Harvey,Generic
UART
Manual,Silicon
Valley,December 1999
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