International Journal of Engineering Trends and Technology (IJETT) – Volume 8 Number 9- Feb 2014
Source Drain Engineering in FinFET – A Review
I.Flavia Princess Nesamani#1, Rekha Puthenpurayil Divakaran#1,Dr.V.Lakshmi Prabha#2 ,Sujith M.B#1
#1
ECE Department, Karunya University, #2Government College of Technology, Coimbatore
Abstract— Scaling poses many challenges
beyond 22nm technology. In this paper, the
various designs proposed by researchers about
the double gate FinFET with raised source and
drain have been studied. Also the significance of
various parameters, different modes of
operation of the FinFET, effect of fin thickness
over the performance, doping level, effect of
height of source and drain, advantages of using
metal gate electrodes along with high-k
dielectrics have been studied. Different
designing techniques of double gate FinFETs
and its advantages are noted so as to create a
new design for better drive current and low
leakage.
Keywords—Source/Drain
Short Channel effect
engineering,
SOI,
I. INTRODUCTION
Scaling the planar transistors to gate length below
22 nm [1] require high doping of the channel and
source/drain regions to control short channel effect.
As a result random dopant fluctuation [2], [3] and
threshold voltage control has become a major issue.
Random dopant fluctuation is seen in extremely
scaled devices particularly due to the narrow device
width [4]. Double gate MOSFETs has higher
scalability than the single gate ones [5]. A fully
depleted SOI device allows for lighter channel
doping [6] or completes elimination of doping in
order to obtain better threshold variability control
[7].
FinFET with undoped channel [8] is a solution
for the elimination of this serious concern. It is due
to their extremely thin fin structure that makes them
the most unique structure among the multi gate
transistors. This helps to control the short channel
effects and suppress the leakage current between
the drain and source. It has a three dimensional
structure and it operates at low voltage [9] and is
less susceptible to random dopant fluctuation.
ISSN: 2231-5381
Source/Drain engineering is done in order to reduce
parasitic resistance. Thus the drive current will be
high in source/drain engineered devices [10].
Symmetric DG-FETs [11] have both the inversion
channels formed, one adjacent to the first gate and
the other to the second gate.
II. LITERATURE SURVEY
As device is scaled down to nanometer regime,
there arise many problems such as short channel
effects, high leakage current, which seriously affect
the device performance.
A. Effect of Fin thickness and fin height on FinFET
In [12], Fin thickness and fin height are the two
important parameters used to control short channel
effects. Thinner the fin much better is the short
channel effect [13]. In thick fin device, the drain
electric field lowers the barrier of channel because
of reduced source/fin and drain/fin junction
capacitances. Subthreshold slope also increase in
thick fin device. The main reason for this is the gate
loses its control over the channel. Fin-thickness
plays a very important role in deciding SCEs. As
the fin thickness is increased, DIBL also increases.
In [27], Prathima et al. noticed that as the
thickness of the fin was reduced, the off state
leakage current was also found to reduce and when
the fin height is increased, the drive current
capability also increases.
B. Metal gate electrode and work function
In [13], feature such as gate-first metal gate
stacks were included to control the short channel
effectively. By this approach, the metal gate is
formed using HfO2 gate dielectric and metal stacks.
Here author mentioned about double etch method to
define the gate lengths below 25 nm.
In [14], Hamed Dadogur et al. mentioned about
the dependency of metal work function on grain
orientation. The work-function for a solid material
depends on the number of metal atoms per unit area
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International Journal of Engineering Trends and Technology (IJETT) – Volume 8 Number 9- Feb 2014
of the metal surface. Work function is dependent on
the interaction at the metal-dielectric interface. In
[28],Farkanda et al. describes if conventional poly
silicon gate, is not heavily doped, then the carrier
concentration vary and a built in electric field exist,
thereby causing a depletion in the poly silicon/
SiO2 interface.
C. Source/Drain engineering
In [15], diamond shaped epi structure was
proposed here to improve the parasitic resistance
[16]. The main reason for this is due to the 3D
structure with thin Si-body. The structure of the
device has a main role to play in providing a good
result. The source/drain is slightly extended in
width than in the channel region mainly to reduce
the parasitic resistance which is caused by the fin
scaling. Parasitic resistance can be reduced by
either using a raised S/D structure or by using self
aligned silicided S/D. Side wall image transfer (SIT)
technique is also mentioned in here. This technique
is the best for creating the scaled fin. Here the
thickness of the fin is defined by the spacer
thickness. In this technique, first spacers are formed
around mandrels, and after the removal of the
mandrels, Si is etched using spacers which acts as a
mask and finally the fins are formed.
In [17], the author describes about the spike
annealing. It is mentioned that spike annealing can
suppress lateral diffusion in source/drain extension.
In [18], Xiao Gong et al. reported about
source/drain engineering technique in N-channel
MOSFET featuring the in-situ doping of the
source/drain with InGaAs which has very high
mobility. By implanting Si in InGaAs S/D regions
does not bring high doping concentration, which
will lead to high S/D series resistance and better
drive current performance.
D. Independent gate and tied gate mode
In [19], Dhruva Ghai et al. describes about tied
gate mode and independent gate mode. Tied gate or
Shorted gate(SG) has smallest delay, followed by
Independent gate. For power consumption, Low
Power(LP) mode gives the lowest power
consumption, followed by IG and SG mode. In
independent gate FinFET the top region of the gate
is removed and both the gates are biased separately,
whereas same voltage is applied to both the gates of
the tied gate FinFET. In [20], Masoud Rostami et
ISSN: 2231-5381
al., describes about the electrostatic force coupling
both the gates together, due to this force the channel
formed due to one gate is highly dependent on the
other. If no voltage is applied to the back gate of an
independent gate FinFET, no channel is formed
near the inactive gate, but this will affect the
threshold voltage of the other gate. In short if any
one of the gates is disabled then the drive current of
the device is reduced by half. The input capacitance
of the disabled gates is half that of conventional tied
gate FinFET.
In [21], author mentions that tied gate has high
drive current and leakage current than that of the
independent gate FinFET. In independent gate, the
back gate bias is to alter the threshold voltage of the
front gate.
In [26], author concludes that tied gate FinFET is
a better option for high performance design.
Symmetric and asymmetric gate work-function
In [21], [22], author refers the symmetric gate
work-function FinFETs as one with both the front
and back gates with same work-function and if both
are of different work-function, then it is called
asymmetric gate work-function FinFETs. It is also
suggested that it is more practical to use
asymmetrical gate work-function FinFETs for ultra
low leakage designs.
E.
Parasitic capacitance
In digital application, the main aim is to have
lower capacitance and high drive current. As
scaling is achieved and when it reaches the
nanometer regime, the gate capacitance including
the intrinsic capacitance and parasitic capacitance is
not reduced as the gate length is reduced and this is
mainly due to the excessive parasitic capacitance.
So to improve the performance of the device,
parasitic capacitance reduction is important.
In [23], Bhoj el al. mentioned about the parasitic
capacitances in multifin multigate FET and in
multigate SRAM. The fin pitch which is the
distance between the centers of the two consecutive
fins is varied and the parasitics were calculated for
each layout. The total drain capacitance increased
in bulk FETs by 11.5% when compared with SOI
FETs for 22 nm node. This increase in the bulk
device is mainly due to the shared drain-to-bulk
capacitance. In case of total gate capacitance, there
is only a slight increase from SOI to bulk. Also
F.
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International Journal of Engineering Trends and Technology (IJETT) – Volume 8 Number 9- Feb 2014
wordline, internal node and bitline capacitances
were measured in the case of multigate SRAM.
In [24], Joshi et al. presented SOI SRAMs for
3D TCAD capacitance extraction assisted with
hardware data. This method consists of three
segments, iterative BEOL analysis, iterative FEOL
analysis and iterative yield analysis. In all these
three cases, the input layouts were converted to 3D
structures and then transport analysis based
capacitance extraction was performed.
Effect of gate oxide thickness on FinFET
In [25], Yee-Chia Yeo et al. says reducing the
gate oxide thickness increases the drain current. As
the scaling is increased further, the use of SiO2
becomes inapplicable. The main reason for this is
the increased penetration of dopants into the
channel region. The main challenge to further
MOSFET scaling is the increased leakage current.
Scaling of gate oxide below 1.2 nm leads to
increase in gate electric field.
In [28], the requirement of ultra thin oxide is
mentioned for scaled sub-50nm MOSFETs, thereby
increasing the gate leakage current which is caused
by direct tunnelling current and this increases the
power consumption and hence deteriorates the
device performance.
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III. CONCLUSIONS
Different FET parameters were studied and it is
found in most of the literatures in scaled down
technology, that metal gates are completely
replacing the conventional poly silicon gates and
conventional gate dielectric material i.e. SiO2 is
being replaced by high–k dielectric materials. The
FET parameters such as fin thickness, fin height,
gate length, and gate oxide thickness all affect the
performance of the device. Thinner fin is found to
have better short channel control, taller fin is best
when high drive current is preferred. Advantages of
shorted gate were noticed and it is suited for high
performance design. So by creating a design by
keeping these parameters in mind would obviously
bring out some better results which can further be
extended to various analog and digital circuit design
application.
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