International Journal of Engineering Trends and Technology (IJETT) – Volume 6 Number 3- Dec 2013
High Speed Design of Ethernet MAC
Bolleddu Alekya 1
P. Bala Nagu 2
1 PG Student (M. Tech), Dept. of ECE, Chirala Engineering College, Chirala, A.P, India.
2 Associate Professor, Dept. of ECE, Chirala Engineering College, Chirala, A.P, India .
*
Abstract: Nowadays, Ethernet technology is the most widely used network technology, and
also widely used in plenty of industries, such as finance, business by means of its efficiency,
high-speed and high performance. Gigabit Ethernet can provide communication bandwidth
with 1 GB/s. Because it uses the same CSMA/CD protocol, frame format, frame length as the
traditional 10/100M Ethernet network, so it is able to realize internet update smoothly and
continuously based on the original slow Ethernet to protect user investment utter mostly. But
in many applications, it calls for the realization of high-speed network data transmission
without using the NIC (Network Interface Card) of PC, and transmitting the post processing
data to Gigabit Ethernet. Then describes software design written by Verilog HDL in detail,
including reset and initialization of the transmission of data packets. After testing, the
transmission rate can reach our goal. The results show that this design meets most
requirements of the real-time transmission system and proves to be a practical design with low
cost and good stability.
Keywords: MAC, CSMA Protocol, High Performance, VHDL.
slow
1. Introduction
Nowadays, Ethernet technology is
the
most
widely
used
network
Ethernet
investment
to
mostly.
protect
But
in
user
many
applications, it calls for the realization
technology, and Gigabit Ethernet is
of
also
of
transmission without using the NIC
industries, such as finance, business
(Network Interface Card) of PC, and
by means of its efficiency, high-speed
transmitting the post processing data
and
to
widely
high
used
in
plenty
performance.
Gigabit
high-speed
Gigabit
network
Ethernet.
This
data
system
Ethernet can provide communication
adopts FPGA and Gigabit NIC to meet
bandwidth with 1Gb/s. Because it
the needs.
uses the same CSMA/CD protocol,
The Ethernet Mac core consists of
frame format, frame length as the
five modules:
traditional
Ethernet
•Host interface connects the Ethernet
network, so it is able to realize
Core to the rest of the system via the
internet
Wishbone
10/100M
update
smoothly
and
(using
DMA
transfers).
continuously based on the original
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International Journal of Engineering Trends and Technology (IJETT) – Volume 6 Number 3- Dec 2013
Registers are also part of the host
wait for the current transmission to
interface.
end.
•TX Ethernet MAC performs transmit
function.
Frame
structure
of
Ethernet
Mac core is :
•RX Ethernet MAC performs receive
function.
•MAC Control Module performs full
duplex flow control function.
•MII Management Module performs
Preamble: A 7 bytes
pattern of
PHY control and gathers the status
alternating 0’s and 1’s used by the
information from it.
receiver
All modules together perform a full
to
establish
bit
synchronization.
function 10/100 Mbit/s Media Access
Start
Control.
sequence 10101011, which indicate the
The
Ethernet
core
can
of
frame
delimiter:
The
operate in a half or a full duplex
actual start of the frame.
mode. The basic of the Ethernet is
Destination
CSMA/CD protocol. The CSMA/CD
station for which the frame is intended.
stands for Carrier Sense Multiple
It may be a unique physical address, a
half
duplex
mode
specifies
the
group address or a global address.
Access / Collision Detection.
In
Address:
when
a
Source Address: specifies the station
station wants to transmit, it has to
that sent the frame.
observe the activity on the media
Length: length of the LLC data field.
(Carrier Sense). As soon as the media
LLC data: Data unit supplied by logic
is idle (no one is transmitting), any
link control (LLC).
station
the
Pad: Bytes added to ensure that frame
transmission (Multiple Access). If two
is long enough for proper collision
or more stations are transmitting at
detection operation.
the same time, a collision on the
Frame Check Sequence (FCS):A 32 bit
media is detected. All stations stop
cyclic redundancy check, based on all
transmitting and back-off for some
fields except the preamble, sfd and
random time. After the back-off time,
FCS.
can
start
with
the station checks the activity on the
media again. If the media is idle, it
starts transmitting. All other stations
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RX Ethernet MAC:
2. ABOUT ETHERNET-MAC
RX
Ethernet IP Core consists of 5
Ethernet
MAC
interprets
10BASE-T/100BASE-TX MII receive
modules as shown in fig.1.
data
nibble
stream
and
supplies
correctly formed packet byte streams
to the host. It searches for the SFD
(start
frame
delimiter)
at
the
beginning of the packet, verifies the
FCS and detects any dribble nibbles
or receive code violations.
MAC Control Module:
The function of this module is to
implement
Figure 1 Ethernet IP Core
The host interface is connected to
the RISC and the memory through the
Wishbone. The RISC writes the data
for the configuration registers directly,
while the data frames are written to
the memory. Frames are accessed
through the DMA.
MAC
generates
10BASE-T/100BASE-TX transmit MII
nibble data streams in response to
the byte streams supplied from the
transmit logic (host). It performs the
required
deferral
and
back-off
algorithms, takes care for the IPG,
computes the checksum (FCS) and
monitors
monitoring
the
physical
Carrier
collision signals).
flow
consists of three sub modules that
provide the following functionality:
• Control frame detection
• Control frame generation
• TX/RX Ethernet MAC Interface
• PAUSE Timer
• Slot Timer
Control Frame Detector
TX Ethernet MAC:
Ethernet
full-duplex
control. The MAC Control Module
Host Interface:
TX
the
media
Sense
(by
and
Checks the incoming frames for
the
control frames. Control frames
can be discarded or passed to the
host. When a PAUSE control frame is
detected, it can stop the TX module
From transmitting for a certain period
of time.
Control Frame Generator
When there is a need to stop the
transmitting
transmission
station
(flow
from
control
in
full
duplex mode), a PAUSE control frame
can be send to it.
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the
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International Journal of Engineering Trends and Technology (IJETT) – Volume 6 Number 3- Dec 2013
TX/RX Ethernet MAC Interface
Output Control Module
MAC Control module is connected
Controls the signal appearance on
between the host interface and the Tx
the MDO, MCK and MDOEN pins.
and the Rx MAC modules. Signals
Shift Register
from the host are passed by to the Tx
Holds the status read from an
MAC in certain occasions and vice
external PHY.
versa.
Clock Generator
PAUSE Timer
Generates an appropriate output
When a PAUSE control frame is
clock MCK according to the input
received, the pause timer value is
host clock and the clock divider bits.
written to the PAUSE timer. This
TRANSMITTER ETHERNET MAC
prevents
the
Tx
module
from
TxEthMAC implements CSMA/CD
transmitting for a »pause timer value«
protocol when transmitting packets of
period of slot time.
data. Before transmitting packets of
Slot Timer
data, TxEthMAC must assure that
Slot timer measures time slots and
medium is idle and then monitors
generate a pulse to the PAUSE timer
medium continuously if there is a
for every slot time passed by.
collision in the middle of transmit
MII Management Module
process.
If
collision
happened,
The function of this module is to
TxEthernet - MAC makes back off
control the PHY and to gather the
operation and retries to transmit after
information from it (status). The MII
a random period depends on number
Management Module consists of four
of collision attempt. The transmit
sub modules:
process can be aborted or dropped if
Operation Control Module
one of the following conditions is
Output Control Module
detected:
Shift Register
• excess
Clock Generator
TxEthernet
Operation Control Module
-
occurs
MAC
when
can't
get
opportunity to transmit longer than
The function of this module is to
perform the following commands:
Write control data
deferral,
twice maximum length of Ethernet
frame
• late collision, occurs when collision is
Read status
detected after 512 bits of data has
Scan status
been transmitted excessive collision,
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International Journal of Engineering Trends and Technology (IJETT) – Volume 6 Number 3- Dec 2013
occurs
when collision is
detected
more than 15 times
• under run, occurs when host can't
provide nibbles of data for transmit
operation
• excessive length, occurs when the
length of packet is longer than 1518
bytes
Clock is provided by MII through
tx_clk, which frequency is 2.5 MHz
when operates at 10 Mbps and 25 MHz
when operates at 100 Mbps.
Figure 3 Transmitter State Machine
The function of this module is to
control transmit process. When host
has packet of data to be transmitted,
tx_sof will be activated. Then, the
State
Machine
will
give
transmit_new_p signal to restart Defer
Counter and Collision Counter and
Figure 2 Block Diagram of Transmitter Ethernet MAC
TX
Ethernet
MAC
consists
of
eleven modules. They are listed below:
1.
FIFO Synchronization
2.
IFG Timer
3.
Defer Counter
4.
Frame Length Counter
5.
Collision Counter
6.
Random Number Generator
7.
Back off Timer
8.
Jam Timer
9.
CRC Generator
10.
Data Multiplexer
11.
TX State Machine
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wait until transmit_available_p from
IFG
Timer
is
detected
to
get
opportunity to transmit Preamble and
SFD.
When
transmit_available_p,
waiting
the
State
Machine monitors excess_deferral to
limit
waiting
time
for
transmit
operation. After IFG has passed and
transmit
operation
has
got
opportunity, the State Machine will
give appropriate data_select signal to
Data Multiplexer.
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International Journal of Engineering Trends and Technology (IJETT) – Volume 6 Number 3- Dec 2013
And it will assert transmit_enable
compute_crc signal. While transmit
to FIFO Synchronization, Collision
operation
is
Counter, Frame Length Counter, and
Machine
monitors
IFG Timer. The State Machine will
coll_event_p,
also
to
continuously. If detected, transmit
by
operation will be aborted or dropped.
transmit_sfd. The Preamble Field will
If coll_event_p is detected, the State
be
Machine will give tx_retransmit and
give
transmit_preamble
Collision
Counter
followed
transmitted
if
the
running,
and
the
State
tx_underrun,
excessive_length
transmit_available_p is detected until
start_backoff
the next 15 clock cycles then SFD
deasserts
Field will be transmitted for one clock
compute_crc, and tx_data_used. The
cycle.
The
Data
transmitted
if
Field
the
will
be
following
value
of
backoff_p
pulse
signal,
and
transmit_enable,
operation
and
is
waiting
then
count_length is greater then 16 until
transmit_enable
tx_eof
transmit operation from the beginning
is detected. But,
the
PAD
detected
of
transmission because late collision
count_length is less than 136, which
and or excessive collision is detected.
is the minimum length of Data field
If transmit operation terminates in
added by Preamble and SFD Field,
normal condition or because any error
and will be deactivated if the value of
conditions, the State Machine will
count_length reaches 136. The FCS
dessert transmit_enable and followed
field will be transmitted if tx_eof is
by status signal.
detected
and
the
value
value
of
count_length is greater than or equal
to 136. If Data Field starts to be
transmitted,
tx_data_used
and
compute_crc are asserted. Then, the
State Machine will monitor tx_eof that
indicates the last nibble of data is
placed in tx_data. If tx_eof is detected
active and Tx Eth MAC doesn't have
to
send
Machine
PAD
will
pattern,
give
the
State
transmit_fcs
to
or
restart
of
the
Field
to
pattern will be transmitted if tx_eof is
when
Preamble
again
asserts
abort
3. Results and Conclusions
In this project we evaluated the
integration
of
packet
switching
capabilities in 10 MAC GbE Ethernet
Transmitter
devices.
The
MAC
architecture was first analyzed to
design a switching system that can
exploit the processing mechanism of
the MAC Ethernet Transmitter layer.
In particular, the latency introduced
to compute the CRC was used to
Frame Length Counter and deassert
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International Journal of Engineering Trends and Technology (IJETT) – Volume 6 Number 3- Dec 2013
implement
a
classification
module
that does not add extra latency.
The
proposed
implemented
and
architecture
validated
was
on
a
synthesizer. Its resource demand was
evaluated to address the scalability of
the architecture and to detect the
most demanding modules. Modelsim
Xilinx
Edition
will
be
used
for
functional simulation and verification
of results. Xilinx ISE will be used for
Figure 5 Technology Schematic View
synthesis. Fig 4 & 5 shows the RTL
Schematic & technology schematic of
the proposed system. Fig 6 Shows the
Simulation Result of the proposed
system.
The
Design
utilization
summary of the Designed Ethernet
MAC is shown in Table-1.
Figure 6 Transmitter Ethernet MAC Simulation ResultsTransmitter Waveform
Table-1
Device Utilization Summary (estimated values)
Logic Utilization Used Available Utilization
Figure 4 RTL Schematic
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Number of Slices
215
768
27%
Number of Slice Flip
Flops
140
1536
9%
Number of 4 input
LUTs
400
1536
26%
Number of bonded
IOBs
30
124
24%
Number of GCLKs
1
8
12%
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International Journal of Engineering Trends and Technology (IJETT) – Volume 6 Number 3- Dec 2013
Acknowledgements
the
International
Conference
The authors would like to thank
Microelectronic
anonymous
2007.
reviewers
for
their
[7]
improving the quality and presentation
Performance
of this paper.
Hoboken, New Jersey: John Wiley & Sons
Connectivity for Computer Servers,” IEEE
J.
Chao
and
Education,
comments which were very helpful in
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