International Journal of Engineering Trends and Technology (IJETT) – Volume 5 Number 7- Nov 2013
A Portable and Wide Banded High-Speed ADPLL Using
Novel Compensation Technique
1
2
1
Appala Raju.k
Y.Phani Kumar
M.Tech, E.C.E Dept, Amrita Sai Institute of science & Tech, Paritala
2
Assist.Prof, Amrita Sai Institute of science & Tech, Paritala
ABSTRACT:
Spice simulator to explore the PLL
Designing of a fast locking ADPLL is
architecture due to its simulation speed
proposed in this thesis. Main intention in
and sometimes it is even impossible due to
this project is to reduce Locking time in
its inability to simulate the noise in a
ADPLL
feed-forward
complex system. In order to solve the
Frequency
speed problem of the Spice simulation,
by
compensation
divider
is
using
algorithm.
fully
reused
and
further
phase-domain simulation technique was
predicted error due to the estimation errors
used.
and the stabilities of the proposed ADPLL
simulation is only useful for predicting the
during the frequency acquisition mode and
loop dynamics and gives little intuitive
phase acquisition modes are implemented
insight into the circuit itself especially for
with more stability.
the beginners. Moreover, the phase domain
KEYWORDS: ADPLL (All Digital Phase
simulation can not be used to evaluate the
Locked
Forward
phase noise performance which is the most
Compensation Technique, charge-pump,
important feature in a PLL system. Analog
Digital Controlled Oscillator, Loop filter,
PLLs (Fig. 1) have been investigated for
Loop Controll.
the past several decades. As a result,
INTRODUCTION:
different types and orders of analog PLLs
It is a well known issue that the phase
have been analyzed and procedures for
locked loop (PLL) simulation by Spice-
their design have been developed. Second-
like simulator is time consuming. In order
order analog PLLs have been analyzed by
to predict the noise in a circuit, Spice
Hein and Scott [5] and Gardner [6].
needs a quiescent operating point which is
Several other references [7]–[9] provide an
not always the case in a PLL circuit [1].
analysis and design procedure for third-
This means that it is impractical to use
order charge-pump PLLs (CPPLLs). But
Loop),
ISSN: 2231-5381
Feed
However,
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the
phase
domain
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International Journal of Engineering Trends and Technology (IJETT) – Volume 5 Number 7- Nov 2013
there is only limited research dedicated to
the analysis of all-digital PLLs (ADPLLs).
OVERVIEW OF ALL-DIGITAL PLLS
A simplified block diagram of the alldigital PLL for a microprocessor or serial
link application is shown in Fig. 2. It
consists of a phase-to-digital converter
(P2D), a digital loop filter (LF), a digitally
controlled
oscillator
(DCO),
and
a
feedback divider. The P2D senses the
phase difference between the reference
Clock Fref
and the DCO divided clock
FCKV and converts it to a digital format.
This information is filtered by the firstorder digital LF and then is used to control
the DCO. In the case of a ring-oscillatorbased DCO, frequency tuning can be
performed by digitally turning on and off
bias current sources. When an LC-based
DCO is employed, frequency tuning is
done by switching on and off the tank
capacitors. The P2D can be implemented
Fig. 1. Typical implementation of a P2D
converter
They are overlapped by an OR gate to
create a pulse, the width of which is
proportional to the absolute value of the
phase error. The width of this pulse is
digitized by a TDC with a resolution
DELTA
and
an-bit
output
ABS
is
produced. The D-flip-flop samples the UP
pulse on the rising edge of the DN pulse.
In
this
manner,
the
sign
of
the
phase/frequency error can be determined.
inmany differentways. Oneway, shownin
Fig.
1,
features
phase/frequency
a
conventional
detector
(PFD)
followedby a time-to-digital converter. It
is beneficial to use a PFD instead of just a
phase detector in order to expand the
frequency lock range. ThePFDproduces up
(UP) and down(DN) pulses.
Figure 2. Conception of the feed-forward
PLL.
The PFD detects the difference in phase
and frequency between the reference clock
and feedback clock inputs and generates
an “up” or “down” control signal based on
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International Journal of Engineering Trends and Technology (IJETT) – Volume 5 Number 7- Nov 2013
whether the feedback frequency is lagging
equal to (M) times the input reference
or leading the reference frequency. These
clock (FREF). The PFD input reference
“up” or “down” control signals determine
clock (FREF) is equal to the input clock
whether the VCO needs to operate at a
(FIN) divided by the pre-scale counter (N).
higher or lower frequency, respectively.
Therefore, the feedback clock (FFB)
The PFD outputs these “up” and “down”
applied to one input of the PFD is locked
signals to a charge pump. If the charge
to the FREF that is applied to the other
pump receives an up signal, current is
input of the PFD. The VCO output feeds
driven into the loop filter. Conversely, if it
post-scale counters which allow a number
receives a down signal, current is drawn
of harmonically related frequencies to be
from the loop filter.
produced within the PLL.
The loop filter converts these signals to a
The output frequency of the PLL is equal
control voltage that is used to bias the
to the VCO frequency (FVCO) divided by
VCO. Based on the control voltage, the
the post-scale counter (C).
VCO oscillates at a higher or lower
In the form of equations:
frequency, which affects the phase and
•
FREF = FIN / N
frequency of the feedback clock. If the
•
FVCO = FREF × M = FIN × M/N
PFD produces an up signal, then the VCO
•
FOUT = FVCO / C = (FREF × M)
frequency
/ C = (FIN × M) / (N × C)
increases.
A
down signal
decreases the VCO frequency. The VCO
where:
stabilizes once the reference clock and the
•
FVCO = VCO frequency
feedback clock have the same phase and
•
FIN = input frequency
frequency. The loop filter filters out jitter
•
FREF = reference frequency
by removing glitches from the charge
•
FOUT = output frequency
pump and preventing voltage over-shoot.
•
M = counter (multiplier), part of
When the reference clock and the feedback
the clock feedback path
clock are aligned, the PLL is considered
•
locked. To find reasons why a PLL may
input clock reference path
lose lock, see Why Does My PLL Lose
•
Lock?
PROPOSED FEED-FORWARD
A divide counter (M) is inserted in the
COMPENSATION ALGORITHM:
feedback loop to increase the VCO
The proposed feed-forward all-digital PLL
frequency above
the input reference
system is shown in Fig. 3. The input
frequency. VCO frequency (FVCO) is
reference can be either a frequency control
ISSN: 2231-5381
N = counter (divider), part of the
C = post-scale counter (divider)
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International Journal of Engineering Trends and Technology (IJETT) – Volume 5 Number 7- Nov 2013
word (FCW) as in [5], or the output of a
function (FF function in Fig.3) is a
frequency to digital converter (FDC) or
mathematical operator as will be shown
time to digital converter (TDC) similar to
later. The digital controlled oscillator
the one in the feed-back path as proposed
(DCO) can be either a digitally controlled
in [5-6]. The phase-detector (PD) is just an
inverter chain ring oscillator or LC
adder, and the low pass filter (LPF) is a
oscillator.
digital low-pass filter. The feed-forward
Figure 3: LPF
.
Figure 4. ADPLL feed-forward model.
A linear model of the feed-forward
is ΚDCO/Κ^DCO, ffree is the free running
ADPLL is shown in Fig. 4 adapted to
estimating the DCO’s gain.
include the feed-forward path and scaling
factors from [5]. The input reference Δf/fR
is the time step unit value reference, N is
the ratio between the wanted frequency at
the output of the PLL and the reference
frequency fR. The function F(z) is the
digital low-pass transfer function while
K^DCO is the DCO gain scaling constant.
KDCO is the DCO gain constant, Κ’DCO
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International Journal of Engineering Trends and Technology (IJETT) – Volume 5 Number 7- Nov 2013
RESULTS:
REFERENCES:
[1] R. B. Staszewski, D. Leipold, K.
Muhammand, and P. T. Balsara, “Digitally
controlled
oscillator
(DCO)-based
architecture for RF frequency synthesis in
a deep-submicrometer CMOS process,”
IEEE Trans. Circuits Syst. II, Analog
Digit. Signal Process., vol. 50, no. 11, pp.
815–822, Nov. 2003.
[2] J. Lin, B. Haroun, T. Foo, J.-S. Wang,
APPLICAIONS:
ADPLL is used as Counter-Based Mode
Switching Controller for multi purpose
counting and storage applications. This
can be used in all type of communications
Barr, and J. Kirkpartick, “A PVT tolerant
0.18 MHz to 600 MHz self-calibrated
digital PLL in 90 nm CMOS process,” in
Dig. Tech. Papers ISSCC’04, Feb. 2004,
like OFDM, CDMA Etc.
Scientific CRO s is mainly constructed
with ADPLLs. ADPLL in these C.R.O.s
are used to generate all type of different
voltage signals and current signals.
pp. 488–489.
[3] P. Raha, S. Randall, R. Jennings, B.
Helmick, A. Amerasekera, and B. Haroun,
“A robust digital delay line architecture in
a 0.13-m CMOS technology node for
CONCLUSION:
A fast locking ADPLL is proposed in this
paper is used to reduce the locking time of
ASPLL. A feed-forward compensation
algorithm; proposed in this ADPLL is used
to generate all signals with less execution
time. Furthermore, the frequency divider is
fully reused. The predicted error due to the
estimation errors and the stabilities of the
proposed ADPLL during the frequency
acquisition mode and phase acquisition
mode are designed.
B. Helmick, S. Randall, T. Mayhugh, C.
reduced design and process sensitivities,”
in Proc. ISQED’02, Mar. 2002, pp. 148–
153.
[4] T. Olsson and P. Nilsson, “Portable
digital clock generator for digital signal
processing applications,” Electron. Lett.,
vol. 39, pp. 1372–1374, Sep. 2003.
[5] E. Roth, M. Thalmann, N. Felber, and
W. Fichtner, “A delay-line based DCO for
multimedia
applications
using
digital
standard cells only,” in Dig. Tech. Papers
ISSCC’03, Feb. 2003, pp. 432–433.
[6] C.-C. Chung and C.-Y. Lee, “An all
digital phase-locked loop for highspeed
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International Journal of Engineering Trends and Technology (IJETT) – Volume 5 Number 7- Nov 2013
clock generation,” IEEE J. Solid-State
Circuits, vol. 38, no. 2, pp. 347–351, Feb.
2003.
[7] J. M. Rabaey, Digital Integrated
Circuits—A
Design
Perspectives.
Englewood Cliffs, NJ: Prentice-Hall, 1996.
[8] I. Hwang, S. Lee, S. Lee, and S. Kim,
“A digitally controlled phaselocked loop
with fast locking scheme for clock
synthesis application,” ISSCC Dig. Tech.
Papers, pp. 168–169, Feb. 2000.
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