Dual, Ultralow Noise
Variable Gain Amplifier
AD604
FEATURES
FUNCTIONAL BLOCK DIAGRAM
PAOx FBKx
–DSXx
+DSXx
VGNx
GAIN CONTROL
AND SCALING
AD604
0dB TO –48.4dB
DIFFERENTIAL
PASSIVE INPUT
ATTENUATOR
PAIx
40Ω
AFA
R-1.5R
LADDER
NETWORK
VREF
OUTx
VOCM
FIXED GAIN
AMPLIFIER
34.4dB
32Ω
8Ω
00540-001
Ultralow input noise at maximum gain
0.80 nV/√Hz, 3.0 pA/√Hz
2 independent linear-in-dB channels
Absolute gain range per channel programmable
0 dB to 48 dB (preamplifier gain = 14 dB) through 6 dB to
54 dB (preamplifier gain = 20 dB)
±1.0 dB gain accuracy
Bandwidth: 40 MHz (−3 dB)
Input resistance: 300 kΩ
Variable gain scaling: 20 dB/V through 40 dB/V
Stable gain with temperature and supply variations
Single-ended unipolar gain control
Power shutdown at lower end of gain control
Drive ADCs directly
COMx
Figure 1.
APPLICATIONS
Ultrasound and sonar time-gain controls
High performance AGC systems
Signal measurement
GENERAL DESCRIPTION
The AD604 is an ultralow noise, very accurate, dual-channel,
linear-in-dB variable gain amplifier (VGA) optimized for timebased variable gain control in ultrasound applications; however,
it supports any application requiring low noise, wide bandwidth,
variable gain control. Each channel of the AD604 provides a
300 kΩ input resistance and unipolar gain control for ease of
use. User-determined gain ranges, gain scaling (dB/V), and dc
level shifting of output further optimize performance.
Each channel of the AD604 uses a high performance
preamplifier that provides an input-referred noise voltage of
0.8 nV/√Hz. The very accurate linear-in-dB response of the
AD604 is achieved with the differential input exponential
amplifier (DSX-AMP) architecture. Each DSX-AMP comprises
a variable attenuator of 0 dB to 48.36 dB followed by a high
speed fixed-gain amplifier. The attenuator is a 7-stage
R-1.5R ladder network. The attenuation between tap points is
6.908 dB and 48.36 dB for the ladder network.
The equation for the linear-in-dB gain response is
G (dB) =
(Gain Scaling (dB/V) × VGN (V)) + (Preamp Gain (dB) – 19 dB)
Preamplifier gains between 5 and 10 (14 dB and 20 dB) provide
overall gain ranges per channel of 0 dB through 48 dB and 6 dB
through 54 dB. The two channels of the AD604 can be cascaded
to provide greater levels of gain range by bypassing the preamplifier
of the second channel. However, in multiple channel systems,
cascading the AD604 with other devices in the AD60x VGA
family that do not include a preamplifier may provide a more
efficient solution. The AD604 provides access to the output of
the preamplifier, allowing for external filtering between the
preamplifier and the differential attenuator stage.
Note that scale factors up to 40 dB/V are achievable with reduced
accuracy for scales above 30 dB/V. The gain scales linearly in
decibels with control voltages of 0.4 V to 2.4 V with the 20 dB/V
scale. Below and above this gain control range, the gain begins
to deviate from the ideal linear-in-dB control law. The gain
control region below 0.1 V is not used for gain control. When
the gain control voltage is <50 mV, the amplifier channel is
powered down to 1.9 mA.
The AD604 is available in 24-lead SSOP, SOIC, and PDIP
packages and is guaranteed for operation over the −40°C to
+85°C temperature range.
Rev. G
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.461.3113 ©1996–2010 Analog Devices, Inc. All rights reserved.
AD604
TABLE OF CONTENTS
Features .............................................................................................. 1
Applications Information .............................................................. 18
Applications ....................................................................................... 1
Ultralow Noise AGC Amplifier with 82 dB to 96 dB Gain
Range............................................................................................ 19
Functional Block Diagram .............................................................. 1
General Description ......................................................................... 1
Revision History ............................................................................... 2
Ultralow Noise, Differential Input-Differential Output VGA
....................................................................................................... 21
Specifications..................................................................................... 3
Medical Ultrasound TGC Driving the AD9050, a 10-Bit, 40
MSPS ADC .................................................................................. 22
Absolute Maximum Ratings............................................................ 5
Evaluation Board ............................................................................ 24
ESD Caution .................................................................................. 5
Connecting a Waveform to the AD604-EVALZ ........................ 24
Pin Configuration and Function Descriptions ............................. 6
DSX Input Connections ............................................................ 24
Typical Performance Characteristics ............................................. 7
Preamplifier Gain ....................................................................... 25
Theory of Operation ...................................................................... 13
Outputs ........................................................................................ 25
Preamplifier ................................................................................. 14
DC Operating Conditions......................................................... 25
Differential Ladder (Attenuator) .............................................. 15
Evaluation Board Artwork and Schematic ............................. 26
AC Coupling ............................................................................... 16
Outline Dimensions ....................................................................... 28
Gain Control Interface ............................................................... 16
Ordering Guide .......................................................................... 29
Active Feedback Amplifier (Fixed-Gain Amp) ...................... 16
REVISION HISTORY
12/10—Rev. F to Rev. G
Changes to Figure 1 .......................................................................... 1
Changes to Evaluation Board Section, Figure 55, Using the
Preamplifier Section, Figure 56, and DSX Input Connections
Section .............................................................................................. 24
Changes to Preamplifier Gain Section, Outputs Section, DC
Operating Conditions Section, Table 4 and Table 5................... 25
Added Figure 57; Renumbered Sequentially .............................. 25
Changes to Figure 58 to Figure 61 ................................................ 26
Added Figure 62.............................................................................. 26
Changes to Figure 63 ...................................................................... 27
Updated Outline Dimensions ....................................................... 28
4/10—Rev. E to Rev. F
Changes to Figure 55, DSX Input Connections Section, and
Differential DSX Inputs Section ................................................... 24
Changes to Figure 61, Deleted Table 6 ......................................... 27
Changes to Ordering Guide .......................................................... 29
10/08—Rev. D to Rev. E
Changes to Figure 1 .......................................................................... 1
Changes to Figure 37 ...................................................................... 13
Changes to Figure 41 ...................................................................... 15
Changes to Evaluation Board Model Name ................................ 24
Changes to Ordering Guide .......................................................... 29
1/08—Rev. C to Rev. D
Changes to AC Coupling Section ................................................. 16
Changes to Applications Information Section............................ 18
Changes to An Ultralow Noise AGC Amplifier with 82 dB to
96 dB Gain Range Section ............................................................. 19
Changes to Figure 55 and Figure 56............................................. 24
Changes to Cascaded DSX Section and Outputs Section ......... 25
Changes to Figure 57 to Figure 60................................................ 26
Changes to Figure 61 and Table 6................................................. 27
Changes to Ordering Guide .......................................................... 29
3/07—Rev. B to Rev. C
Added Evaluation Board Section ................................................. 24
Added Evaluation Board Artwork and Schematics Section ..... 26
Changes to Ordering Guide .......................................................... 29
12/06—Rev. A to Rev. B
Changes to General Description .....................................................1
Changes to Figure 54...................................................................... 23
Changes to Ordering Guide .......................................................... 25
1/04—Rev. 0 to Rev. A
Changes to Specifications .................................................................2
Changes to Absolute Maximum Ratings ........................................3
Changes to Ordering Guide .............................................................3
Changes to Figure 1 Caption............................................................5
Changes to Figure 11 Caption .........................................................6
Changes to Figure 17.........................................................................6
Changes to Figure 51...................................................................... 17
Updated Outline Dimensions ....................................................... 18
10/96—Revision 0: Initial Version
Rev. G | Page 2 of 32
AD604
SPECIFICATIONS
Each amplifier channel at TA = 25°C, VS = ±5 V, RS = 50 Ω, RL = 500 Ω, CL = 5 pF, VREF = 2.50 V (scaling = 20 dB/V), 0 dB to 48 dB gain
range (preamplifier gain = 14 dB), VOCM = 2.5 V, C1 and C2 = 0.1 μF (see Figure 37), unless otherwise noted.
Table 1.
Parameter
INPUT CHARACTERISTICS
Preamplifier
Input Resistance
Input Capacitance
Input Bias Current
Peak Input Voltage
Input Voltage Noise
Input Current Noise
Noise Figure
DSX
Input Resistance
Input Capacitance
Peak Input Voltage
Input Voltage Noise
Input Current Noise
Noise Figure
Common-Mode Rejection Ratio
OUTPUT CHARACTERISTICS
−3 dB Bandwidth
Slew Rate
Output Signal Range
Output Impedance
Output Short-Circuit Current
Harmonic Distortion
HD2
HD3
HD2
HD3
Two-Tone Intermodulation Distortion (IMD)
Third-Order Intercept
1 dB Compression Point
Channel-to-Channel Crosstalk
Group Delay Variation
VOCM Input Resistance
Conditions
Min
Typ
Max
Unit
Preamplifier gain = 14 dB
Preamplifier gain = 20 dB
VGN = 2.9 V, RS = 0 Ω
Preamplifier gain = 14 dB
Preamplifier gain = 20 dB
Independent of gain
RS = 50 Ω, f = 10 MHz, VGN = 2.9 V
RS = 200 Ω, f = 10 MHz, VGN = 2.9 V
300
8.5
−27
±400
±200
kΩ
pF
mA
mV
mV
0.8
0.73
3.0
2.3
1.1
nV/√Hz
nV/√Hz
pA/√Hz
dB
dB
VGN = 2.9 V
VGN = 2.9 V
RS = 50 Ω, f = 10 MHz, VGN = 2.9 V
RS = 200 Ω, f = 10 MHz, VGN = 2.9 V
f = 1 MHz, VGN = 2.65 V
175
3.0
2.5 ± 2
1.8
2.7
8.4
12
−20
Ω
pF
V
nV/√Hz
pA/√Hz
dB
dB
dB
40
170
2.5 ± 1.5
2
±40
MHz
V/μs
V
Ω
mA
−54
−67
−43
−48
dBc
dBc
dBc
dBc
−74
−71
−12.5
dBc
dBc
dBm
15
−30
dBm
dB
±2
45
ns
kΩ
Constant with gain
VGN = 1.5 V, output = 1 V step
RL ≥ 500 Ω
f = 10 MHz
VGN = 1 V, VOUT = 1 V p-p
f = 1 MHz
f = 1 MHz
f = 10 MHz
f = 10 MHz
VGN = 2.9 V, VOUT = 1 V p-p
f = 1 MHz
f = 10 MHz
f = 10 MHz, VGN = 2.65 V, VOUT = 1 V p-p,
input referred
f = 1 MHz, VGN = 2.9 V, output referred
VOUT = 1 V p-p, f = 1 MHz,
Channel 1: VGN = 2.65 V, inputs shorted,
Channel 2: VGN = 1.5 V (mid gain)
1 MHz < f < 10 MHz, full gain range
Rev. G | Page 3 of 32
AD604
Parameter
ACCURACY
Absolute Gain Error
0 dB to 3 dB
3 dB to 43 dB
43 dB to 48 dB
Gain Scaling Error
Output Offset Voltage
Output Offset Variation
GAIN CONTROL INTERFACE
Gain Scaling Factor
Gain Range
Input Voltage (VGN) Range
Input Bias Current
Input Resistance
Response Time
VREF Input Resistance
POWER SUPPLY
Specified Operating Range
Power Dissipation
Quiescent Supply Current
Powered Down
Power-Up Response Time
Power-Down Response Time
Conditions
Min
Typ
Max
Unit
0.25 V < VGN < 0.400 V
0.400 V < VGN < 2.400 V
2.400 V < VGN < 2.65 V
0.400 V < VGN < 2.400 V
VREF = 2.500 V, VOCM = 2.500 V
VREF = 2.500 V, VOCM = 2.500 V
−1.2
−1.0
−3.5
+0.75
±0.3
−1.25
±0.25
±30
30
+3
+1.0
+1.2
dB
dB
dB
dB/V
mV
mV
VREF = 2.5 V, 0.4 V < VGN < 2.4 V
VREF = 1.67 V
Preamplifier gain = 14 dB
Preamplifier gain = 20 dB
20 dB/V, VREF = 2.5 V
−50
19
48 dB gain change
One complete channel
One DSX only
One complete channel
One DSX only
VPOS, one complete channel
VPOS, one DSX only
VNEG, one preamplifier only
VPOS, VGN < 50 mV, one channel
VNEG, VGN < 50 mV, one channel
48 dB gain change, VOUT = 2 V p-p
Rev. G | Page 4 of 32
−15
20
30
0 to 48
6 to 54
0.1 to 2.9
−0.4
2
0.2
10
±5
5
220
95
32
19
−12
1.9
−150
0.6
0.4
+50
50
21
36
23
3.0
dB/V
dB/V
dB
dB
V
μA
MΩ
μs
kΩ
V
V
mW
mW
mA
mA
mA
mA
μA
μs
μs
AD604
ABSOLUTE MAXIMUM RATINGS
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
Table 2.
1, 2
Parameter
Supply Voltage ±VS
Pin 17 to Pin 20 (with Pin 16, Pin 22 = 0 V)
Input Voltages
Pin 1, Pin 2, Pin 11, Pin 12
Pin 4, Pin 9
Pin 5, Pin 8
Pin 6, Pin 7, Pin 13, Pin 14, Pin 23, Pin 24
Internal Power Dissipation
PDIP (N)
SOIC (RW)
SSOP (RS)
Operating Temperature Range
Storage Temperature Range
Lead Temperature, Soldering 60 sec
θJA 3
AD604AN
AD604AR
AD604ARS
θJC3
AD604AN
AD604AR
AD604ARS
Rating
±6.5 V
VPOS/2 ± 2 V
continuous
±2 V
VPOS, VNEG
VPOS, 0 V
ESD CAUTION
2.2 W
1.7 W
1.1 W
−40°C to +85°C
−65°C to +150°C
300°C
105°C/W
73°C/W
112°C/W
35°C/W
38°C/W
34°C/W
1
Pin 1, Pin 2, Pin 11 to Pin 14, Pin 23, and Pin 24 are part of a single-supply
circuit. The part is likely to suffer damage if any of these pins are accidentally
connected to VN.
2
When driven from an external low impedance source.
3
Using MIL-STD-883 test method G43-87 with a 1S (2-layer) test board.
Rev. G | Page 5 of 32
AD604
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
–DSX1 1
24 VGN1
+DSX1 2
23 VREF
PAO1 3
22 OUT1
PAI1 5
COM1 6
21 GND1
AD604
20 VPOS
PAI2 8
19 VNEG
TOP VIEW
(Not to Scale) 18 VNEG
17 VPOS
FBK2 9
16 GND2
PAO2 10
15 OUT2
+DSX2 11
14 VOCM
–DSX2 12
13 VGN2
COM2 7
00540-002
FBK1 4
Figure 2. Pin Configuration
Table 3. Pin Function Descriptions
Pin No.
1
2
3
4
5
6
7
8
9
10
11
12
13
Mnemonic
–DSX1
+DSX1
PAO1
FBK1
PAI1
COM1
COM2
PAI2
FBK2
PAO2
+DSX2
–DSX2
VGN2
14
15
16
17
18
19
20
21
22
23
24
VOCM
OUT2
GND2
VPOS
VNEG
VNEG
VPOS
GND1
OUT1
VREF
VGN1
Description
Channel 1 Negative Signal Input to DSX1.
Channel 1 Positive Signal Input to DSX1.
Channel 1 Preamplifier Output.
Channel 1 Preamplifier Feedback Pin.
Channel 1 Preamplifier Positive Input.
Channel 1 Signal Ground. When this pin is connected to positive supply, Preamplifier 1 shuts down.
Channel 2 Signal Ground. When this pin is connected to positive supply, Preamplifier 2 shuts down.
Channel 2 Preamplifier Positive Input.
Channel 2 Preamplifier Feedback Pin.
Channel 2 Preamplifier Output.
Channel 2 Positive Signal Input to DSX2.
Channel 2 Negative Signal Input to DSX2.
Channel 2 Gain Control Input and Power-Down Pin. If this pin is grounded, the device is off; otherwise, positive
voltage increases gain.
Input to this pin defines the common mode of the output at OUT1 and OUT2.
Channel 2 Signal Output.
Ground.
Positive Supply.
Negative Supply.
Negative Supply.
Positive Supply.
Ground.
Channel 1 Signal Output.
Input to this pin sets gain scaling for both channels to 2.5 V = 20 dB/V and 1.67 V = 30 dB/V.
Channel 1 Gain Control Input and Power-Down Pin. If this pin is grounded, the device is off; otherwise, positive
voltage increases gain.
Rev. G | Page 6 of 32
AD604
TYPICAL PERFORMANCE CHARACTERISTICS
Unless otherwise noted, G (preamplifier) = 14 dB, VREF = 2.5 V (20 dB/V scaling), f = 1 MHz, RL = 500 Ω, CL = 5 pF, TA = 25°C, and
VSS = ±5 V.
40.0
50
37.5
40
35.0
GAIN SCALING (dB/V)
30
GAIN (dB)
THEORETICAL
3 CURVES
–40°C,
+25°C,
+85°C
20
10
32.5
ACTUAL
30.0
27.5
25.0
0
0.5
0.9
1.3
1.7
2.1
2.5
20.0
1.25
2.9
00540-006
00540-003
–10
0.1
22.5
1.50
1.75
VGN (V)
Figure 3. Gain vs. VGN for Three Temperatures
2.50
2.0
G (PREAMP) = +14dB
(0dB TO +48dB)
50
1.5
1.0
GAIN ERROR (dB)
40
G (PREAMP) = +20dB
(+6dB TO +54dB)
20
10
DSX ONLY
(–14dB TO +34dB)
0
0.9
1.3
1.7
2.1
–0.5
+85°C
–1.5
00540-004
0.5
+25°C
–40°C
0
–1.0
–10
–20
0.1
0.5
2.5
–2.0
0.2
2.9
00540-007
30
GAIN (dB)
2.25
Figure 6. Gain Scaling vs. VREF
60
0.7
1.2
1.7
2.2
2.7
VGN (V)
VGN (V)
Figure 7. Gain Error vs. VGN
Figure 4. Gain vs. VGN for Different Preamplifier Gains
2.0
50
ACTUAL
40
1.5
ACTUAL
30dB/V
VREF = 1.67V
1.0
GAIN ERROR (dB)
30
20
20dB/V
VREF = 2.5V
10
0.5
FREQ = 1MHz
0
–0.5
FREQ = 5MHz
FREQ = 10MHz
–1.0
0
0.5
0.9
1.3
1.7
2.1
2.5
–2.0
0.2
2.9
00540-008
–10
0.1
–1.5
00540-005
GAIN (dB)
2.00
VREF (V)
0.7
1.2
1.7
2.2
VGN (V)
VGN (V)
Figure 8. Gain Error vs. VGN at Different Frequencies
Figure 5. Gain vs. VGN for Different Gain Scalings
Rev. G | Page 7 of 32
2.7
AD604
50
2.0
VGN = 2.5V
40
1.5
VGN = 2.9V
30
20dB/V
VREF = 2.5V
0.5
GAIN (dB)
0
–0.5
30dB/V
VREF = 1.67V
–1.0
20
VGN = 1.5V
10
VGN = 0.5V
0
VGN = 0.1V
–10
–20
–30
00540-009
–1.5
–2.0
0.2
0.7
1.2
1.7
2.2
VGN = 0V
00540-012
GAIN ERROR (dB)
1.0
–40
–50
100k
2.7
1M
VGN (V)
10M
100M
FREQUENCY (Hz)
Figure 9. Gain Error vs. VGN for Two Gain Scaling Values
25
Figure 12. AC Response for Various Values of VGN
2.55
N = 50
VGN1 = 1.0V
VGN2 = 1.0V
ΔG(dB) =
G(CH1) – G(CH2)
20
VOCM = 2.5V
2.54
–40°C
2.53
VOUT (V)
PERCENTAGE
2.52
15
10
2.51
2.50
+25°C
2.49
2.48
5
–0.8
–0.6
–0.4
–0.2
0.1
0.3
0.5
0.7
2.46
2.45
0.2
0.9
0.7
1.2
DELTA GAIN (dB)
Figure 10. Gain Match; VGN1 = VGN2 = 1.0 V
25
NOISE (nV/ Hz)
5
170
150
+85°C
130
+25°C
110
00540-011
PERCENTAGE
190
10
–1.0
–0.8
–0.6
–0.4
–0.2
0.1
0.3
2.7
210
15
0
2.2
Figure 13. Output Offset vs. VGN for Three Temperatures
N = 50
VGN1 = 2.50V
VGN2 = 2.50V
ΔG(dB) =
G(CH1) – G(CH2)
20
1.7
VGN (V)
0.5
0.7
90
0.1
0.9
DELTA GAIN (dB)
–40°C
0.5
0.9
1.3
1.7
2.1
00540-014
–1.0
+85°C
00540-013
00540-010
0
2.47
2.5
2.9
VGN (V)
Figure 11. Gain Match; VGN1 = VGN2 = 2.50 V
Figure 14. Output Referred Noise vs. VGN for Three Temperatures
Rev. G | Page 8 of 32
AD604
10
1000
VGN = 2.9V
NOISE (nV/ Hz)
NOISE (nV/ Hz)
100
10
1
RSOURCE ALONE
0.1
0.1
0.5
0.9
1.3
1.7
2.1
2.5
0.1
2.9
00540-018
00540-015
1
1
10
VGN (V)
Figure 15. Input Referred Noise vs. VGN
900
100
1k
RSOURCE (Ω)
Figure 18. Input Referred Noise vs. RSOURCE
16
VGN = 2.9V
VGN = 2.9V
15
14
850
13
NOISE FIGURE (dB)
NOISE (pV/ Hz)
12
800
750
700
11
10
9
8
7
6
5
4
650
600
–40
–20
0
20
40
60
80
00540-019
00540-016
3
2
1
90
1
1k
10k
RSOURCE (Ω)
Figure 16. Input Referred Noise vs. Temperature
770
100
10
TEMPERATURE (°C)
Figure 19. Noise Figure vs. RSOURCE
40
VGN = 2.9V
RS = 240Ω
35
765
NOISE FIGURE (dB)
755
750
25
20
15
10
745
1M
0
10M
FREQUENCY (Hz)
00540-020
740
100k
5
00540-017
NOISE (pV/ Hz)
30
760
0
0.4
0.8
1.2
1.6
2.0
VGN (V)
Figure 17. Input Referred Noise vs. Frequency
Figure 20. Noise Figure vs. VGN
Rev. G | Page 9 of 32
2.4
2.8
AD604
–40
–20
VO = 1V p-p
VGN = 1V
–45
–40
–50
–50
POUT (dBm)
HD2
–55
HD3
–60
–60
–70
–80
–90
–100
00540-021
–65
–70
100k
1M
10M
00540-024
HARMONIC DISTORTION (dBc)
VO = 1V p-p
VGN = 1V
–30
–110
–120
100M
9.96
9.98
0
–40
HD2 (10MHz)
–5
–45
–10
–55
PIN (dBm)
–50
HD3 (10MHz)
–60
INPUT
SIGNAL
LIMIT
800mV p-p
10MHz
–15
–20
1MHz
–65
–25
–70
HD2 (1MHz)
–80
0.5
0.9
1.3
1.7
2.1
2.5
–35
0.1
2.9
00540-025
HD3 (1MHz)
–75
–30
00540-022
HARMONIC DISTORTION (dBc)
10.04
5
VO = 1V p-p
–35
0.5
0.9
1.3
VGN (V)
–20
RS
25
2.5
2.9
VO = 1V p-p
20
500Ω
15
HD2 (10MHz)
–40
f = 1MHz
IP3 (dBm)
10
HD3 (10MHz)
HD2 (1MHz)
–60
HD3 (1MHz)
f = 10MHz
–10
00540-023
50
0
–5
–70
0
5
100
150
200
–15
0.4
250
RSOURCE (Ω)
00540-026
–50
–80
2.1
Figure 25. 1 dB Compression vs. VGN
VO = 1V p-p
VGN = 1V
DUT
50Ω
–30
1.7
VGN (V)
Figure 22. Harmonic Distortion vs. VGN
HARMONIC DISTORTION (dBc)
10.02
Figure 24. Intermodulation Distortion
Figure 21. Harmonic Distortion vs. Frequency
–30
10.00
FREQUENCY (MHz)
FREQUENCY (Hz)
0.9
1.4
1.9
2.4
VGN (V)
Figure 26. Third-Order Intercept vs. VGN
Figure 23. Harmonic Distortion vs. RSOURCE
Rev. G | Page 10 of 32
2.9
AD604
2V
VO = 2V p-p
VGN = 1.5V
500mV
2.9V 100
VGN (V)
400mV/DIV
90
10
–2V
253ns
500mV
00540-030
0%
00540-027
0.1V
100ns
1.253µs
100ns/DIV
Figure 30. Gain Response
Figure 27. Large Signal Pulse Response
0
200
VO = 200mV p-p
VGN = 1.5V
–10
VGN1 = 1V
VOUT1 = 1V p-p
VIN2 = GND
VGN2 = 2.9V
–30
–40
VGN2 = 2V
–50
TRIG'D
–60
00540-028
–200
253ns
–70
100k
1.253µs
100ns/DIV
VGN2 = 1.5V
VGN2 = 0.1V
1M
10M
00540-031
40mV/DIV
CROSSTALK (dB)
–20
100M
FREQUENCY (Hz)
Figure 31. Crosstalk (Channel 1 to Channel 2) vs. Frequency
Figure 28. Small Signal Pulse Response
0
500mV
–10
2.9V 100
VGN = 2.9V
90
VGN (V)
CMRR (dB)
–20
–30
VGN = 2.5V
VGN = 2V
–40
10
0%
200ns
–50
00540-029
500mV
–60
100k
VGN = 0.1V
1M
00540-032
0V
10M
100M
FREQUENCY (Hz)
Figure 32. DSX Common-Mode Rejection Ratio vs. Frequency
Figure 29. Power-Up/Power-Down Response
Rev. G | Page 11 of 32
AD604
40
35
SUPPLY CURRENT (mA)
10k
1k
100
10
10k
100k
1M
10M
15
10
PREAMP (±IS)
+IS (VGN = 0)
–20
0
20
40
60
80
90
TEMPERATURE (°C)
FREQUENCY (Hz)
Figure 33. Input Impedance vs. Frequency
Figure 35. Supply Current (One Channel) vs. Temperature
27.6
20
27.4
18
27.2
16
DELAY (ns)
27.0
26.8
26.6
14
VGN = 0.1V
12
26.4
10
26.2
VGN = 2.9V
26.0
25.8
–40
8
00540-034
INPUT BIAS CURRENT (µA)
DSX (+IS)
20
0
–40
100M
AD604 (+I S)
25
5
00540-033
1
1k
30
–20
0
20
40
60
80
6
100k
90
TEMPERATURE (°C)
00540-036
INPUT IMPEDANCE (Ω)
100k
+IS (AD604) = +I S (PA) + +IS (DSX)
–IS (AD604) = –I S (PA)
00540-035
1M
1M
10M
FREQUENCY (Hz)
Figure 34. Input Bias Current vs. Temperature
Figure 36. Group Delay vs. Frequency
Rev. G | Page 12 of 32
100M
AD604
THEORY OF OPERATION
example, if the preamp gain is set to 14 dB and VREF is set to
2.50 V (to establish a gain scaling of 20 dB/V), the gain equation
simplifies to
The AD604 is a dual-channel VGA with an ultralow noise
preamplifier. Figure 37 shows the simplified block diagram of
one channel. Each identical channel consists of a preamplifier
with gain setting resistors (R5, R6, and R7) and a single-supply
X-AMP® (hereafter called DSX, differential single-supply X-AMP)
made up of the following:
•
A precision passive attenuator (differential ladder).
•
A gain control block.
•
A VOCM buffer with supply splitting resistors
(R3 and R4).
•
G (dB) = 20 (dB/V) × VGN (V) – 5 dB
The desired gain can then be achieved by setting the unipolar
gain control (VGN) to a voltage within its nominal operating
range of 0.25 V to 2.65 V (for 20 dB/V gain scaling). The gain is
monotonic for a complete gain control voltage range of 0.1 V to
2.9 V. Maximum gain can be achieved at a VGN of 2.9 V.
The inputs VREF and VOCM are common to both channels.
They are decoupled to ground, minimizing interchannel
crosstalk. For the highest gain scaling accuracy, VREF should
have an external low impedance voltage source. For low accuracy
20 dB/V applications, the VREF input can be decoupled with a
capacitor to ground. In this mode, the gain scaling is determined
by the midpoint between VPOS and GND; therefore, care
should be taken to control the supply voltage to 5 V. The input
resistance looking into the VREF pin is 10 kΩ ± 20%.
An active feedback amplifier (AFA) with gain setting
resistors (R1 and R2). To understand the active-feedback
amplifier topology, refer to the AD830 data sheet. The
AD830 is a practical implementation of the idea.
The preamplifier is powered by a ±5 V supply, while the DSX
uses a single +5 V supply. The linear-in-dB gain response of the
AD604 can generally be described by
G (dB) = Gain Scaling (dB/V) × Gain Control (V) +
(Preamp Gain (dB) − 19 dB)
The DSX portion of the AD604 is a single-supply circuit, and
the VOCM pin is used to establish the dc level of the midpoint
of this portion of the circuit. The VOCM pin only needs an
external decoupling capacitor to ground to center the midpoint
between the supply voltages (5 V, GND); however, the VOCM
can be adjusted to other voltage levels if the dc common-mode
level of the output is important to the user (for example, see the
section entitled Medical Ultrasound TGC Driving the AD9050,
a 10-Bit, 40 MSPS ADC). The input resistance looking into the
VOCM pin is 45 kΩ ± 20%.
(1)
Each channel provides between 0 dB to 48.4 dB and 6 dB to 54.4
dB of gain, depending on the user-determined preamplifier
gain. The center 40 dB of gain is exactly linear-in-dB while the
gain error increases at the top and bottom of the range. The gain
of the preamplifier is typically either 14 dB or 20 dB but can be
set to intermediate values by a single external resistor (see the
Preamplifier section for details). The gain of the DSX can vary
from −14 dB to +34.4 dB, as determined by the gain control
voltage (VGN). The VREF input establishes the gain scaling;
the useful gain scaling range is between 20 dB/V and 40 dB/V
for a VREF voltage of 2.5 V and 1.25 V, respectively. For
VREF
VGNx
GAIN
CONTROL
PAOx C1
PAIx
R7
40Ω
R5
32Ω
+DSXx
175Ω
DISTRIBUTED GM
EXT.
FBKx
C2
DIFFERENTIAL
ATTENUATOR
–DSXx
G1
Ao
175Ω
VPOS
R6
8Ω
G2
R3
200kΩ COMx
R2
20Ω
VOCM
EXT.
R4
200kΩ
R1
820Ω
00540-037
C3
OUTx
Figure 37. Simplified Block Diagram of a Single Channel of the AD604
Rev. G | Page 13 of 32
AD604
PREAMPLIFIER
The input capability of the following single-supply DSX (2.5 ± 2 V
for a +5 V supply) limits the maximum input voltage of the
preamplifier to ±400 mV for the 14 dB gain configuration or
±200 mV for the 20 dB gain configuration.
The preamplifier gain can be programmed to 14 dB or 20 dB by
either shorting the FBK1 node to PAO1 (14 dB) or by leaving
the FBK1 node open (20 dB). These two gain settings are very
accurate because they are set by the ratio of the on-chip resistors.
Any intermediate gain can be achieved by connecting the
appropriate resistor value between PAO1 and FBK1 according
to Equation 2 and Equation 3.
(R7 || REXT ) + R5 + R6
V
G = OUT =
VIN
R6
To achieve optimum specifications, power and ground management are critical to the AD604. Large dynamic currents result
because of the low resistances needed for the desired noise
performance. Most of the difficulty is with the very low gain
setting resistors of the preamplifier that allow for a total input
referred noise, including the DSX, as low as 0.8 nV/√Hz. The
consequently large dynamic currents have to be carefully
handled to maintain performance even at large signal levels.
20
(2)
(3)
Because the internal resistors have an absolute tolerance of ±20%,
the gain can be in error by as much as 0.33 dB when REXT is 30 Ω,
where it is assumed that REXT is exact.
Figure 38 shows how the preamplifier is set to gains of 14 dB,
17.5 dB, and 20 dB. The gain range of a single channel of the
AD604 is 0 dB to 48 dB when the preamplifier is set to 14 dB
(Figure 38a), 3.5 dB to 51.5 dB for a preamp gain of 17.5 dB
(Figure 38b), and 6 dB to 54 dB for the highest preamp gain of
20 dB (Figure 38c).
PAI1
PAO1
R5
32Ω
R7
40Ω
FBK1
a. PREAMP GAIN = 14dB
PAI1
COM1
PAO1
R6
8Ω
R5
32Ω
R7
40Ω
R10
40Ω
FBK1
b. PREAMP GAIN = 17.5dB
PAO1
R5
32Ω
R7
40Ω
FBK1
c. PREAMP GAIN = 20dB
00540-038
R6
8Ω
15
SHORT
14
13
12
11
10
100k
VIN
IN
150Ω
50Ω
8Ω
32Ω
1M
40Ω
REXT
10M
FREQUENCY (Hz)
100M
Figure 39. AC Response for Preamplifier Gains of 14 dB, 17.5 dB, and 20 dB
The preamplifier uses a dual ±5 V supply to accommodate large
dynamic currents and a ground referenced input. The preamplifier
output is also ground referenced and requires a common-mode
level shift into the single-supply DSX. The two external coupling
capacitors (C1 and C2 in Figure 37) connected to the PAO1 and
+DSXx, and –DSXx, nodes and ground, respectively, perform
this function (see the AC Coupling section). In addition, they
eliminate any offset that would otherwise be introduced by the
preamplifier. It should be noted that an offset of 1 mV at the
input of the DSX is amplified by 34.4 dB (× 52.5) when the gain
control voltage is at its maximum; this equates to 52.5 mV at the
output. AC coupling is consequently required to keep the offset
from degrading the output signal range.
The gain-setting preamplifier feedback resistors are small
enough (8 Ω and 32 Ω) that even an additional 1 Ω in the
ground connection at Pin COM1 (the input common-mode
reference) seriously degrades gain accuracy and noise performance.
This node is sensitive, and careful attention is necessary to
minimize the ground impedance. All connections to the COM1
node should be as short as possible.
PAI1
COM1
16
00540-039
[R6 × G − (R5 + R6)] × R7
R6
8Ω
40Ω
18
17
R 7 − ( R6 × G ) + ( R5 + R 6 )
COM1
OPEN
19
GAIN (dB)
R EXT =
preamplifier to be 17.7 dB. The −3 dB small signal bandwidth of
one complete channel of the AD604 (preamplifier and DSX) is
40 MHz and is independent of gain.
Figure 38. Preamplifier Gain Programmability
For a preamplifier gain of 14 dB, the −3 dB small signal bandwidth
of the preamplifier is 130 MHz. When the gain is at its maximum
of 20 dB, the bandwidth is reduced by half to 65 MHz. Figure 39
shows the ac response for the three preamp gains shown in
Figure 38. Note that the gain for an REXT of 40 Ω should be
17.5 dB, but the mismatch between the internal resistors and
the external resistor causes the actual gain for this particular
The preamplifier, including the gain setting resistors, has a
noise performance of 0.71 nV/√Hz and 3 pA/√Hz. Note that a
significant portion of the total input referred voltage noise is
due to the feedback resistors. The equivalent noise resistance
presented by R5 and R6 in parallel is nominally 6.4 Ω, which
contributes 0.33 nV/√Hz to the total input referred voltage noise.
Rev. G | Page 14 of 32
AD604
The larger portion of the input referred voltage noise comes
from the amplifier with 0.63 nV/√Hz. The current noise is
independent of gain and depends only on the bias current in
the input stage of the preamplifier, which is 3 pA/√Hz.
A unique circuit technique is used to interpolate continuously
among the tap points, thereby providing continuous attenuation
from 0 dB to −48.36 dB. The ladder network, together with the
interpolation mechanism, can be considered a voltage-controlled
potentiometer.
The preamplifier can drive 40 Ω (the nominal feedback resistors)
and the following 175 Ω ladder load of the DSX with low
distortion. For example, at 10 MHz and 1 V at the output, the
preamplifier has less than −45 dB of second and third harmonic
distortion when driven from a low (25 Ω) source resistance.
In applications that require more than 48 dB of gain range, two
AD604 channels can be cascaded. Because the preamplifier has
a limited input signal range and consumes over half (120 mW)
of the total power (220 mW), and its ultralow noise is not necessary
after the first AD604 channel, a shutdown mechanism that
disables only the preamplifier is provided. To shut down the
preamplifier, connect the COM1 pin and/or COM2 pin to the
positive supply; the DSX is unaffected. For additional details,
refer to the Applications Information section.
–DSX1
VGN1 24
+DSX1
VREF 23
3
PAO1
OUT1 22
4
FBK1
GND1 21
5
PAI1
VPOS 20
6
COM1
VNEG 19
7
COM2
VNEG 18
8
PAI2
VPOS 17
9
FBK2
GND2 16
10 PAO2
OUT2 15
11 +DSX2
VOCM 14
12 –DSX2
VGN2 13
AD604
Figure 40. Shutdown of Preamplifiers Only
DIFFERENTIAL LADDER (ATTENUATOR)
The attenuator before the fixed-gain amplifier of the DSX is
realized by a differential 7-stage R-1.5R resistive ladder network
with an untrimmed input resistance of 175 Ω single-ended or
350 Ω differential. The signal applied at the input of the ladder
network is attenuated by 6.908 dB per tap; thus, the attenuation
at the first tap is 0 dB, at the second, 13.816 dB, and so on, all
the way to the last tap where the attenuation is 48.356 dB
(see Figure 41).
+DSXx
R
–6.908dB
R
1.5R
–13.82dB
R
1.5R
–20.72dB
What changes is the load seen by the driver; it is 175 Ω when
each input is driven single-ended but 350 Ω when driven
differentially. This is easily explained by thinking of the ladder
network as two 175 Ω resistors connected back-to-back with
the middle node, MID, being biased by the VOCM buffer. A
differential signal applied between the +DSXx and −DSXx
nodes results in zero current into the MID node, but a singleended signal applied to either input, +DSXx or –DSXx, while
the other input is ac-grounded causes the current delivered by
the source to flow into the VOCM buffer via the MID node.
The ladder resistor value of 175 Ω provides the optimum
balance between the load driving capability of the preamplifier
and the noise contribution of the resistors. An advantage of the
X-AMP architecture is that the output referred noise is constant
vs. gain over most of the gain range. Figure 41 shows that the
tap resistance is equal for all taps after only a few taps away
from the inputs. The resistance seen looking into each tap is
54.4 Ω, which makes 0.95 nV/√Hz of Johnson noise spectral
density. Because there are two attenuators, the overall noise
contribution of the ladder network is √2 times 0.95 nV/√Hz
or 1.34 nV/√Hz, a large fraction of the total DSX noise. The
balance of the DSX circuit components contributes another
1.2 nV/√Hz, which together with the attenuator produces
1.8 nV/√Hz of total DSX input referred noise.
00540-040
1
2
Because the DSX circuit uses a single voltage power supply, the
input biasing is provided by the VOCM buffer driving the MID
node (see Figure 41). Without internal biasing, the user would
have to dc bias the inputs externally. If not done carefully, the
biasing network can introduce additional noise and offsets. By
providing internal biasing, the user is relieved of this task and
only needs to ac-couple the signal into the DSX. Note that the
input to the DSX is still fully differential if driven differentially;
that is, Pin +DSXx and Pin −DSXx see the same signal but with
opposite polarity (see the Ultralow Noise, Differential InputDifferential Output VGA section).
R
1.5R
–27.63dB
R
1.5R
–34.54dB
R
1.5R
–41.45dB
R
1.5R
–48.36dB
1.5R
175Ω
1.5R
175Ω
MID
R
1.5R
R
1.5R
R
1.5R
R
1.5R
R
1.5R
NOTES
1. R = 96Ω
2. 1.5R = 144Ω
R
1.5R
R
00540-041
–DSXx
Figure 41. R-1.5R Dual Ladder Network
Rev. G | Page 15 of 32
AD604
AC COUPLING
The DSX portion of the AD604 is a single-supply circuit and,
therefore, its inputs need to be ac-coupled to accommodate
ground-based signals. External Capacitors C1 and C2 in Figure 37
level shift the ground referenced preamplifier output from
ground to the dc value established by VOCM (nominal 2.5 V).
C1 and C2, together with the 175 Ω looking into each of the
DSX inputs (+DSXx and −DSXx), act as high-pass filters with
corner frequencies depending on the values chosen for C1 and
C2. As an example, for values of 0.1 μF at C1 and C2, combined
with the 175 Ω input resistance at each side of the differential
ladder of the DSX, the −3 dB high-pass corner is 9.1 kHz.
If the AD604 output needs to be ground referenced, another
ac coupling capacitor is required for level shifting. This
capacitor also eliminates any dc offsets contributed by the DSX.
With a nominal load of 500 Ω and a 0.1 μF coupling capacitor,
this adds a high-pass filter with −3 dB corner frequency at about
3.2 kHz.
The choice for all three of these coupling capacitors depends on
the application. They should allow the signals of interest to pass
unattenuated while, at the same time, they can be used to limit
the low frequency noise in the system.
GAIN CONTROL INTERFACE
The gain control interface provides an input resistance of
approximately 2 MΩ at VGN1 and gain scaling factors from
20 dB/V to 40 dB/V for VREF input voltages of 2.5 V to 1.25 V,
respectively. The gain scales linearly in decibels for the center
40 dB of gain range, which for VGN is equal to 0.4 V to 2.4 V for
the 20 dB/V scale and 0.2 V to 1.2 V for the 40 dB/V scale. Figure 42
shows the ideal gain curves for a nominal preamplifier gain
of 14 dB, which are described by the following equations:
G (20 dB/V) = 20 × VGN – 5, VREF = 2.500 V
(4)
G (20 dB/V) = 30 × VGN – 5, VREF = 1.666 V
(5)
G (20 dB/V) = 40 × VGN – 5, VREF = 1.250 V
(6)
50
45
40
35
40dB/V
30dB/V
20dB/V
15
2.5
Figure 42. Ideal Gain Curves vs. VGN
3.0
00540-042
1.0
1.5
2.0
GAIN CONTROL VOLTAGE (VGN)
GAIN (dB)
(7)
To achieve single-supply operation and a fully differential input
to the DSX, an active feedback amplifier (AFA) is used. The
AFA is an op amp with two gm stages; one of the active stages is
used in the feedback path (therefore the name), while the other
is used as a differential input. Note that the differential input is
an open-loop gm stage that requires it to be highly linear over
the expected input signal range. In this design, the gm stage that
senses the voltages on the attenuator is a distributed one; for
example, there are as many gm stages as there are taps on the
ladder network. Only a few of them are on at any one time,
depending on the gain control voltage.
The AFA makes a differential input structure possible because
one of its inputs (G1) is fully differential; this input is made up
of a distributed gm stage. The second input (G2) is used for
feedback. The output of G1 is some function of the voltages
sensed on the attenuator taps, which is applied to a high-gain
amplifier (A0). Because of negative feedback, the differential
input to the high-gain amplifier has to be zero; this in turn
implies that the differential input voltage to G2 times gm2 (the
transconductance of G2) has to be equal to the differential
input voltage to G1 times gm1 (the transconductance of G1).
V ATTEN
5
0.5
Gain Scale
ACTIVE FEEDBACK AMPLIFIER (FIXED-GAIN AMP)
VOUT
10
0
2.500 V × 20 dB/V
Usable gain control voltage ranges are 0.1 V to 2.9 V for the
20 dB/V scale and 0.1 V to 1.45 V for the 40 dB/V scale. VGN
voltages of less than 0.1 V are not used for gain control because
below 50 mV the channel (preamplifier and DSX) is powered
down. This can be used to conserve power and, at the same
time, to gate off the signal. The supply current for a powereddown channel is 1.9 mA; the response time to power the device
on or off is less than 1 μs.
LINEAR-IN-dB RANGE
OF AD604 WITH
PREAMPLIFIER
SET TO 14dB
20
–5
VREF =
Therefore, the overall gain function of the AFA is
30
25
From these equations, it can be seen that all gain curves intercept at
the same −5 dB point; this intercept is +6 dB higher (+1 dB) if
the preamplifier gain is set to +20 dB or +14 dB lower (−19 dB)
if the preamplifier is not used at all. Outside the central linear
range, the gain starts to deviate from the ideal control law but
still provides another 8.4 dB of range. For a given gain scaling,
VREF can be calculated as shown in Equation 7.
=
g m1
g m2
×
R1 + R 2
R2
where:
VOUT is the output voltage.
VATTEN is the effective voltage sensed on the attenuator.
(R1 + R2)/R2 = 42
gm1/gm2 = 1.25
The overall gain is thus 52.5 (34.4 dB).
Rev. G | Page 16 of 32
(8)
AD604
The AFA offers the following additional features:
•
The ability to invert the signal by switching the positive
and negative inputs to the ladder network
•
The possibility of using DSX1 input as a second signal
input
•
Fully differential high-impedance inputs when both
preamplifiers are used with one DSX (the other DSX could
still be used alone)
•
Independent control of the DSX common-mode voltage
Under normal operating conditions, it is best to connect a
decoupling capacitor to VOCM, in which case, the commonmode voltage of the DSX is half the supply voltage, which allows
for maximum signal swing. Nevertheless, the common-mode
voltage can be shifted up or down by directly applying a voltage
to VOCM. It can also be used as another signal input, the only
limitation being the rather low slew rate of the VOCM buffer.
If the dc level of the output signal is not critical, another coupling
capacitor is normally used at the output of the DSX; again, this
is done for level shifting and to eliminate any dc offsets contributed
by the DSX (see the AC Coupling section).
Rev. G | Page 17 of 32
AD604
APPLICATIONS INFORMATION
The basic circuit in Figure 43 shows the connections for one
channel of the AD604. The signal is applied at Pin 5. RGN is
normally 0, in which case the preamplifier is set to a gain of 5
(14 dB). When FBK1 is left open, the preamplifier is set to a
gain of 10 (20 dB), and the gain range shifts up by 6 dB. The ac
coupling capacitors before −DSX1 and +DSX1 should be selected
according to the required lower cutoff frequency. In this example,
the 0.1 μF capacitors, together with the 175 Ω seen looking into
each of the DSXx input pins, provide a −3 dB high-pass corner
of about 9.1 kHz. The upper cutoff frequency is determined by
the bandwidth of the channel, which is 40 MHz. Note that the
signal can be simply inverted by connecting the output of the
preamplifier to −DSX1 instead of +DSX1; this is due to the fully
differential input of the DSX.
0.1µF
RGN
VIN
–DSX1
VGN1 24
2
+DSX1
VREF 23
3
PAO1
OUT1 22
4
FBK1
GND1 21
5
PAI1
6
COM1
VNEG 19
+5V
7
COM2
VNEG 18
–5V
8
PAI2
VPOS 17
9
FBK2
GND2 16
10
PAO2
OUT2 15
11
+DSX2
VOCM 14
12
–DSX2
VGN2 13
AD604
VPOS 20
0.1µF
+2.5V
OUT
RL
500Ω
0.1µF
00540-043
0.1µF
VGN
1
Figure 43. Basic Connections for a Single Channel
In Figure 43, the output is ac-coupled for optimum performance.
For dc coupling, as shown in Figure 52, the capacitor can be
eliminated if VOCM is biased at the same 3.3 V common-mode
voltage as the analog-to-digital converter, AD9050.
VREF requires a voltage of 1.25 V to 2.5 V, with between 40 dB/V
and 20 dB/V gain scaling, respectively. Voltage VGN controls
the gain; its nominal operating range is from 0.25 V to 2.65 V
for 20 dB/V gain scaling and 0.125 V to 1.325 V for 40 dB/V
scaling. When VGNx is grounded, the channel powers down
and disables its output.
COM1 is the main signal ground for the preamplifier and needs
to be connected with as short a connection as possible to the input
ground. Because the internal feedback resistors of the preamplifier
are very small for noise reasons (8 Ω and 32 Ω nominally), it is
of utmost importance to keep the resistance in this connection
to a minimum. Furthermore, excessive inductance in this
connection can lead to oscillations.
Because of the ultralow noise and wide bandwidth of the
AD604, large dynamic currents flow to and from the power
supply. To ensure the stability of the part, careful attention to
supply decoupling is required. A large storage capacitor in
parallel with a smaller high-frequency capacitor connected at
the supply pins, together with a ferrite bead coming from the
supply, should be used to ensure high-frequency stability.
To provide for additional flexibility, COM1 can be used to
disable the preamplifier. When COM1 is connected to VP, the
preamplifier is off, yet the DSX portion can be used independently.
This may be of value when cascading the two DSX stages in the
AD604. In this case, the first DSX output signal with respect to
noise is large and using the second preamplifier at this point
would waste power (see Figure 44).
Rev. G | Page 18 of 32
AD604
C1
0.1µF
C2
0.1µF
VIN
(MAX
800mV p-p)
1
–DSX1
VGN1 24
2
+DSX1
VREF 23
VREF
AD604
R1
49.9Ω
3
PAO1
OUT1 22
4
FBK1
GND1 21
5
PAI1
VPOS 20
VSET (<0V)
6
COM1
VNEG 19
–5V
7
COM2
VNEG 18
–5V
– (V1)2
1V
R4
2kΩ
C8
0.33µF
+5V
C3
0.1µF
8
PAI2
VPOS 17
9
FBK2
GND2 16
10
PAO2
OUT2 15
11
+DSX2
VOCM 14
12
–DSX2
VGN2 13
C4
0.1µF
+5V
V1 = VIN × G
C7
0.33µF
C7
0.1µF
8
7
6
5
X1
X2
VP
W
R3
1kΩ
C10
1µF
Y1
Y2
VN
Z
1
2
3
4
R2
453Ω
1
R7
1kΩ
AD835
C6
0.56µF
LOWPASS
FILTER
C11
1µF
OFFS
NULL
NC
8
+VS 7
2
+5V
AD711
–5V
3
OUT 6
4
OFFS 5
NULL
– (A)2
2
–VS
VG
IF V1 = A × cos (wt)
–5V
FB
+5V
C9
0.33µF
RF OUT
R5
2kΩ
R6
2kΩ
FB
–5V
C13
0.1µF ALL SUPPLY PINS ARE DECOUPLED AS SHOWN.
00540-044
C12
0.1µF
R8
2kΩ
+5V
Figure 44. AGC Amplifier with 82 dB of Gain Range
ULTRALOW NOISE AGC AMPLIFIER WITH 82 dB TO
96 dB GAIN RANGE
Figure 44 shows an implementation of an AGC amplifier with
82 dB of gain range using a single AD604. The signal is applied
to connector VIN and, because the signal source is 50 Ω, a
terminating resistor (R1) of 49.9 Ω is added. The signal is then
amplified by 14 dB (Pin FBK1 shorted to PAO1) through the
Channel 1 preamplifier and is further processed by the Channel 1
DSX. Next, the signal is applied directly to the Channel 2 DSX. The
second preamplifier is powered down by connecting its COM2 pin
to the positive supply as explained in the Preamplifier section.
C1 and C2 level shift the signal from the preamplifier into the
first DSX and, at the same time, eliminate any offset contribution
of the preamplifier. C3 and C4 have the same offset cancellation
purpose for the second DSX. Each set of capacitors, combined
with the 175 Ω input resistance of the corresponding DSX,
provides a high-pass filter with a −3 dB corner frequency of
about 9.1 kHz. VOCM is decoupled to ground by a 0.1 μF
capacitor, while VREF can be externally provided; in this
application, the gain scale is set to 20 dB/V by applying 2.500 V.
Because each DSX amplifier operates from a single 5 V supply,
the output is ac-coupled via C6 and C7. The output signal can
be monitored at the connector labeled RF OUT.
Figure 45 and Figure 46 show the gain range and gain error for
the AD604 connected as shown in Figure 44. The gain range is
−14 dB to +82 dB; the useful range is 0 dB to +82 dB if the RF
output amplitude is controlled to ±400 mV (+2 dBm). The main
limitation on the lower end of the signal range is the input
capability of
the preamplifier. This limitation can be overcome by adding an
attenuator in front of the preamplifier, but that would defeat the
advantage of the ultralow noise preamplifier. It should be noted
that the second preamplifier is not used because its ultralow
noise and the associated high-power consumption are overkill
after the first DSX stage. It is disabled in this application by
connecting the COM2 pin to the positive supply. Nevertheless,
the second preamplifier can be used, if so desired, and the
useful gain range increases by 14 dB to encompass 0 dB to
96 dB of gain. For the same +2 dBm output, this allows signals
as small as −94 dBm to be measured.
To achieve the highest gains, the input signal must be bandlimited to reduce the noise; this is especially true if the second
preamplifier is used. If the maximum signal at OUT2 of the AD604
is limited to ±400 mV (+2 dBm), the input signal level at the
AGC threshold is +25 μV rms (−79 dBm). The circuit as shown in
Figure 44 has about 40 MHz of noise bandwidth; the 0.8 nV/√Hz
of input referred voltage noise spectral density of the AD604
results in an rms noise of 5.05 μV in the 40 MHz bandwidth.
Rev. G | Page 19 of 32
AD604
The 50 Ω termination resistor, in parallel with the 50 Ω source
resistance of the signal generator, forms an effective resistance of
25 Ω as seen by the input of the preamplifier, creating 4.07 μV of
rms noise at a bandwidth of 40 MHz. The noise floor of this
channel is consequently 6.5 μV rms, the rms sum of these two
main noise sources. The minimum detectable signal (MDS) for
this circuit is +6.5 μV rms (−90.7 dBm). Generally, the measured
signal should be about a factor of three larger than the noise
floor, in this case 19.5 μV rms. Note that the 25 μV rms signal
that this AGC circuit can correct for is just slightly above the
MDS. Of course, the sensitivity of the input can be improved by
band-limiting the signal; if the noise bandwidth is reduced by a
factor of four to 10 MHz, the noise floor of the AGC circuit with a
50 Ω termination resistor drops to +3.25 μV rms (−96.7 dBm).
Further noise improvement can be achieved by an input matching
network or by transformer coupling of the input signal.
90
70
f = 1MHz
60
Figure 47 shows the control voltage, VGN, vs. the input power at
frequencies of 1 MHz (solid line) and 10 MHz (dashed line) at
an output regulated level of 2 dBm (800 mV p-p). The AGC
threshold is evident at a PIN of about −79 dBm; the highest input
power that can still be accommodated is about +3 dBm. At this
level, the output starts being distorted because of clipping in the
preamplifier.
GAIN (dB)
50
40
30
20
10
0
00540-045
–10
–20
–30
0.1
0.5
0.9
1.3
1.7
VGN (V)
2.1
2.5
For example, if the signal presented to the detector is V1 = A ×
cos(ωt) as indicated in Figure 44, the output of the squarer is
−(V1)2/1 V. The reason for all the minus signs in the detection
circuitry is the necessity of providing negative feedback in the
control loop; actually, if VSET becomes greater than 0 V, the
control loop provides positive feedback. Squaring A × cos(ωt)
results in two terms, one at dc and one at 2ω; the following lowpass filter passes only the −(A)2/2 dc term. This dc voltage is
now forced equal to the voltage, VSET, by the control loop. The
squarer, together with the low-pass filter, functions as a meansquare detector. As should be evident by controlling the value of
VSET, the amplitude of the voltage V1 can be set at the input of
the AD835; if VSET equals −80 mV, the AGC output signal
amplitude is ±400 mV.
4.5
2.9
4.0
CONTROL VOLTAGE (V)
Figure 45. Cascaded Gain vs. VGN (Based on Figure 44)
4
f = 1MHz
3
GAIN ERROR (dB)
2
1
0
3.0
2.5
2.0
10MHz
1MHz
1.5
1.0
–1
0.5
–80
–2
0.7
1.2
1.7
2.2
–70
–60
–50
–40
–30
PIN (dBm)
–20
–10
0
10
Figure 47. Control Voltage vs. Input Power of the Circuit in Figure 44
00540-046
–3
–4
0.2
3.5
00540-047
80
the incoming signal frequency, while passing the low frequency
AM information. The following integrator with a time constant of
2 ms set by R8 and C11 integrates the error signal presented by
the low-pass filter and changes VG until the error signal is equal
to VSET.
2.7
VGN (V)
Figure 46. Cascaded Gain Error vs. VGN (Based on Figure 44)
The descriptions of the detector circuitry functions, comprising
a squarer, a low-pass filter, and an integrator, follow. At this
point, it is necessary to make some assumptions about the input
signal. The following explanation of the detector circuitry presumes
an amplitude modulated RF carrier where the modulating signal is
at a much lower frequency than the RF signal. The AD835
multiplier functions as the detector by squaring the output signal
presented to it by the AD604. A low-pass filter following the
squaring operation removes the RF signal component at twice
As previously mentioned, the second preamplifier can be used
to extend the range of the AGC circuit in Figure 44. Figure 48
shows the modifications that must be made to Figure 46 to achieve
96 dB of gain and dynamic range. Because of the extremely high
gain, the bandwidth must be limited to reject some of the noise.
Furthermore, limiting the bandwidth helps suppress highfrequency oscillations. The added components act as a low-pass
filter and dc block (C5 decouples the 2.5 V common-mode
output of the first DSX). The ferrite bead has an impedance of
about 5 Ω at 1 MHz, 30 Ω at 10 MHz, and 70 Ω at 100 MHz.
The bead, combined with R2 and C6, forms a 1 MHz low-pass
filter.
Rev. G | Page 20 of 32
AD604
Figure 49 shows the control voltage vs. the input power at 1 MHz
to the circuit shown in Figure 48; note that the AGC threshold is at
−95 dBm. The output signal level is set to 800 mV p-p by applying
−80 mV to the VSET connector.
the signal amplitude compared with when they are driven
single-ended.
AD604
C1
0.1µF
C2
0.1µF
C5
0.1µF
VREF 23
3
PAO1
OUT1 22
4
FBK1
GND1 21
VREF
C7
0.1µF
5
PAI1
VPOS 20
+5V
VGN1 24
6
COM1
VNEG 19
–5V
2
+DSX1
VREF 23
7
COM2
VNEG 18
–5V
3
PAO1
OUT1 22
8
PAI2
VPOS 17
+5V
4
FBK1
GND1 21
9
FBK2
GND2 16
10 PAO2
OUT2 15
11 +DSX2
VOCM 14
12 –DSX2
VGN2 13
VIN–
C4
0.1µF
VPOS 20
5
PAI1
6
COM1
VNEG 19
C6
560pF
7
COM2
VNEG 18
8
PAI2
VPOS 17
9
FBK2
GND2 16
FB
+5V
C3
0.1µF
10 PAO2
OUT2 15
FB
–5V
11 +DSX2
VOCM 14
12 –DSX2
VGN2 13
AD604
C3
0.1µF
C13
0.1µF
C12
0.1µF
C6
0.1µF
VOUT+
R1
453Ω
R2
453Ω
VOUT–
VG
C5
0.1µF
ALL SUPPLY PINS ARE DECOUPLED AS SHOWN.
00540-048
Figure 50. Ultralow Noise, Differential Input-Differential Output VGA
FAIR-RITE
#2643000301
Figure 48. Modifications of the AGC Amplifier to Create 96 dB of Gain Range
4.5
4.0
CONTROL VOLTAGE (V)
VGN1 24
+DSX1
–DSX1
FB
3.5
3.0
2.5
2.0
–DSX1
2
1
VIN+
R2
499Ω
1
00540-050
At 1 MHz, the attenuation is about −0.2 dB, increasing to −6 dB
at 10 MHz and −28 dB at 100 MHz. Signals less than approximately
1 MHz are not significantly affected.
1MHz
Figure 51 displays the output signals VOUT+ and VOUT− after
a −20 dB attenuator formed between the 453 Ω resistors shown
in Figure 50 and the 50 Ω loads presented by the oscilloscope
plug-in. R1 and R2 are inserted to ensure a nominal load of 500 Ω
at each output. The differential gain of the circuit is set to 20 dB
by applying a control voltage, VGN, of 1 V; the gain scaling is
20 dB/V for a VREF of 2.500 V; the input frequency is 10 MHz,
and the differential input amplitude is 100 mV p-p. The resulting
differential output amplitude is 1 V p-p as can be seen on the
scope photo when reading the vertical scale as 200 mV/div.
1.5
20mV
1.0
0
–100 –90 –80 –70 –60 –50 –40 –30 –20 –10
PIN (dBm)
00540-049
0.5
0
20ns
100
ACTUAL
VOUT
+500mV
90
10
Figure 49. Control Voltage vs. Input Power of the Circuit in Figure 48
ULTRALOW NOISE, DIFFERENTIAL INPUTDIFFERENTIAL OUTPUT VGA
10
–500mV
0%
Rev. G | Page 21 of 32
20mV
NOTES
1. THE OUTPUT AFTER 10× ATTENUATER FORMED
BY 453Ω TOGETHER WITH 50Ω OF 7A24 PLUG-IN.
Figure 51. Output of VGA in Figure 50 for VGN = 1 V
00540-054
Figure 50 shows how to use both preamplifiers and DSXs to
create a high impedance, differential input-differential output
VGA. This application takes advantage of the differential inputs
to the DSXs. Note that the input is not truly differential in the
sense that the common-mode voltage needs to be at ground to
achieve maximum input signal swing. This has largely to do
with the limited output swing capability of the output drivers of
the preamplifiers; they clip around ±2.2 V due to having to drive
an effective load of about 30 Ω. If a different input common-mode
voltage needs to be accommodated, ac coupling (as in Figure 48)
is recommended. The differential gain range of this circuit runs
from 6 dB to 54 dB, which is 6 dB higher than each individual
channel of the AD604 because the DSX inputs now see twice
AD604
The gain is controlled by means of a digital byte that is input to
an AD7226 DAC that outputs the analog gain control signal.
The output common-mode voltage of the AD604 is set to VPOS/2
by means of an internal voltage divider. The VOCM pin is
bypassed with a 0.1 μF capacitor to ground.
MEDICAL ULTRASOUND TGC DRIVING THE
AD9050, A 10-BIT, 40 MSPS ADC
The AD604 is an ideal candidate for the time gain control (TGC)
amplifier that is required in medical ultrasound systems to limit
the dynamic range of the signal that is presented to the ADC.
Figure 52 shows a schematic of an AD604 driving an AD9050
in a typical medical ultrasound application.
J2
ANALOG
INPUT
50Ω
50Ω
0.1µF
(MSB) D9 15
0.1µF
0.1µF
0.1µF
The DSX output is optionally filtered and then buffered by
an AD9631 op amp, a low distortion, low noise amplifier. The
op amp output is ac-coupled into the self-biasing input of an
AD9050 ADC that is capable of outputting 10 bits at a 40 MSPS
sampling rate.
AD9050
1
–DSX1
VGN1 24
2
+DSX1
VREF 23
3
PAO1
OUT1 22
4
FBK1
GND1 21
FILTER
5
PAI1
VPOS 20
+5V
0.1µF
6
COM1
VNEG 19
7
COM2
VNEG 18
8
PAI2
VPOS 17
9
FBK2
GND2 16
10 PAO2
OUT2 15
11 +DSX2
VOCM 14
12 –DSX2
VGN2 13
AD604
0.1µF
1kΩ
–5V
0.1µF
1kΩ
2
3
AD9631
–IN
OUT
D7 17
4
VREFIN
D6 18
5
COMP
D5 19
6
REFBP
D4 24
9
AINB
D3 25
10 AIN
14 OR
OPTIONAL
0.1µF
VOUTB
VOUTC 20
VOUTA
VOUTD 19
3
VSS
4
VREF
5
AGND
A1 16
DGND
DB7
7
(MSB)
8 DB6
WR 15
DB0 14
(LSB)
DB1 13
VDD 18
D1 27
(LSB) D0 28
VDD 20
VDD 22
CLK
0.1µF
0.1µF
+15V
A0 17
DB5
DB2 12
10 DB4
DB3 11
00540-051
AD7226
A/D
OUTPUT
D2 26
13 ENCODE
0.1µF
2
9
VREFOUT
1kΩ
1
6
0.1µF
+IN
100Ω
VREF
6
D8 16
3
DIGITAL GAIN CONTROL
Figure 52. TGC Circuit for Medical Ultrasound Application
Rev. G | Page 22 of 32
AD604
C3
0.1µF
PAO1
C1
0.1µF
NOTE 2 R2
RGN
VG1
1
–DSX1
VGN1 24
2
+DSX1
VREF 23
3
PAO1
OUT1 22
4
FBK1
GND1 21
VREF
C4
0.1µF
C2
5pF
C12
0.1µF
AD604
IN1
IN2
PAO2
R3
RGN
C6
0.1µF
5
PAI1
VPOS 20
6
COM1
VNEG 19
7
COM2
VNEG 18
8
PAI2
VPOS 17
9
FBK2
GND2 16
10
PAO2
OUT2 15
11
+DSX2
VOCM 14
R1
500Ω
OUT1
NOTE 3
OPTIONAL
C11
0.1µF
+5V
–5V
C10
0.1µF
C9
0.1µF
C8
5pF
NOTE 3
R4
500Ω
C7
0.1µF
OUT2
VOCM
0.1µF
–DSX2
VGN2 13
VG2
NOTES
1. PAO1 AND PAO2 ARE USED TO MEASURE PREAMPS.
2. RGN = 0 NOMINALLY; PREAMP GAIN = 5, RGN = OPEN; PREAMP GAIN = 10.
3. WHEN MEASURING BW WITH 50Ω SPECTRUM ANALYZER, USE 450Ω IN SERIES.
Figure 53. Basic Test Board
HP3577B
OUT
R
A
HP11636B
POWER
SPLITTER
50Ω
PAI
0.1µF
450Ω
DUT
00540-053
49.9Ω
AD604
Figure 54. Setup for Gain Measurements
Rev. G | Page 23 of 32
00540-052
12
C5
0.1µF
AD604
EVALUATION BOARD
Figure 56 is a photograph of the AD604 evaluation board assembly.
Multiple input connections, testpoints, switch-selectable options,
and on-board trims offer convenience when configuring the
AD604 in various operating modes.
The evaluation board requires only a dual 5 V supply capable of
200 mA or higher to operate both channels. Prior to shipment,
the evaluation board is fully tested. Users need only attach power
supply leads and the appropriate test equipment to the board.
Because of this flexibility, some of the component positions on
the board are user selectable. Installing or changing additional
parts, such as gain resistor values or SMA connectors for nonstandard I/O, is discretionary.
00540-156
The AD604-EVALZ is fabricated on a 4-layer board with inner
power and ground layers. Figure 55 is a photograph of the top
views of the board, assembly and artwork layers are shown in
Figure 56, a representative test setup is shown in Figure 57, and
Figure 58 to Figure 62 show the artwork drawings of the
evaluation board.
Figure 56. AD604 Evaluation Board Assembly
DSX INPUT CONNECTIONS
00540-155
The VGA input configuration options are single-ended or
differential. Connections are provided for each of the inputs and
are labeled VGAx+IN and VGAx−IN. Switches VGAx+IN and
VGAx−IN select between the preamplifier outputs (PAOx) and
the VGA SMA input connectors. For direct drive of the Channel
VGA channels from an external source, such as a signal generator,
simply use the switches to select the desired signal paths. Refer
to the schematic shown in Figure 63 for circuit details.
Because the VGA section of the AD604 uses a single 5 V supply,
the VGA inputs are ac-coupled. The VGA ladder network input is
connected to the device ±DSX1/±DSX2 pins, and the network
impedance is nominally 200 Ω. If direct access to the DSX is
desired, signals can be applied to the test loops ±DSX1/±DSX2.
Optionally, SMA connectors can be installed at the VGAx±IN
locations and 66.5 Ω, 1% resistors at R5, R6, R9, and R10 to
provide an input termination value of 49.9Ω.
Cascade VGAs to Boost Gain
Figure 55. Top View Photograph of AD604 Evaluation Board
CONNECTING A WAVEFORM TO THE AD604-EVALZ
To test the AD604, apply the desired waveform to either or both
of the preamplifier input SMA connectors, PRE1IN or PRE2IN.
Referring to the schematic in Figure 63, the inputs are already
terminated 49.9 Ω resistors (R7 and R8); therefore, no external
terminating networks are required.
To enable the preamplifiers, insert jumpers in the JP8 and JP9
rightmost positions; this connects COM1 and COM2 to ground.
Power down the preamplifiers by inserting jumpers in the JP8
and JP9 leftmost positions.
The AD604 channels may be cascaded to achieve higher gain
range by moving the VG2+IN_SW to its CASCADE position.
The resulting single-channel gain range is 96 dB.
The gains of cascaded VGAs are controlled independently or in
common. For common (parallel) control, move the gain control
switch, GN2, to the 1&2 position.
To use the optional GNx_ADJ trimmers for static gain control
voltages, set GN1 to EXT and GN2 to 2ONLY. For external
control, connect the desired signal source to the test loops, VGNx.
Rev. G | Page 24 of 32
AD604
PREAMPLIFIER GAIN
DC OPERATING CONDITIONS
The default gain of the preamplifier is 20 dB, 14 dB is achieved
with 0 Ω resistors in the R11and R12 positions. The 14 dB and
20 dB preset gains are accurate because of the close matching of
the internal thin film resistors. The gain accuracy after installing
external resistors is subject to inherent tolerance of absolute
accuracy; however, any pair of preamplifiers is reasonably
matched when standard 1% SM resistors are used.
Table 4 lists the trimmers and their functions provided for
convenient dc level adjustments of gain, reference voltage, and
output common-mode voltage. Table 5 lists the switches and
their functions.
OUTPUTS
The DSX outputs are available on the OUT1 and OUT2 SMA
connectors and are series terminated with decoupling capacitors
and 49.9 Ω series resistors.
Table 4. Trimmer Functions
Trimmer
GN1_ADJ
VREF_ADJ
VOCM_ADJ
GN2_ADJ
Function
Optional dc level for VGA Channel 1
Optional dc level to adjust reference voltage
Output common-mode voltage adjustment
Optional dc level for VGA Channel 2
Table 5. Jumpers
VG2−IN
GN1
REF
OCMV
Function
Connects –DSX1 to the SMA connector VGA1−IN or to ground.
Connects +DSX1 (ac-coupled) to the preamplifier output of Channel 1 (PAO1) or to the SMA connector VGA1+ IN.
Enables/disables Channel 1 preamp by connecting COM1 to ground (enable) or to +5V (disable).
Enables/disables Channel 2 preamp by connecting COM2 to ground (enable) or to +5V (disable).
Connects the +DSX input to the SMA VGA2+IN, the Channel 2 preamplifier output (PAO2), or the output of Channel 1 for
a cascade connection.
Connects –DSX2 to SMA VGA2−IN or to ground.
Connects the VGN1 input to trimmer GN1_ADJ gain adjust wiper or leaves the input unconnected.
Connects the reference input to the VREF_ADJ trimmer or leaves the input connected.
Connects VOCM to the common-mode voltage trimmer, VOCM_ADJ.
POWER SUPPLY
OSCILLOSCOPE TO
MONITOR VOUT
FUNCTION
GENERATOR SINE
INPUT
00540-157
Switch
VG1−IN
VG1+IN
CH1
CH2
VG2+IN_SW
Figure 57. A Representative Test Setup of the AD604-EVALZ
Rev. G | Page 25 of 32
AD604
00540-158
00540-161
EVALUATION BOARD ARTWORK AND SCHEMATIC
Figure 61. Internal Power Plane
00540-159
00540-162
Figure 58. Component Side Copper
Figure 59. Secondary Side Copper
00540-160
Figure 62. Component Side Silkscreen of the AD604 Evaluation Board
Figure 60. Internal Ground Plane
Rev. G | Page 26 of 32
AD604
+5 V
C1 +
10µF
10V
+5V
GND
–5V
–DSX1
VG1–IN
+5V
EXT
+DSX1
AD604
VG1+IN
C9
0.1µF
PAO1
PAO1
1
–DSX1
VGN1
+DSX1
VREF
PAO1
OUT1
FBK1
GND1
PAI1
VPOS
COM1
VNEG
7 COM2
VNEG
2
3
R11
0Ω
PAI1
R7
49.9Ω
4
5
CH2
CH1
DIS
DIS
6
+5V
EN
EN
8
PAO2
VG2+IN
_SW
4
SMA
3
PAO2
R12
0Ω
+DSX2
C10
0.1µF
2
R10
66.5Ω
VGA2
–IN
–DSX2
1
+5V
23
22
PAI2
9 FBK2
10
PAO2
11 +DSX2
VPOS
GND2
OUT2
VOCM
REF
C5
1nF
VREF
C6
0.1µF
21
20
+5V
19
C4
0.1µF –5V
12
–DSX 2
VGN2
R13
49.9Ω
C13
0.1µF
R14 C14
49.9Ω 0.1µF
18
+5V
17
16
OUT2
C2
0.1µF
OUT2
_TP
15
14
VREF
_ADJ
OUT1
OCMV 10kΩ
VOCM
VGN2
CASCADE
EXT
10kΩ
INT
OUT1
_TP
13
EXT
C7
0.1µF
1& 2
+5V
VOCM
_ADJ
INT
GN2
C12
1nF
VG2–IN
SMA
R9
66.5Ω
GN1
_ADJ
VGN1
24
PAI2
R8
49.9Ω
10kΩ
INT
SMA
VGA2
+IN
GND4
C8
0.1µF
SMA
R6
66.5Ω
PRE2
IN
GND3
C3
10µF
+ 10V
GND
PRE1
IN
GND2
GN1
R5
66.5Ω
VGA1
+IN
GND1
2ONLY
+5V
C11
0.1µF
10kΩ
GN2
_ADJ
GND
NOTE:
PARTS IN GRAY INSTALLED AT USER DISCRETION
Figure 63. Evaluation Board Schematic
Rev. G | Page 27 of 32
00540-163
VGA1
–IN
–5V
AD604
OUTLINE DIMENSIONS
1.280 (32.51)
1.250 (31.75)
1.230 (31.24)
24
13
1
0.280 (7.11)
0.250 (6.35)
0.240 (6.10)
12
0.325 (8.26)
0.310 (7.87)
0.300 (7.62)
0.100 (2.54)
BSC
0.060 (1.52)
MAX
0.210 (5.33)
MAX
0.015
(0.38)
MIN
0.150 (3.81)
0.130 (3.30)
0.115 (2.92)
0.022 (0.56)
0.018 (0.46)
0.014 (0.36)
0.195 (4.95)
0.130 (3.30)
0.115 (2.92)
0.015 (0.38)
GAUGE
PLANE
SEATING
PLANE
0.430 (10.92)
MAX
0.005 (0.13)
MIN
0.014 (0.36)
0.010 (0.25)
0.008 (0.20)
0.070 (1.78)
0.060 (1.52)
0.045 (1.14)
071006-A
COMPLIANT TO JEDEC STANDARDS MS-001
CONTROLLING DIMENSIONS ARE IN INCHES; MILLIMETER DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF INCH EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN.
CORNER LEADS MAY BE CONFIGURED AS WHOLE OR HALF LEADS.
Figure 64. 24-Lead Plastic Dual In-Line Package [PDIP]
Narrow Body
(N-24-1)
Dimensions shown in inches and (millimeters)
15.60 (0.6142)
15.20 (0.5984)
13
24
7.60 (0.2992)
7.40 (0.2913)
12
2.65 (0.1043)
2.35 (0.0925)
0.30 (0.0118)
0.10 (0.0039)
COPLANARITY
0.10
10.65 (0.4193)
10.00 (0.3937)
1.27 (0.0500)
BSC
0.51 (0.0201)
0.31 (0.0122)
SEATING
PLANE
0.75 (0.0295)
45°
0.25 (0.0098)
8°
0°
0.33 (0.0130)
0.20 (0.0079)
COMPLIANT TO JEDEC STANDARDS MS-013-AD
CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN.
Figure 65. 24-Lead Standard Small Outline Package [SOIC_W]
Wide Body
(RW-24)
Dimensions shown in millimeters and (inches)
Rev. G | Page 28 of 32
1.27 (0.0500)
0.40 (0.0157)
12-09-2010-A
1
AD604
8.50
8.20
7.90
13
24
5.60
5.30
5.00
1
8.20
7.80
7.40
12
0.65 BSC
0.38
0.22
SEATING
PLANE
8°
4°
0°
0.95
0.75
0.55
COMPLIANT TO JEDEC STANDARDS MO-150-AG
060106-A
0.05 MIN
COPLANARITY
0.10
0.25
0.09
1.85
1.75
1.65
2.00 MAX
Figure 66. 24-Lead Shrink Small Outline Package [SSOP]
(RS-24)
Dimensions shown in millimeters
ORDERING GUIDE
Model 1
AD604ANZ
AD604AR
AD604AR-REEL
AD604ARZ
AD604ARZ-RL
AD604ARS
AD604ARS-REEL7
AD604ARSZ
AD604ARSZ-RL
AD604ARSZ-R7
AD604-EVALZ
1
Temperature Range
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
Package Description
24-Lead Plastic Dual In-Line Package [PDIP]
24-Lead Standard Small Outline Package [SOIC_W]
24-Lead Standard Small Outline Package [SOIC_W]
24-Lead Standard Small Outline Package [SOIC_W]
24-Lead Standard Small Outline Package [SOIC_W]
24-Lead Shrink Small Outline Package [SSOP]
24-Lead Shrink Small Outline Package [SSOP]
24-Lead Shrink Small Outline Package [SSOP]
24-Lead Shrink Small Outline Package [SSOP]
24-Lead Shrink Small Outline Package [SSOP]
Evaluation Board
Z = RoHS Compliant Part.
Rev. G | Page 29 of 32
Package Option
N-24-1
RW-24
RW-24
RW-24
RW-24
RS-24
RS-24
RS-24
RS-24
RS-24
AD604
NOTES
Rev. G | Page 30 of 32
AD604
NOTES
Rev. G | Page 31 of 32
AD604
NOTES
©1996–2010 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D00540-0-12/10(G)
Rev. G | Page 32 of 32