Evaluation Board User Guide UG-304
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Evaluation Board User Guide UG-304 One Technology Way • P.O. Box 9106 • Norwood, MA 02062-9106, U.S.A. • Tel: 781.329.4700 • Fax: 781.461.3113 • www.analog.com Evaluating the ADM1075 −48 V Hot-Swap Controller and Digital Power Monitor with PMBus Interface FEATURES GENERAL DESCRIPTION Full support evaluation kit for the ADM1075 Supports LFCSP device package Board populated and tested with −48 V, 10 A, 680 µF design Input voltage range of −36 V to −75 V PMBus™ communication supported Isolated PMBus interface for −48 V operation Special N-MOSFET footprint to accommodate different FET packages Supports up to 3 sense resistors in parallel Supports up to 3 field effect transistors (FETs) in parallel 3 on-board ADT75 accurate temperature sensors Supports cascade setup for multiple boards Toggle and push-button switches for easy input control LED indicated status outputs The EVAL-ADM1075EBZ is a compact full feature evaluation board for the ADM1075-1ACPZ and ADM1075-2ACPZ devices. The layout gives users a clear visual of all the peripheral components and the hot-swap power path. The layout also maximizes the ability of the board to dissipate heat for some of the key components on the power path, allowing evaluation of high current hot-swap setups. Three sense-resistor slots and three multipackage FET slots give users great flexibility and allow them to simulate a wide range of application setups. HARDWARE REQUIREMENTS Multiple test points allow easy access to all critical points/pins. Seven LEDs give users a direct visual indication of variations in the board status, such as system input voltage, isolation power, IC PWRGD output, LATCH output, and GPO outputs. Three ADT75 digital temperature sensors on the back of the board allow users to obtain the FET temperature through an I2C bus in real time. USB-to-serial-I/O interface USB-SDP-CABLEZ (The USB-SDPCABLEZ is not supplied in the evaluation kit and should be ordered separately from Analog Devices, Inc. Only one USB-SDP-CABLEZ is required in the multiboard cascade setup.) 8-way, 150 mm Micro-MaTch ribbon cable (optional) The board supports I2C communication, allowing users to communicate with the ADM1075 and the ADT75. A 64 Kb I2C EEPROM is used to store the ADC resistor divider and sense resistor values on board for use with the evaluation software. The evaluation kit also supports cascade setup so that multiple evaluation boards can be connected and share the same I2C bus. SOFTWARE REQUIREMENT The boards are fully compatible with the ADM1075 evaluation software tool, which can be downloaded at http://www.analog.com/hotswaptools. PACKAGE CONTENTS EVAL-ADM1075EBZ evaluation board Analog Devices hot-swap and power monitoring evaluation software Users need a USB-SDP-CABLEZ USB-to-I2C dongle to use the evaluation software tools. A Micro-MaTch ribbon cable may also be required if multiple evaluation boards are cascaded. This cable can be ordered through Farnell. The evaluation board is prepopulated and tested with a −48 V (−36 V minimum to −75 V maximum), 10 A hot-swap design with a 680 µF output capacitor. The part is configured to retry seven times; however, the board is easily reconfigurable to select different retry schemes (see Table 6). Complete specifications for the ADM1075 can be found in the ADM1075 data sheet available from Analog Devices and should be consulted in conjunction with this user guide when using the evaluation board. PLEASE SEE THE LAST PAGE FOR AN IMPORTANT WARNING AND LEGAL TERMS AND CONDITIONS. Rev. B | Page 1 of 16 UG-304 Evaluation Board User Guide TABLE OF CONTENTS Features .............................................................................................. 1 Switch, Jumper, and LED Functions ...........................................5 Package Contents .............................................................................. 1 Evaluation Board Overview .............................................................6 Hardware Requirements .................................................................. 1 Evaluation Board Lab Setup .............................................................9 Software Requirement...................................................................... 1 Board Specifications......................................................................9 General Description ......................................................................... 1 Test Plots ...................................................................................... 10 Revision History ............................................................................... 2 Evaluation Board Schematics and Artwork ................................ 11 Evaluation Board Description......................................................... 3 Ordering Information .................................................................... 14 Evaluation Board Hardware ............................................................ 5 Bill of Materials ........................................................................... 14 REVISION HISTORY 4/13—Rev. A to Rev. B Changes Figure 1 .............................................................................. 3 Changes to Table 7 ............................................................................ 9 Changes to Figure 17 ...................................................................... 11 Changes to Table 8 .......................................................................... 14 9/12—Rev. 0 to Rev. A Changes to Package Contents, to Hardware Requirements, and to General Description ............................................................. 1 Changes to Evaluation Board Description Section ...................... 3 Changes to Figure 2 .......................................................................... 4 Changes to Table 2 ............................................................................ 5 Changes to Figure 10 ........................................................................ 9 11/11—Revision 0: Initial Version Rev. B | Page 2 of 16 Evaluation Board User Guide UG-304 EVALUATION BOARD DESCRIPTION The evaluation board is designed to demonstrate many different features of the ADM1075. Not all components are required in a typical design. The functional block diagram in Figure 1 shows the key components of the evaluation board. The typical lab setup is shown in Figure 2. The hot-swap line input voltage is connected across the RTN IN and −48V IN connectors. A resistive load can be connected across RTN OUT and −48V OUT. The mini-USB connector is used to supply 5 V power to the isolated section of the board while the USB-SDP-CABLEZ is connected to the 10-way connector, SK3, for isolated I2C communication. Isolation is required in most −48 V applications because there is a large ground potential difference between the −48 V section of the board and a PC or microcontroller. The ADuM1250 is used to demonstrate I2C isolation on the board, and the ADuM3200 is used to demonstrate isolation of other digital signals. The ADuM5404 provides quad-channel digital isolation with isoPower®. An integrated dc-to-dc converter provides up to 500 mW of regulated, isolated power from the isolated side to the −48 V side. When the isolated section is powered, the isoPower is switched in to power the 5 V components on the primary side of the board. –48V RTN (0V) RDROP = 3kΩ 825kΩ 1μF 560kΩ VEE SHDN_ISO SPLYGD VCC AND REFERENCE GENERATOR OV ADuM3200 RESTART LATCH GPO1/ALERT1/CONV GPO2/ALERT2 SDAO SDAI SCL ADR POWER ACCUMULATOR UVH UVL SHDN VIN POWER MULTIPLIER UNDERVOLTAGE AND OVERVOLTAGE DETECTOR DIGITAL AND PMBus 12-BIT ADC ADC_AUX ADC_V 11.3kΩ FET POWER FOLDBACK CONTROL VCAP DRAIN SDA_ISO ADuM1250 LATCH 1.8MΩ LATCH_ISO GPO2 ADuM5404 PLIM VEE ISET GATE CONTROL GATE CURRENT LIMIT SENSE+ 1μF GPO2_ISO PWRGD_ISO 1kΩ FAULT TIMER SCL_ISO VEE PWRGD 16kΩ CLOAD = 680μF RESTART_ISO 150kΩ SPLYGD SPLYGD_ISO N-FET RSENSE = 2mΩ SENSE– TIMER SS VEE_G VEE 10070-101 470nF –48V Figure 1. Functional Block Diagram Rev. B | Page 3 of 16 Evaluation Board User Guide 10070-102 UG-304 Figure 2. Board Lab Setup Table 1. Emitter Follower Configuration Value 0Ω Not populated Not populated 0Ω 0Ω 11 V Zener Effect System power to Emitter Follower 1 Isolates Emitter Follower 1 from Emitter Follower 2 Power 5 V LED off other emitter follower (Emitter Follower 2) Powers 5 V LED off Emitter Follower 2 Powers VIN directly via emitter follower 1 Powers VIN directly with ~10.5 V The ADM1075 can be powered via a shunt resistor from the hotswap line voltage or can be powered directly from a 9.2 V to 11.5 V supply. The shunt power option is the default on the evaluation board; however, an emitter follower can be reconfigured to generate the chip voltage directly. The required board modifications are shown in Table 1. More information on powering the ADM1075 can be found in the ADM1075 data sheet. The default power configuration is shown in Figure 3, and the emitter follower configuration is shown in Figure 4. RTN 10.5V TERMINAL BLOCK 12V SHUNT 5V LEDs 5V isoPower® LOAD USB MINI iCouplers ISOLATED 5V TEMP SENSORS ISOLATED AREA EEPROM OPTIONAL POWER PATH CONFIGURABLE POWER PATH TERMINAL BLOCK 5V isoPower® Figure 4. Board Power (Emitter Follower) LOAD USB MINI iCouplers ISOLATED 5V ADM1075 TEMP SENSORS EEPROM DEFAULT POWER PATH OPTIONAL POWER PATH 10070-103 –48V TERMINAL BLOCK 5V DEFAULT POWER PATH EMITTER FOLLOWER 2 5V ISOLATED AREA ADM1075 –48V TERMINAL 5V BLOCK 5V LEDs EMITTER FOLLOWER 2 5V RTN EMITTER FOLLOWER 1 EMITTER FOLLOWER 1 Figure 3. Board Power (Shunt) Rev. B | Page 4 of 16 10070-104 Component R57 R25 R59 R43 R58 D5 Evaluation Board User Guide UG-304 EVALUATION BOARD HARDWARE SWITCH, JUMPER, AND LED FUNCTIONS Table 2. Connector Functions Connector RTN IN, −48V IN RTN OUT, −48V OUT J6 SK1, SK2 J9 J7 J8 J5 SK3 Description Hot-swap line voltage inputs that also power the board components. Input voltage is 36 V to 75 V. Hot-swap line voltage outputs. 5 V auxiliary board voltage. Not required; emitter follower circuit used to generate 5 V from 48 V input. Bottom and top cascade connectors; connect with a Micro-MaTch ribbon cable to link with other EVAL-ADM1075EBZ boards. I2C/PMBus communication dongle connector. From top down: VEE, SDA, SCL. Note that the dongle should only be connected at this side (primary side) if using a 0 V to 48 V supply. If using a −48 V to 0 V supply, the USB port can be damaged. This 3-pin connector is designed to be used with the USB-SMBUS-CABLEZ dongle. Not required if using USB-SDP-CABLEZ. Isolated side I2C/PMBus communication dongle connector. From top down: SCL, SDA, GND. This 3-pin connector is designed to be used with the USB-SMBUS-CABLEZ dongle. Not required if using USB-SDP-CABLEZ. 5 V isolation supply voltage (power supply). 5 V isolation supply voltage (mini-USB). 10-way isolated side connector for USB-SDP-CABLEZ; I2C communication and 5 V supply. Table 3. Switch Functions Switch S_SHDN2 S_SHDN S_DeLATCH S_RST Description Toggle switch to shut down hot swap. Right = hot swap enabled, and left = hot swap disabled. Push-button switch to generate shutdown. Can be used to clear faults. Note that SHDN has a seven-retry counter. After seven SHDN events, GPO2 goes active low. A restart or clear via PMBus is required to enable the hot swap again. Push-button switch to clear latch after seven shutdown events (not on Rev. 0 boards). Push-button switch to generate 10 sec restart. Table 4. LED Functions LED D_INPUT D_LATCH D_PWRGD D_SPLYGD D_GPO1 D_GPO2 D_ISO Description Voltage input > ~10 V detected. Active high; green. LATCH, active low; red. PWRGD, active low; green. SPLYGD, active low; green. GPO1/ALERT1/CONV, active low; yellow. GPO2/ALERT2, active low; yellow. Isolation 5 V power supply. Active high; blue (not on Rev. 0 boards). Table 5. On-Board ICs IC U1 U2 U3 U4 U5 UT1 to UT3 Description ADM1075 main IC 64 kb I2C EEPROM ADuM3200, dual-channel digital isolator ADuM1250, dual I2C isolator ADuM5404, quad-channel isolator with integrated dc-to-dc converter ADT75, ±2°C accurate, 12-bit digital temperature sensor, sensing temperature on the MOSFETs Table 6. Retry Configuration Retry Scheme No Retries (Latch Off ) 7 Retries, Then Latch Off (Default) 1 Retry Every 10 Seconds 7 Retries Every 10 Seconds R_7retry Not populated 0Ω Not populated Not populated BOM Component R_1rty_10s Not populated Not populated 0Ω Not populated Rev. B | Page 5 of 16 R_7rty_10s Not populated Not populated Not populated 0Ω UG-304 Evaluation Board User Guide 10070-001 EVALUATION BOARD OVERVIEW Figure 5. Evaluation Board Top Side (Rev. A) Rev. B | Page 6 of 16 UG-304 10070-002 Evaluation Board User Guide Figure 6. Evaluation Board Bottom Side 1 3 2 10070-003 1 Figure 7. Multipackage N-MOSFET Footprint Rev. B | Page 7 of 16 Evaluation Board User Guide 10070-004 UG-304 Figure 8. Recommended Sense Resistor Layout (Not on Rev. 0 Boards) 8.40mm 1.60mm 1.20mm 0.50mm 4.00mm 0.60mm 0.50mm 1.20mm 3.40mm 3.40mm 10070-005 For the best current sensing accuracy with the footprint shown in Figure 8, chip resistors without a nickel barrier layer (usually in green) are recommended. The data in this user guide may not be applicable to all resistors and results may vary depending on resistor composition and size. Test alternative resistors independently. It is the responsibility of the user to ensure that the layout dimensions and structure of the footprint comply with the individual SMT manufacturing requirements. Analog Devices does not accept responsibility for any issues that may arise because of using this footprint. Figure 9. Optimum Footprint Dimensions (Based on Welwyn ULR Green Resistor and Layout in Figure 8) Rev. B | Page 8 of 16 Evaluation Board User Guide UG-304 10070-012 EVALUATION BOARD LAB SETUP Figure 10. Board Lab Setup BOARD SPECIFICATIONS Table 7. Board Specifications Parameter UVL UVH OV Rising OV Falling Load Capacitance Trip Current (Nominal) Regulation Current (Nominal) Constant Power Level Rating 32.4 V 36 V 74.0 V 69.9 V 680 µF 9.56 A 10 A 155 W Rev. B | Page 9 of 16 UG-304 Evaluation Board User Guide 10070-016 Figure 11. Power-Up Profile; Channel 1 = VIN (Yellow); Channel 2 = VDS (Blue); Channel 3 = Gate (Pink); Channel 4 = System Current (Green); M1 = FET Power (CH2 × CH4) (Orange) Figure 14. Severe OC Event; Channel 1 = VIN (Yellow); Channel 2 = VDS (Blue); Channel 3 = Gate (Pink); Channel 4 = System Current (Green); M1 = FET Power (CH2 × CH4) (Orange) 10070-014 10070-017 10070-013 TEST PLOTS Figure 15. Short Circuit Event; Channel 1 = VIN (Yellow); Channel 2 = VDS (Blue); Channel 3 = Gate (Pink); Channel 4 = System Current (Green); M1 = FET Power (CH2 × CH4) (Orange) Figure 13. TIMER During a Fault; Channel 1 = VIN (Yellow); Channel 2 = VDS (Blue); Channel 3 = TIMER (Pink); Channel 4 = System Current (Green) 10070-018 10070-015 Figure 12. Power-Up into a Fault (TIMER); Channel 1 = VIN (Yellow); Channel 2 = VDS (Blue); Channel 3 = TIMER (Pink); Channel 4 = System Current (Green) Figure 16. Short-Circuit Event (Zoom); Channel 1 = VIN (Yellow); Channel 2 = VDS (Blue); Channel 3 = Gate (Pink); Channel 4 = System Current (Green) Rev. B | Page 10 of 16 Figure 17. Evaluation Board Schematic, Page 1 Rev. B | Page 11 of 16 GPO2 LATCH –48V NO POP R_7rty_10s NO POP SCL J4 ADC_IN SDAO SDAI SENSEN SENSEP GATE GPO2 GPO1 LATCH SPLYGD PWRGD RTN IN –48V SDA VEE 10 9 8 NO POP 0Ω Rsdai SDAO GPO2 GPO1 T49 SOURCE NO POP ADC_IN Raux1 Rsdao 0Ω 14 13 GPO2 SDAO 12 GPO1 Css RESTART SHDN ADR LATCH Ctimer RESTART 11 SHDN ADR LATCH Ctimer2 NO POP VEE Riset2 NO POP VEE VEE 470nF Csnb NO POP –48V OUT Raux_out –48V IN 0Ω Radr NO POP Radr2 RTN Rsnb NO POP NO POP D1 85V TVS –48V TERMINAL RESTART SHDN VCAP UVH UVL OV PLIM VCAP ADC_VIN ISET SS TIMER VEE SHDN_int T47 T46 T31 T30 T29 T25 T24 T23 T22 T21 T20 T19 T18 T17 T16 T15 T13 T11 T9 T7 T6 T5 T4 R_1rty_10s RESTART 0Ω R_7retry D_INPUT LED_GREEN R1 100kΩ J1 VEE T27 Riset1 0Ω VCAP U1 ADM1075 T28 10kΩ Raux2 -48V T50 VEE 1µF 16V Ccap VEE 0Ω VIN GATE VEE_G DRAIN VEE SENSEP R15 VEE VEE UVL UVH SENSEN NO POP Rsense3 R13 10Ω NO POP Rsense2 R11 10Ω 2mΩ 3W Rsense1 R8 10Ω NO POP R14 10Ω R12 10Ω R9 10Ω SENSEP 22 1.8MΩ GATE R7 –48V VEE Rdrain 1µF 25V Cvin Ruvl2 NO POP Rvin4 15kΩ 0.5W Rvin5 15kΩ 0.5W OUT DRAIN 4 3 2 1 0Ω Rgate 16kΩ C4 NO POP R3 NO POP VEE Q3 NO POP Q2 NO POP Q1 IPB072N15N3 G –48V Cuvl 100nF R4 10Ω T26 R5 10Ω R6 10Ω VEE Rplim2 1kΩ Rplim1 150kΩ VEE Cplim NO POP PLIM Rvin6 Rvin7 Rvin8 Rvin1 NO POP NO POP NO POP 15kΩ 0.5W T48 T12 T8 –48V T14 T10 5V_IN_P 8 SK2 7 6 5 4 3 2 1 SK1 R2 NO POP SCL SDA 8 7 6 Rvin3 15kΩ 0.5W –48V OUT 0Ω Rvin2 Cuvh 15kΩ 100nF 0.5W VIN J3 RTN OUT 5 Ruvh2 Ruvh1 560kΩ C1 680µF J2 Ruuv Ruvl1 NO POP T39 Rov1 825kΩ NO POP Rouv T3 23 24 25 26 VIN 27 UVH 28 UVL VEE Cov 100nF 50V Radc3 0Ω Cadc 100nF 50V Rov2 11.3kΩ –48V T2 VEE Radc1 NO POP T1 Radc2 NO POP VEE OV 1 1 1 7 TIMER TMR 15 SDAI SDAI 6 SS SS 5 ISET ISET 16 SCL PWRGD 17 PWRGD SCL 3 VCAP VCAP 4 ADC_VIN ADC_VIN ADC_AUX 18 SPLYGD SPLYGD 19 2 PLIM PLIM VEE 20 OV SENSEN 21 1 1 RTN Evaluation Board User Guide UG-304 EVALUATION BOARD SCHEMATICS AND ARTWORK 10070-006 Figure 18. Evaluation Board Schematic, Page 2 Rev. B | Page 12 of 16 2 SCL_TEMP 2 SCL_TEMP –48V 4 3 1 SDA_TEMP –48V 4 3 1 2 SDA_TEMP –48V 4 3 1 SCL_TEMP 0Ω R36 0Ω R33 SDA_TEMP SCL SDA GPO2 ADT75ARMZ GND OS/ALERT SCL SDA UT3 ADT75ARMZ GND OS/ALERT SCL SDA UT2 ADT75ARMZ GND OS/ALERT SCL SDA UT1 SCL_TEMP SDA_TEMP A2 A1 A0 VDD A2 A1 A0 VDD A2 A1 A0 VDD LATCH D_GPO2 LED_YEL LOW 8 –48V 5 6 7 8 –48V 5 6 7 8 –48V 5 6 7 2 1 2 1 D_LATCH LED_RED R20 3300Ω -48V –48V C18 1µF 25V 5V_board –48V C14 1µF 25V 5V_board –48V 4 3 4 3 2 1 R43 UVL 24LC64-I/MS Vss/GND A2 A1 A0 U2 10kΩ R53 5V_s 2 1 SDA SCL WP Vcc BAT54H 5 SDA 4 3 4 3 –48V –48V T45 SDA T44 –48V SCL NO POP R49 NO POP R48 –48V 3 2 1 J9 SHDN RESTART 5V_icp BAT54H D5 S_SHDN2A 5V_board C19 100nF 50V SHDN –48V 5V_IN_P –48V C5 1µF 25V 5V_aux Q7 NPN 100V R22 1kΩ 0.33w RTN C2 100nF 50V RESTART 5V_IN_P 1µF 25V C15 NO P OP R45 –48V 6 SCL 7 8 5V_board D3 5V_icp 4 3 4 3 NO P OP R40 –48V 0Ω R24 D2 DI ODE- Z_SOD- 123 R41 100kΩ RTN 5V_board S_SHDN NO P OP R47 0Ω R44 2 1 6V2 S_RST NO P OP R42 0Ω R39 2 1 2 1 5V_LED D_GPO1 LED_YELLOW R18 3300Ω 5V_aux NO POP –48V –48V 4 3 5V_aux R28 NO P OP 5V_L ED GPO1 C11 1µF 25V 5V_board S_DeLATCH R30 NO POP 5V_LED D_SPLYGD LED_GREEN R17 3300Ω 5V_L ED R27 NO P OP 5V_L ED SPLYGD D_PWRGD LED_GREEN R19 3300Ω 5V_L ED R29 NO P OP 5V_L ED PWRGD R21 NO P OP R16 3300Ω 5 5V_L ED 5 5 5V_LED 2 1 T38 GPO1 GPO2 –48V 5V_s 10kΩ R51 10kΩ GPO1 –48V –48V 9 –48V 0Ω –48V 5V_s NO POP C16 100nF 50V 13 16 15 14 12 11 10 SPLYGD R52 VDD2 VOA VOB GND2 U3 GND1 SCL1 SDA1 VDD1 U4 ADuM5404 VISO GNDISO VIA VIB VIC VID VSEL GNDISO U5 ADuM1250 4 3 2 1 –48V PWRGD LATCH SCL R54 C12 1µF 25V –48V –48V SDA 8 7 6 5 R58 NO POP VI N C3 ADuM3200 100nF 50V 5V_icp –48V C9 100nF 50V 5V_icp NO P OP R31 100kΩ R32 C6 1µF 25V R59 0Ω 5V_LED Q8 NPN 100V R23 1kΩ 0.33W RTN 100kΩ R56 NO POP 0Ω R38 R37 SDA SCL RESTART SHDN 2 1 J6 R50 2 1 –48V R25 0Ω 6V2 D6 NO POP R57 NO POP RTN TERMINAL BLOCK, PCB, 2WAY 5V_L ED GND_ISO GPOx_ISO LATCH_ISO SPLYGD_ISO PWRGD_ISO RST/GPO1_ISO VDD1 GND1 VOA VOB VOC VOD RCOUT 1 2 3 4 5 6 7 8 GND_ISO 5 50V GND_ISO C10 10µF 10V GND_ISO SPLYGD_ISO PWRGD_ISO J8 3 2 1 2 1 5 4 3 2 1 SOCKET, TOP ENTRY, 10WAY 5V_ISO T40 GND_ISO D_I SO L R10 1kΩ 5V_ISO T41 SDA_ISO SCL _ISO R34 3300Ω 5V_ISO USB_mini GND_ISO 9 8 7 6 J5 5V_ISO BAT54H D4 T43 GND_ISO GND_ISO 2 1 9 8 7 6 10 9 8 7 6 5 4 3 2 R35 3300Ω GND_ISO GND_ISO T42 J7 GND_ISO SDA_ISO 1 SK3 TERMINAL BLOCK, PCB, 2WAY R55 10kΩ C13 100nF 50V 5V_I SO GND_ISO GND_ISO 50V C7 100nF 5V_ISO GND_ISO GPOx_ISO R46 10kΩ 5V_ISO NO P OP R26 C8 100nF 5V_ISO LATCH_ISO 6 SCL_ISO 7 SDA_ISO 8 1 2 RST/GPO1_ISO 3 SHDN_ISO 4 GND1 GND2 SCL2 SDA2 VDD2 VDD1 VIA VIB GND1 T37 T36 T35 T34 T33 T32 SHDN_ISO T51 5V_ISO SCL_ISO ISOLATED AREA HEADER, RIGHT ANGLE, 1ROW, 3WAY 5V_L ED NO POP UG-304 Evaluation Board User Guide 10070-007 UG-304 10070-008 10070-010 Evaluation Board User Guide Figure 19. Top Layer Figure 20. Middle Layer 1 10070-011 10070-009 Figure 21. Middle Layer 2 Figure 22. Bottom Layer Rev. B | Page 13 of 16 UG-304 Evaluation Board User Guide ORDERING INFORMATION BILL OF MATERIALS Table 8. Reference Designator C1 Css Ctimer Q1 Q2 Q3 Q7, Q8 Riset1 Riset2 Ruvh1 Ruvh2 Rov1 Rov2 Ruvl1 Ruvl2 Ruuv R_1rty_10s R_7rty_10s R_7retry Rplim1 Rplim2 Rdrain Rsense1 Rsense2 Rsense3 C2, C3, C7, C8, C9, C13, C16, C19, Cadc, Cov C4, Cplim, Ctimer2 C5, C6, C11, C12, C14, C15, C18, Cvin C10 Ccap Csnb, Rsnb, Rvin6, Rvin7, Rvin8 Cuvh, Cuvl D1 D2 D3, D4, D5 D6 D_GPO1, D_GPO2 D_INPUT, D_PWRGD, D_SPLYGD D_ISO D_LATCH J1 J2 J3 J4 J5 J6, J8 J7 J9 R1 Description 680 µF, 100 V capacitor, CAPPR7.5-18 × 35.5 Not populated, 0603, capacitor 470 nF, 0603, capacitor IPB072N15N3 G, FET_mix4 Not populated, FET_mix4 Not populated, FET_mix4 NPN, 100 V, SOT-2-23 0 Ω, 0805, resistor Not populated, 0805, resistor 560 kΩ, 0805, resistor 16 kΩ, 0805, resistor 825 kΩ, 0805, resistor 11.3 kΩ, 0805, resistor Not populated, 0805, resistor Not populated, 0805, resistor 0 Ω, 0603, resistor Not populated, 0603, resistor Not populated, 0603, resistor 0 Ω, 0603, resistor 150 kΩ, 0805, resistor 1 kΩ, 0805, resistor 1.8 MΩ, 0805, resistor 2 mΩ, 3 W, Rsense_2512 Not populated, Rsense_2512 Not populated, Rsense_2512 100 nF, 50 V, 0603, capacitor Not populated, 0603, capacitor 1 µF, 25 V, 0805, capacitor 10 µF, 10 V, 0805, capacitor 1 µF, 16 V, 0805, capacitor Not populated, 1210 100 nF, 0603, capacitor 85 V TVS, DIO18.84-9.6 × 5.6 DIODE-Z_SOD-123 BAT54H, SOD-123 Not populated, SOD-123 Yellow LED, PLCC-2 Green LED, PLCC-2 Blue LED, 0805 Red LED, PLCC-2 RTN IN, TERMINAL-8191 RTN OUT, TERMINAL-8191 −48V OUT, TERMINAL-8191 −48V IN, TERMINAL-8191 USB_Mini, USB/SM0.8-6H5 Terminal block, PCB, 2-way Header, right angle, 1 row, 3-way Not populated, 3-pin header 100 kΩ, 1206, resistor Rev. B | Page 14 of 16 Farnell 9692657 Digi-Key 1828894 1700708 1570789 1652925 2139113 541-11.3KCDKR-ND 1500680 9333711 1576163 1292508 1692286 1637035 1833812 1288256 1692286 SMCJ85ABCT-ND 1757814 1757752 1328365 1226376 8529876 1328348 7691K-ND 7691K-ND 7691K-ND 7691K-ND 1125348 151789 9733450 1576656 Evaluation Board User Guide Reference Designator R2, R7, R26, R57, R58, Radc1, Radc2, Raux_out R3, R21, R27, R28, R29, R30, R31, R38, R40, R42 R43, R45, R47, R48, R49, R52, Radr2, Raux1, Rouv R4, R5, R6 R8, R9, R11, R12, R13, R14 R10 R15, R33, R36, R37, R39, R44, R54, Radr, Rsdai, Rsdao R16, R17, R18, R19, R20, R34, R35 R22, R23 R24, R25, R59, Radc3, Rgate, Riset1 R32, R56 R41 R46, R50, R51, R53, R55, Raux2 Rvin1, Rvin2, Rvin3, Rvin4, Rvin5 SK1, SK2 SK3 S_DeLATCH, S_RST, S_SHDN S_SHDN2 T1 to T51 U1 U2 U3 U4 U5 UT1, UT2, UT3 UG-304 Description Not populated, 0805, resistor Not populated, 0603, resistor Not populated, 0603, resistor 10 Ω, 0805, resistor 10 Ω, 0603, resistor 1 kΩ, 0805, resistor 0 Ω, 0603, resistor 33 kΩ, 0805, resistor 1 kΩ, 0.33 W, 1210 0 Ω, 0805, resistor 100 kΩ, 0603, resistor 100 kΩ, 0805, resistor 10 kΩ, 0603, resistor 15 kΩ, 0.5 W, 1210 8-way Micro-MaTch Socket, top entry, 10-way Micro-MaTch Switch push-button MCIPTG23K-V 3-pin switch SWITCH-DPST Test points, not populated ADM1075-1ACPZ, 28-lead LFCSP 24LC64-I/MS, MSOP-8 ADuM3200, dual-channel, digital isolator, enhanced system-level ESD reliability ADuM1250, hot swappable dual I2C isolator, 8-lead SOIC ADuM5404, quad-channel isolators with integrated dc-to-dc converter, 16-lead SOIC ADT75ARMZ, ±2°C accurate, 12-bit digital temperature sensor, 8-lead MSOP Rev. B | Page 15 of 16 Farnell 1469859 1469751 9333711 1469911, 1738911 1577394 1469649 1469860 1738918 1739028 148593 148600 1605470 1123875 1331335 Digi-Key UG-304 Evaluation Board User Guide NOTES ESD Caution ESD (electrostatic discharge) sensitive device. Charged devices and circuit boards can discharge without detection. Although this product features patented or proprietary protection circuitry, damage may occur on devices subjected to high energy ESD. Therefore, proper ESD precautions should be taken to avoid performance degradation or loss of functionality. Legal Terms and Conditions By using the evaluation board discussed herein (together with any tools, components documentation or support materials, the “Evaluation Board”), you are agreeing to be bound by the terms and conditions set forth below (“Agreement”) unless you have purchased the Evaluation Board, in which case the Analog Devices Standard Terms and Conditions of Sale shall govern. Do not use the Evaluation Board until you have read and agreed to the Agreement. Your use of the Evaluation Board shall signify your acceptance of the Agreement. This Agreement is made by and between you (“Customer”) and Analog Devices, Inc. (“ADI”), with its principal place of business at One Technology Way, Norwood, MA 02062, USA. Subject to the terms and conditions of the Agreement, ADI hereby grants to Customer a free, limited, personal, temporary, non-exclusive, non-sublicensable, non-transferable license to use the Evaluation Board FOR EVALUATION PURPOSES ONLY. Customer understands and agrees that the Evaluation Board is provided for the sole and exclusive purpose referenced above, and agrees not to use the Evaluation Board for any other purpose. Furthermore, the license granted is expressly made subject to the following additional limitations: Customer shall not (i) rent, lease, display, sell, transfer, assign, sublicense, or distribute the Evaluation Board; and (ii) permit any Third Party to access the Evaluation Board. As used herein, the term “Third Party” includes any entity other than ADI, Customer, their employees, affiliates and in-house consultants. The Evaluation Board is NOT sold to Customer; all rights not expressly granted herein, including ownership of the Evaluation Board, are reserved by ADI. CONFIDENTIALITY. This Agreement and the Evaluation Board shall all be considered the confidential and proprietary information of ADI. Customer may not disclose or transfer any portion of the Evaluation Board to any other party for any reason. Upon discontinuation of use of the Evaluation Board or termination of this Agreement, Customer agrees to promptly return the Evaluation Board to ADI. ADDITIONAL RESTRICTIONS. Customer may not disassemble, decompile or reverse engineer chips on the Evaluation Board. Customer shall inform ADI of any occurred damages or any modifications or alterations it makes to the Evaluation Board, including but not limited to soldering or any other activity that affects the material content of the Evaluation Board. Modifications to the Evaluation Board must comply with applicable law, including but not limited to the RoHS Directive. TERMINATION. ADI may terminate this Agreement at any time upon giving written notice to Customer. Customer agrees to return to ADI the Evaluation Board at that time. LIMITATION OF LIABILITY. THE EVALUATION BOARD PROVIDED HEREUNDER IS PROVIDED “AS IS” AND ADI MAKES NO WARRANTIES OR REPRESENTATIONS OF ANY KIND WITH RESPECT TO IT. ADI SPECIFICALLY DISCLAIMS ANY REPRESENTATIONS, ENDORSEMENTS, GUARANTEES, OR WARRANTIES, EXPRESS OR IMPLIED, RELATED TO THE EVALUATION BOARD INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTY OF MERCHANTABILITY, TITLE, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT OF INTELLECTUAL PROPERTY RIGHTS. IN NO EVENT WILL ADI AND ITS LICENSORS BE LIABLE FOR ANY INCIDENTAL, SPECIAL, INDIRECT, OR CONSEQUENTIAL DAMAGES RESULTING FROM CUSTOMER’S POSSESSION OR USE OF THE EVALUATION BOARD, INCLUDING BUT NOT LIMITED TO LOST PROFITS, DELAY COSTS, LABOR COSTS OR LOSS OF GOODWILL. ADI’S TOTAL LIABILITY FROM ANY AND ALL CAUSES SHALL BE LIMITED TO THE AMOUNT OF ONE HUNDRED US DOLLARS ($100.00). EXPORT. Customer agrees that it will not directly or indirectly export the Evaluation Board to another country, and that it will comply with all applicable United States federal laws and regulations relating to exports. GOVERNING LAW. This Agreement shall be governed by and construed in accordance with the substantive laws of the Commonwealth of Massachusetts (excluding conflict of law rules). Any legal action regarding this Agreement will be heard in the state or federal courts having jurisdiction in Suffolk County, Massachusetts, and Customer hereby submits to the personal jurisdiction and venue of such courts. The United Nations Convention on Contracts for the International Sale of Goods shall not apply to this Agreement and is expressly disclaimed. ©2011–2013 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. UG10070-0-4/13(B) Rev. B | Page 16 of 16
