a
FEATURES
1.8 V to 5.5 V Single Supply
2.5 V Dual Supply
2.5 On Resistance
0.5 On Resistance Flatness
100 pA Leakage Currents
19 ns Switching Times
Triple SPDT: ADG733
Quad SPDT: ADG734
Small TSSOP and QSOP Packages
Low Power Consumption
TTL/CMOS Compatible Inputs
CMOS, 2.5 Low Voltage,
Triple/Quad SPDT Switches
ADG733/ADG734
FUNCTIONAL BLOCK DIAGRAMS
ADG733
S1B
S1A
S4A
D2
D1
D1
S3A
S1A
S4B
S1B
D3
S3B
IN4
IN1
ADG734
S2A
D2
IN2
IN3
S2B
S3B
S2B
D2
LOGIC
S2A
APPLICATIONS
Data Acquisition Systems
Communication Systems
Relay Replacement
Audio and Video Switching
Battery Powered Systems
A0
A1 A2
D3
S3A
EN
SWITCHES SHOWN FOR A “1” INPUT LOGIC
GENERAL DESCRIPTION
PRODUCT HIGHLIGHTS
The ADG733 and ADG734 are low voltage, CMOS devices
comprising three independently selectable SPDT (single pole,
double throw) switches and four independently selectable SPDT
switches respectively.
1. Single/Dual Supply Operation. The ADG733 and ADG734 are
fully specified and guaranteed with 3 V and 5 V single supply
rails and ± 2.5 V dual supply rails.
Low power consumption and operating supply range of 1.8 V to
5.5 V and dual ± 2.5 V make the ADG733 and ADG734 ideal for
battery powered, portable instruments. All channels exhibit
break-before-make switching action preventing momentary
shorting when switching channels. An EN input on the ADG733 is
used to enable or disable the device. When disabled, all channels
are switched OFF.
2. Low On Resistance (2.5 Ω typical)
3. Low Power Consumption (<0.01 µW)
4. Guaranteed Break-Before-Make Switching Action
These 2–1 multiplexers/SPDT switches are designed on an
enhanced submicron process that provides low power dissipation
yet gives high switching speed, very low on resistance, high signal
bandwidths, and low leakage currents. On resistance is in the
region of a few ohms, is closely matched between switches, and is
very flat over the full signal range. These parts can operate equally
well in either direction and have an input signal range that extends
to the supplies.
The ADG733 is available in small TSSOP and QSOP packages,
while the ADG734 is available in a small TSSOP package.
REV. B
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties that
may result from its use. No license is granted by implication or otherwise
under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel:
781/329-4700
www.analog.com Fax: 781/326-8703
© Analog Devices, Inc., 2014
ADG733/ADG734–SPECIFICATIONS1 (V
B Version
–40C
+25C
to +85C
Parameter
ANALOG SWITCH
Analog Signal Range
On Resistance (RON)
0 V to VDD
2.5
4.5
On Resistance Match between
Channels (∆RON)
On Resistance Flatness (RFLAT(ON))
5.0
0.1
0.4
0.5
1.2
LEAKAGE CURRENTS
Source OFF Leakage IS (OFF)
Channel ON Leakage ID, IS (ON)
DIGITAL INPUTS
Input High Voltage, VINH
Input Low Voltage, VINL
Input Current
IINL or IINH
± 0.01
± 0.1
± 0.01
± 0.1
= 5 V 10%, VSS = 0 V, GND = 0 V, unless otherwise noted.)
Unit
V
Ω typ
Ω max
Ω typ
Ω max
Ω typ
Ω max
Test Conditions/Comments
VS = 0 V to VDD, IDS = 10 mA;
Test Circuit 1
VS = 0 V to VDD, IDS = 10 mA
VS = 0 V to VDD, IDS = 10 mA
VDD = 5.5 V
VD = 4.5 V/1 V, VS = 1 V/4.5 V;
Test Circuit 2
VD = VS = 1 V, or 4.5 V;
Test Circuit 3
± 0.5
nA typ
nA max
nA typ
nA max
2.4
0.8
V min
V max
± 0.1
µA typ
µA max
pF typ
VIN = VINL or VINH
RL = 300 Ω, CL = 35 pF;
VS = 3 V, Test Circuit 4
RL = 300 Ω, CL = 35 pF;
VS = 3 V, Test Circuit 4
RL = 300 Ω, CL = 35 pF;
VS = 3 V, Test Circuit 5
RL = 300 Ω, CL = 35 pF;
VS = 3 V, Test Circuit 5
RL = 300 Ω, CL = 35 pF;
VS = 3 V, Test Circuit 6
VS = 2 V, RS = 0 Ω, CL = 1 nF;
Test Circuit 7
RL = 50 Ω, CL = 5 pF, f = 1 MHz;
Test Circuit 8
RL = 50 Ω, CL = 5 pF, f = 1 MHz;
Test Circuit 9
RL = 50 Ω, CL = 5 pF, Test Circuit 10
f = 1 MHz
f = 1 MHz
± 0.3
0.005
CIN, Digital Input Capacitance
DD
4
2
DYNAMIC CHARACTERISTICS
tON
19
Break-Before-Make Time Delay, tD
13
Charge Injection
±3
ns typ
ns max
ns typ
ns max
ns typ
ns max
ns typ
ns max
ns typ
ns min
pC typ
Off Isolation
–72
dB typ
Channel-to-Channel Crosstalk
–67
dB typ
–3 dB Bandwidth
CS (OFF)
CD, CS (ON)
160
11
34
MHz typ
pF typ
pF typ
0.001
µA typ
µA max
34
tOFF
7
ADG733 tON(EN)
20
12
40
tOFF(EN)
7
12
1
POWER REQUIREMENTS
IDD
1.0
VDD = 5.5 V
Digital Inputs = 0 V or 5.5 V
NOTES
1
Temperature range is as follows: B Version: –40°C to +85°C.
2
Guaranteed by design, not subject to production test.
Specifications subject to change without notice.
–2–
REV. B
1 (VDD = 3 V 10%, VSS = 0 V, GND = 0 V, unless otherwise noted.)
SPECIFICATIONS
B Version
–40C
+25C
to +85C
Parameter
ANALOG SWITCH
Analog Signal Range
On Resistance (RON)
0 V to VDD
6
11
On Resistance Match between
Channels (∆RON)
On Resistance Flatness (RFLAT(ON))
LEAKAGE CURRENTS
Source OFF Leakage IS (OFF)
Channel ON Leakage ID, IS (ON)
DIGITAL INPUTS
Input High Voltage, VINH
Input Low Voltage, VINL
Input Current
IINL or IINH
± 0.01
± 0.1
± 0.01
± 0.1
12
0.1
0.4
3
V
Ω typ
Ω max
Ω typ
Ω max
Ω typ
Test Conditions/Comments
VS = 0 V to VDD, IDS = 10 mA;
Test Circuit 1
VS = 0 V to VDD, IDS = 10 mA
VS = 0 V to VDD, IDS = 10 mA
VDD = 3.3 V
VS = 3 V/1 V, VD = 1 V/3 V;
Test Circuit 2
VS = VD = 1 V or 3 V;
Test Circuit 3
± 0.5
nA typ
nA max
nA typ
nA max
2.0
0.8
V min
V max
± 0.1
µA typ
µA max
pF typ
VIN = VINL or VINH
RL = 300 Ω, CL = 35 pF;
VS = 2 V, Test Circuit 4
RL = 300 Ω, CL = 35 pF;
VS = 2 V, Test Circuit 4
RL = 300 Ω, CL = 35 pF;
VS = 2 V, Test Circuit 5
RL = 300 Ω, CL = 35 pF;
VS = 2 V, Test Circuit 5
RL = 300 Ω, CL = 35 pF;
VS = 2 V, Test Circuit 6
VS = 1 V, RS = 0 Ω, CL = 1 nF;
Test Circuit 7
RL = 50 Ω, CL = 5 pF, f = 1 MHz;
Test Circuit 8
RL = 50 Ω, CL = 5 pF, f = 1 MHz;
Test Circuit 9
RL = 50 Ω, CL = 5 pF, Test Circuit 10
f = 1 MHz
f = 1 MHz
± 0.3
0.005
CIN, Digital Input Capacitance
Unit
ADG733/ADG734
4
2
DYNAMIC CHARACTERISTICS
tON
28
Break-Before-Make Time Delay, tD
22
Charge Injection
±3
ns typ
ns max
ns typ
ns max
ns typ
ns max
ns typ
ns max
ns typ
ns min
pC typ
Off Isolation
–72
dB typ
Channel-to-Channel Crosstalk
–67
dB typ
–3 dB Bandwidth
CS (OFF)
CD, CS (ON)
160
11
34
MHz typ
pF typ
pF typ
0.001
µA typ
µA max
55
tOFF
9
ADG733 tON(EN)
29
16
60
tOFF(EN)
9
16
1
POWER REQUIREMENTS
IDD
1.0
NOTES
1
Temperature ranges are as follows: B Version: –40°C to +85°C.
2
Guaranteed by design, not subject to production test.
Specifications subject to change without notice.
REV. B
–3–
VDD = 3.3 V
Digital Inputs = 0 V or 3.3 V
ADG733/ADG734–SPECIFICATIONS1
DUAL SUPPLY
(VDD = +2.5 V 10%, VSS = –2.5 V 10%, GND = 0 V, unless otherwise noted.)
B Version
–40C
+25C
to +85C
Parameter
ANALOG SWITCH
Analog Signal Range
On Resistance (RON)
VSS to VDD
2.5
4.5
On Resistance Match between
Channels (∆RON)
On Resistance Flatness (RFLAT(ON))
5.0
0.1
0.4
0.5
1.2
LEAKAGE CURRENTS
Source OFF Leakage IS (OFF)
Channel ON Leakage ID, IS (ON)
DIGITAL INPUTS
Input High Voltage, VINH
Input Low Voltage, VINL
Input Current
IINL or IINH
± 0.01
± 0.1
± 0.01
± 0.1
V
Ω typ
Ω max
Ω typ
Ω max
Ω typ
Ω max
Test Conditions/Comments
VS = VSS to VDD, IDS = 10 mA;
Test Circuit 1
VS = VSS to VDD, IDS = 10 mA
VS = VSS to VDD, IDS = 10 mA
VDD = +2.75 V, VSS = –2.75 V
VS = +2.25 V/–1.25 V, VD = –1.25 V/+2.25 V;
Test Circuit 2
VS = VD = +2.25 V/–1.25 V, Test Circuit 3
± 0.5
nA typ
nA max
nA typ
nA max
1.7
0.7
V min
V max
± 0.1
µA typ
µA max
pF typ
VIN = VINL or VINH
RL = 300 Ω, CL = 35 pF;
VS = 1.5 V, Test Circuit 4
RL = 300 Ω, CL = 35 pF;
VS = 1.5 V, Test Circuit 4
RL = 300 Ω, CL = 35 pF;
VS = 1.5 V, Test Circuit 5
RL = 300 Ω, CL = 35 pF;
VS = 1.5 V, Test Circuit 5
RL = 300 Ω, CL = 35 pF;
VS = 1.5 V, Test Circuit 6
VS = 0 V, RS = 0 Ω, CL = 1 nF;
Test Circuit 7
RL = 50 Ω, CL = 5 pF, f = 1 MHz;
Test Circuit 8
RL = 50 Ω, CL = 5 pF, f = 1 MHz;
Test Circuit 9
RL = 50 Ω, CL = 5 pF, Test Circuit 10
f = 1 MHz
f = 1 MHz
± 0.3
0.005
CIN, Digital Input Capacitance
Unit
4
2
DYNAMIC CHARACTERISTICS
tON
21
Break-Before-Make Time Delay, tD
13
Charge Injection
±5
ns typ
ns max
ns typ
ns max
ns typ
ns max
ns typ
ns max
ns typ
ns min
pC typ
Off Isolation
–72
dB typ
Channel-to-Channel Crosstalk
–67
dB typ
–3 dB Bandwidth
CS (OFF)
CD, CS (ON)
200
11
34
MHz typ
pF typ
pF typ
0.001
µA typ
µA max
µA typ
µA max
35
tOFF
10
ADG733 tON(EN)
21
tOFF(EN)
10
16
40
16
1
POWER REQUIREMENTS
IDD
1.0
ISS
0.001
1.0
VDD = 2.75 V
Digital Inputs = 0 V or 2.75 V
VSS = –2.75 V
Digital Inputs = 0 V or 2.75 V
NOTES
1
Temperature range is as follows: B Version: –40°C to +85°C.
2
Guaranteed by design, not subject to production test.
Specifications subject to change without notice.
–4–
REV. B
ADG733/ADG734
ABSOLUTE MAXIMUM RATINGS 1
(TA = 25°C, unless otherwise noted.)
VDD to VSS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 V
VDD to GND . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +7 V
VSS to GND . . . . . . . . . . . . . . . . . . . . . . . . . . +0.3 V to –3.5 V
Analog Inputs2 . . . . . . . . . . . . . . VSS – 0.3 V to VDD + 0.3 V or
30 mA, Whichever Occurs First
Digital Inputs2 . . . . . . . . . . . . . . . . . –0.3 V to VDD + 0.3 V or
30 mA, Whichever Occurs First
Peak Current, S or D . . . . . . . . . . . . . . . . . . . . . . . . . . 100 mA
(Pulsed at 1 ms, 10% Duty Cycle max)
Continuous Current, S or D . . . . . . . . . . . . . . . . . . . . . 30 mA
Operating Temperature Range
Industrial (A, B Versions) . . . . . . . . . . . . . –40°C to +85°C
Storage Temperature Range . . . . . . . . . . . . –65°C to +150°C
Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . 150°C
16-Lead TSSOP, θJA Thermal Impedance . . . . . . . 150.4°C/W
20-Lead TSSOP, θJA Thermal Impedance . . . . . . . . . 143°C/W
16-Lead QSOP, θJA Thermal Impedance . . . . . . . 149.97°C/W
Lead Temperature, Soldering (10 sec) . . . . . . . . . . . . . 300°C
IR Reflow, Peak Temperature (<20 sec) . . . . . . . . . . . . 235°C
NOTES
1
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the
device at these or any other conditions above those listed in the operational
sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability. Only one absolute
maximum rating may be applied at any one time.
2
Overvoltages at A, EN, IN, S, or D will be clamped by internal diodes. Current
should be limited to the maximum ratings given.
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection.
Although the ADG733/ADG734 feature proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper
ESD precautions are recommended to avoid performance degradation or loss of functionality.
PIN CONFIGURATIONS
TSSOP/QSOP
TSSOP
IN1 1
20 IN4
S1A 2
19 S4A
S2B 1
16 VDD
S2A 2
15 D2
D1 3
S3B 3
14 D1
S1B 4
ADG733
TOP VIEW 13 S1B
(Not to Scale)
S3A 5
12 S1A
D3 4
18 D4
ADG734
17 S4B
TOP VIEW 16 VDD
(Not to Scale)
15 NC
GND 6
VSS 5
EN 6
11 A0
S2B 7
VSS 7
10 A1
D2 8
GND 8
9 A2
S2A 9
IN2 10
14 S3B
13 D3
12 S3A
11 IN3
NC = NO CONNECT
REV. B
–5–
ADG733/ADG734
Table II. ADG734 Truth Table
Table I. ADG733 Truth Table
A2
A1
A0
EN
ON Switch
Logic
Switch A
Switch B
X
0
0
0
0
1
1
1
1
X
0
0
1
1
0
0
1
1
X
0
1
0
1
0
1
0
1
1
0
0
0
0
0
0
0
0
None
D1-S1A, D2-S2A, D3-S3A
D1-S1B, D2-S2A, D3-S3A
D1-S1A, D2-S2B, D3-S3A
D1-S1B, D2-S2B, D3-S3A
D1-S1A, D2-S2A, D3-S3B
D1-S1B, D2-S2A, D3-S3B
D1-S1A, D2-S2B, D3-S3B
D1-S1B, D2-S2B, D3-S3B
0
1
OFF
ON
ON
OFF
X = Don’t Care.
TERMINOLOGY
VDD
VSS
IDD
ISS
GND
S
D
AX
EN
VD (VS)
RON
∆RON
RFLAT(ON)
IS (OFF)
ID, IS (ON)
VINL
VINH
IINL(IINH)
CS (OFF)
CD, CS(ON)
CIN
tON
tOFF
tON(EN)
tOFF(EN)
tOPEN
Charge
Off Isolation
Crosstalk
On Response
Insertion Loss
Most Positive Power Supply Potential
Most Negative Power Supply in a Dual Supply Application. In single supply applications, this should be tied to
ground close to the device.
Positive Supply Current
Negative Supply Current
Ground (0 V) Reference
Source Terminal. May be an input or output.
Drain Terminal. May be an input or output.
Logic Control Input
Active low device enable
Analog Voltage on Terminals D and S
Ohmic Resistance between D and S
On Resistance Match between any Two Channels (i.e., RONmax and RONmin)
Flatness is defined as the difference between the maximum and minimum value of on resistance as measured over
the specified analog signal range.
Source Leakage Current with the Switch “OFF”
Channel Leakage Current with the Switch “ON”
Maximum Input Voltage for Logic “0”
Minimum Input Voltage for Logic “1”
Input Current of the Digital Input
“OFF” Switch Source Capacitance. Measured with reference to ground.
“ON” Switch Capacitance. Measured with reference to ground.
Digital Input Capacitance
Delay Time Measured between the 50% and 90% Points of the Digital Inputs and the Switch “ON” Condition
Delay Time Measured between the 50% and 90% Points of the Digital Input and the Switch “OFF” Condition
Delay Time between the 50% and 90% Points of the EN Digital Input and the Switch “ON” Condition
Delay Time between the 50% and 90% Points of the EN Digital Input and the Switch “OFF” Condition
“OFF” Time Measured between the 80% Points of Both Switches when Switching from One Address State to
Another
A Measure of the Glitch Impulse Transferred Injection from the Digital Input to the Analog Output during Switching
A Measure of Unwanted Signal Coupling through an “OFF” Switch.
A Measure of Unwanted Signal that Is Coupled through from One Channel to Another as a Result of Parasitic Capacitance
The Frequency Response of the “ON” Switch
The Loss Due to the On Resistance of the switch
–6–
REV. B
Typical Performance Characteristics–ADG733/ADG734
8
8
5
VDD = 3.3V
VDD = 4.5V
4
3
7
7
6
6
ON RESISTANCE – VDD = 2.7V
6
ON RESISTANCE – ON RESISTANCE – 7
8
TA = 25C
TA = 25C
VSS = 0V
5
VDD = +2.5V
VSS = –2.5V
4
3
2
2
VDD = 5V
VSS = 0V
5
4
+25C
+85C
3
2
VDD = 5.5V
–40C
1
1
0
0
1
2
3
0
–3
5
4
1
–2
–1
0
1
0
3
2
VD, VS, DRAIN OR SOURCE VOLTAGE – V
VD, VS, DRAIN OR SOURCE VOLTAGE – V
TPC 1. On Resistance as a Function of
VD (VS) for Single Supply
7
4
0.1
VDD = +2.5V
VSS = –2.5V
7
VDD = 5V
VSS = GND
TA = 25C
+85C
5
4
–40C
3
+25C
2
6
CURRENT – nA
ON RESISTANCE – ON RESISTANCE – 0.05
6
5
4
+25C
+85C
3
0
0
–3
–1
0
1
2
–0.15
3
0
0.25
VDD = +2.5V
VSS = –2.5V
VD = +2.25V/–1.25V
VS = –1.25V/+2.25V
0.20
0.15
0
–0.02
–0.04
–0.06
CURRENT – nA
IS, ID (ON)
0.02
0.05
IS, ID (ON), VD = VS
0
–0.05
4
3
5
VDD = 5V
VSS = GND
VD = 4.5V/1.0V
VS = 1.0V/4.5V
0.10
IS, ID (ON)
0.05
0
IS (OFF)
IS (OFF)
2
TPC 6. Leakage Currents as a
Function of VD (VS)
VDD = +2.5V
VSS = –2.5V
TA = 25C
0.10
0.04
1
VS, (VD = VDD – VS) – V
0.15
CURRENT – nA
CURRENT – nA
–2
TPC 5. On Resistance as a Function of
VD (VS) for Different Temperatures,
Dual Supply
VDD = 3V
VSS = GND
TA = 25C
0.06
IS (OFF)
VD, VS, DRAIN OR SOURCE VOLTAGE – V
0.10
0.08
–0.05
–0.1
–40C
1
TPC 4. On Resistance as a Function of
VD (VS) for Different Temperatures,
Single Supply
IS, ID (ON)
0
2
1
1.0
1.5
2.0
2.5
3.0
0
0.5
VD OR VS – DRAIN OR SOURCE VOLTAGE – V
5
TPC 3. On Resistance as a Function of
VD (VS) for Different Temperatures,
Single Supply
8
VDD = 3V
VSS = 0V
3
2
VD, OR VS DRAIN OR SOURCE VOLTAGE – V
TPC 2. On Resistance as a Function of
VD (VS) for Dual Supply
8
1
0
–0.10
IS (OFF)
–0.05
–0.08
–0.10
0
0.5
1.0
1.5
2.0
2.5
VS, (VD = VDD – VS) – V
TPC 7. Leakage Currents as a
Function of VD (VS)
REV. B
3.0
–0.15
–3
–2
–1
0
1
2
VS, (VD = VDD –VS) – V
TPC 8. Leakage Currents as a
Function of VD (VS)
–7–
3
–0.10
5
20
35
50
65
TEMPERATURE – C
TPC 9. Leakage Currents as a
Function of Temperature
80
ADG733/ADG734
0.20
tON, VDD = 3V
0.05
IS, ID (ON)
0
–0.05
IS (OFF)
20
5
35
50
65
–2
30
0.10
–0.10
VSS = GND
35
TIME – ns
CURRENT – nA
0.15
0
40
VDD = 3V
VSS = GND
VD = 2.7V/1V
VS = 1V/2.7V
25
tON, VDD = 5V
20
15
10
tOFF, VDD = 3V
5
tOFF, VDD = 5V
0
80
–20
TEMPERATURE – C
0
20
–6
–8
–10
–12
–14
60
80
–16
10k
0
0
VDD = 5V
TA = 25C
TA = 25C
1m
1
VSS = 3V
VDD = GND
100n
10n
0.1
1
ATTENUATION – dB
ATTENUATION – dB
VDD = +2.5V
VSS = –2.5V
–40
–60
–80
10000
TPC 13. Input Current, IDD vs.
Switching Frequency
–120
30k
100M
VDD = 5V
TA = 25C
–40
–60
–80
–100
–100
10
100
1000
FREQUENCY – kHz
10M
1M
FREQUENCY – HZ
–20
–20
VDD = 5V
VSS = GND
100
100k
TPC 12. On Response vs. Frequency
TPC 11. tON /tOFF Times vs.
Temperature
10m
CURRENT – A
40
VDD = 5V
TA = 25C
–4
TEMPERATURE – C
TPC 10. Leakage Currents as a
Function of Temperature
10
ON RESPONSE – dB
0.25
100k
1M
10M
FREQUENCY – kHz
100M
TPC 14. Off Isolation vs. Frequency
–120
30k
100k
1M
10M
FREQUENCY – kHz
100M
TPC 15. Crosstalk vs. Frequency
30
VDD = +2.5V
VSS = –2.5V
TA = 25C
QINJ – pC
20
VDD = 3V
VSS = GND
10
0
VDD = 5V
VSS = GND
–10
–3
–2
–1
0
1
2
VOLTAGE – V
3
4
5
TPC 16. Charge Injection vs. Source
Voltage
–8–
REV. B
ADG733/ADG734
Test Circuits
IDS
V1
IS (OFF)
S
D
S
A
VS
D
S
NC
VS
D
ID (ON)
A
VD
VD
RON = V1/IDS
Test Circuit 3. ID (ON)
Test Circuit 2. IS (OFF)
Test Circuit 1. On Resistance
VDD
0.1F
VDD
ADDRESS
DRIVE
S1B
VS1B
S1A
VS1A
50%
50%
VOUT
D1
VS1A
CL
35pF
RL
300
IN/EN
90%
90%
VOUT
VS1B
tOFF
tON
VSS
GND
0.1F
VSS
Test Circuit 4. Switching Times, tON, tOFF
VDD
VSS
VDD
VSS
0.1F
3V
A2
S1A
A1
ENABLE
DRIVE (VIN)
VS
50%
0V
S1B
A0
50%
tOFF(EN)
ADG733
VO
EN
VIN
D1
50
RL
300
GND
CL
35pF
0.9V0
0.9V0
VO
OUTPUT
0V
tON(EN)
Test Circuit 5. Enable Delay, tON (EN), tOFF (EN)
VDD
0.1F
3V
VDD
ADDRESS
VIN
VS
SA
ADDRESS*
0V
SB
50
ADG733/
ADG734
VS
D1
GND
VSS
RL
300
CL
35pF
VOUT
VOUT
80%
80%
0.1F
tOPEN
VSS
*A0, A1, A2 FOR ADG733, IN1-4 FOR ADG734
Test Circuit 6. Break-Before-Make Delay, tOPEN
REV. B
–9–
ADG733/ADG734
VDD
VSS
VDD
VSS
3V
LOGIC
INPUT (VIN)
ADG733/
ADG734
0V
RS
D
S
CL
1nF
EN*
VS
VOUT
VOUT
QINJ = CL VOUT
GND
VIN
VOUT
* IN1–4 FOR ADG734
Test Circuit 7. Charge Injection
VDD
VDD
VSS
0.1F
0.1F
NETWORK
ANALYZER
VSS
VDD
S
0.1F
VDD
VSS
S
50
50
IN
VSS
0.1F
NETWORK
ANALYZER
50
IN
VS
VS
D
D
VIN
RL
50
GND
VOUT
VIN
GND
OFF ISOLATION = 20 LOG
VOUT
INSERTION LOSS = 20 LOG
VS
RL
50
VOUT
VOUT WITH SWITCH
VOUT WITHOUT SWITCH
Test Circuit 8. Off Isolation
Test Circuit 10. Bandwidth
VDD
VSS
0.1F
NETWORK
ANALYZER
VOUT
0.1F
VSS
VDD
SA
RL
50
D
SB
50
R
50
IN
VS
GND
CHANNEL-TO-CHANNEL
VOUT
CROSSTALK = 20 LOG
VS
Test Circuit 9. Channel-to-Channel Crosstalk
–10–
REV. B
Data Sheet
ADG733/ADG734
OUTLINE DIMENSIONS
0.197 (5.00)
0.193 (4.90)
0.189 (4.80)
16
9
1
0.158 (4.01)
0.154 (3.91)
0.150 (3.81)
8
0.010 (0.25)
0.006 (0.15)
0.069 (1.75)
0.053 (1.35)
0.065 (1.65)
0.049 (1.25)
0.010 (0.25)
0.004 (0.10)
COPLANARITY
0.004 (0.10)
0.244 (6.20)
0.236 (5.99)
0.228 (5.79)
0.025 (0.64)
BSC
SEATING
PLANE
0.012 (0.30)
0.008 (0.20)
8°
0°
0.020 (0.51)
0.010 (0.25)
0.041 (1.04)
REF
0.050 (1.27)
0.016 (0.41)
01-28-2008-A
COMPLIANT TO JEDEC STANDARDS MO-137-AB
CONTROLLING DIMENSIONS ARE IN INCHES; MILLIMETER DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF INCH EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN.
Figure 11. 16-Lead Shrink Small Outline Package [QSOP]
(RQ-16)
Dimensions shown in inches and (millimeters)
5.10
5.00
4.90
16
9
4.50
4.40
4.30
6.40
BSC
1
8
PIN 1
1.20
MAX
0.15
0.05
0.20
0.09
0.65
BSC
0.30
0.19
COPLANARITY
0.10
SEATING
PLANE
8°
0°
COMPLIANT TO JEDEC STANDARDS MO-153-AB
Figure 12. 16-Lead Thin Shrink Small Outline Package [TSSOP]
(RU-16)
Dimensions shown in millimeters
REV. B
--11--
0.75
0.60
0.45
ADG733/ADG734
Data Sheet
6.60
6.50
6.40
20
11
4.50
4.40
4.30
6.40 BSC
1
10
PIN 1
0.65
BSC
1.20 MAX
0.15
0.05
COPLANARITY
0.10
0.30
0.19
0.20
0.09
SEATING
PLANE
8°
0°
0.75
0.60
0.45
COMPLIANT TO JEDEC STANDARDS MO-153-AC
Figure 13. 20-Lead Thin Shrink Small Outline Package [TSSOP]
(RU-20)
Dimensions shown in millimeters
ORDERING GUIDE
Model1
ADG733BRQZ
ADG733BRQZ-REEL
ADG733BRU-REEL7
ADG733BRUZ
ADG733BRUZ-REEL
ADG733BRUZ-REEL7
ADG734BRU
ADG734BRU-REEL
ADG734BRUZ
ADG734BRUZ-REEL
ADG734BRUZ-REEL7
1
Temperature Range
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
Package Description
16-Lead Shrink Small Outline Package [QSOP]
16-Lead Shrink Small Outline Package [QSOP]
16-Lead Thin Shrink Small Outline Package [TSSOP]
16-Lead Thin Shrink Small Outline Package [TSSOP]
16-Lead Thin Shrink Small Outline Package [TSSOP]
16-Lead Thin Shrink Small Outline Package [TSSOP]
20-Lead Thin Shrink Small Outline Package [TSSOP]
20-Lead Thin Shrink Small Outline Package [TSSOP]
20-Lead Thin Shrink Small Outline Package [TSSOP]
20-Lead Thin Shrink Small Outline Package [TSSOP]
20-Lead Thin Shrink Small Outline Package [TSSOP]
Package Option
RQ-16
RQ-16
RU-16
RU-16
RU-16
RU-16
RU-20
RU-20
RU-20
RU-20
RU-20
Z = RoHS Compliant Part.
REVISION HISTORY
4/14—Rev. A to Rev. B
Updated Outline Dimensions ....................................................... 11
Changes to Ordering Guide .......................................................... 12
11/02—Data Sheet changed from REV. 0 to REV. A.
Changes to FEATURES ................................................................... 1
Changes to PRODUCT HIGHLIGHTS ........................................ 1
Changes to SPECIFICATIONS ...................................................... 2
Changes to ABSOLUTE MAXIMUM RATINGS Note 2 ........... 5
Changes to TERMINOLOGY table ............................................... 6
Replaced TPCs 2, 5, 8, and 9 ........................................................... 7
Edits to TPCs 6 and 7 ....................................................................... 7
Replaced TPC 12............................................................................... 8
Edits to TPCs 13 and 16................................................................... 8
Replaced Test Circuits 8 and 9 ...................................................... 10
Added Test Circuit 10 .................................................................... 10
Updated OUTLINE DIMENSIONS ............................................ 11
©2014 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D01602-0-4/14(B)
--12--
REV. B