P1.0 / ADC0 / T2
1
P1.1 / ADC1 / T2EX
direct
8bit internal address (00h-FFh)
3
2
P1.2 / ADC2
@Ri
indirect addressing using R0 or R1
4
3
P1.3 / ADC3
source
any of [Rn, direct, @Ri]
5
4,5
dest
any of [Rn, direct, @Ri]
#data
8bit constant included in instruction
6 6,7,8 AGND
12
bit
8bit direct address of bit
8
10
VREF
1,2
12
rel
signed 8bit offset
9
11
DAC0
DPTR *
1
24
addr11
11bit address in current 2K page
10
12
DAC1
DEC
A
1
12
addr16
16bit address
11
13
P1.4 / ADC4
DEC
source
1,2
12
12
14
P1.5 / ADC5 / SS
MUL
AB
multiply A by B
1
48
13
15
P1.6 / ADC6
DIV
AB
divide A by B
1
48
14
16
P1.7 / ADC7
27
29
SDATA / MOSI
40
43
EA
DA
A
decimal adjust
1
12
12
direct,A
MOV
dest,#data
ORL
direct,#data
XRL
A,source
2,3 12,24
MOV DPTR,#data16
3
24
MOVC A,@A+DPTR move from
code memory
MOVC A,@A+PC
1
24
XRL
A,#data
1
24
XRL
direct,A
MOVX A,@Ri
1
24
XRL
direct,#data
MOVX A,@DPTR
MOVX @Ri,A
move to/from
data memory
MOVX @DPTR,A
logical OR
logical XOR
43
46
P0.0 / AD0
1,2
12
18
20
P3.2 / INT0
31
33
P2.3 / A11 / A19
44
47
P0.1 / AD1
2
12
19
21
P3.3/INT1/MISO/PWM1
32
34
XTAL1 (in)
45
48
P0.2 / AD2
2
12
20
22
DVDD
33
35
XTAL2 (out)
46
49
P0.3 / AD3
3
24
21
23
DGND
34
36
DVDD
47
50
DGND
1,2
12
22
24
P3.4 / T0 / PWMC /
PWM0 / EXTCLK
35 37,38 DGND
48
51
DVDD
25
P3.5 / T1 / CONVST
36
P2.4 / A12 / A20
49
52
P0.4 / AD4
12
23
2
12
24
26
P3.6 / WR
37
40
P2.5 / A13 / A21
50
53
P0.5 / AD5
3
24
25
27
P3.7 / RD
38
41
P2.6/A14/A22/PWM0
51
54
P0.6 / AD6
26
28
SCLOCK
39
42
P2.7/A15/A23/PWM1
52
55
P0.7 / AD7
2
1
24
CLR
A
clear A to zero
1
12
24
CPL
A
complement A
1
12
1
24
RL
A
rotate A left
1
12
2
24
RLC
A
...through C
1
12
pop from stack
2
24
RR
A
rotate A right
1
12
XCH
A,source
exchange bytes 1,2
12
RRC
A
...through C
1
12
exchg low digits
12
SWAP A
swap nibbles
1
12
Boolean Variable Manipulation
2
24
CLR
C
3
24
CLR
bit
RET
return from sub.
1
24
SETB C
RETI
return from int.
1
24
SETB bit
AJMP addr11
LJMP addr16
SJMP rel
jump
clear bit to zero
set bit to one
1
12
1
12
2
12
1
12
2
12
2
24
CPL
C
3
24
CPL
bit
2
24
ANL
C,bit
AND bit with C
2
24
1
24
ANL
C,/bit
...NOTbit with C
2
24
C,bit
OR bit with C
2
24
...NOTbit with C
2
24
2
12
complement bit
@A+DPTR
JZ
rel
jump if A = 0
2
24
ORL
JNZ
rel
jump if A not 0
2
24
ORL
C,/bit
3
24
MOV
C,bit
3
24
MOV
bit,C
2
24
3
24
JC
rel
jump if C set
2
24
2
24
JNC
rel
jmp if C not set
2
24
CJNE A,#data,rel
CJNE Rn,#data,rel
compare and
jump if not
equal
CJNE @Ri,#data,rel
DJNZ Rn,rel
DJNZ direct, rel
NOP
decrement and
jump if not zero
no operation
2
24
JB
bit,rel
3
24
JNB
1
12
JBC
move bit to bit
jump if bit set
3
24
bit,rel
jmp if bit not set
3
24
bit, rel
jmp&clear if set
3
24
ASSEMBLER DIRECTIVES
EQU
DATA
IDATA
XDATA
BIT
CODE
DS
DBIT
DB
define symbol
define internal memory symbol
define indirect addressing symbol
define external memory symbol
define internal bit memory symbol
define program memory symbol
reserve bytes of data memory
reserve bits of bit memory
store byte values in program memory
BIG MEMORY
BIG MEMORY
DW
ORG
END
CSEG
XSEG
DSEG
ISEG
BSEG
store word values in program memory
set segment location counter
end of assembly source file
select program memory space
select external data memory space
select internal data memory space
select indirectly addressed internal
data memory space
select bit addressable memory space
BIG MEMORY
12bit, 5µs, 8channel, self calibrating
0.5LSB INL & 70dB SNR
DAC:
dual, 12bit, 15µs, voltage output
1LSB DNL
Flash/EEPROM:
62K bytes Flash/EE program memory
4K bytes Flash/EE data memory
microcontroller:
industry standard 8052
32 I/O lines, programmable PLL clock
(131KHz to 16.8MHz from 32KHz crystal)
FFFFh
(NOP instructions)
FUNCTIONAL BLOCK DIAGRAM
* pin numbers below refer to MQFP package
12
2
JMP
CJNE A,direct,rel
CODE MEMORY SPACE
FFFFh
F800h
F7FFh
ADC:
other on-chip features: temperature sensor, power supply monitor,
watchdog timer, flexible serial interface ports,
voltage reference, time interval counter,
dual 8/16bit PWM, power-on-reset
by
te
s
O
S
pe C
rio
d
by
te
s
O
S
pe C
rio
d
s
LCALL addr16
call subroutine
39
the ADuC832 is:
s
push onto stack
direct
ACALL addr11
SP
P2.2 / A10 / A18
POP
Program Branching
C
32
1
1
FP
30
PUSH direct
XCHD A,@Ri
Q
P3.1 / TxD
BIG MEMORY
EA=1
EA=0
internal
code space
external
code space
62K bytes
Flash/EE
(64K
addressable)
0000h
0000h
INTERRUPT VECTOR ADDRESSES
Interrupt
Bit
PSMCON.5
WDS
IE0
ADCI
TF0
IE1
TF1
ISPI/I2CI
RI/TI
TF2/EXF2
TIMECON.2
BIG MEMORY
23
ADC0
ADC1
ADC2
ADC3
ADC4
ADC5
ADC6
ADC7
1
2
3
4
11
12
13
14
Power Supply Monitor Interrupt
WatchDog Timer Interrupt
External Interrupt 0
End of ADC Conversion Interrupt
Timer0 Overflow Interrupt
External Interrupt 1
Timer1 Overflow Interrupt
SPI/I2C Interrupt
UART Interrupt
Timer2 Interrupt
Time Interval Counter Interrupt
43h
5Bh
03h
33h
0Bh
13h
1Bh
3Bh
23h
2Bh
53h
BIG MEMORY
ADuC832
ADC
control
&
calibration
12bit ADC
T/H
AIN
MUX
DAC0
BUF
9
DAC0
DAC1
BUF
10
DAC1
38
PWM0
DAC
control
PWM
TEMP
sensor
Vector Priority
within
Address Level
Interrupt Name
BIG MEMORY
hardware
CONVST
1
2
3
4
5
6
7
8
9
10
11
4K x 8
data
(-3 mV/oC)
2K x 8
user “XRAM”
Flash/EE
62K x 8
program
2.5V
bandgap
reference
8052
Flash/EE
MCU
core
baudrate timer
BIG MEMORY
VREF
8
CREF
7
asynchronous
serial port
(UART)
POR
www.analog.com/microconverter
BIG MEMORY
watchdog
timer
power supply
monitor
downloader
debugger
BUF
256 x 8
user RAM
synchronous
serial interface
(SPI or I2C)
16bit
counter
timers
time
interval
counter
BIG MEMORY
BIG MEMORY
39
PWM1
22
T0
23
T1
1
T2
2
T2EX
18
INT0
19
INT1
OSC &
PLL
33
ORL
19
32
1,2,3 24
17
XTAL2
dest,source
24
XTAL1
MOV
ALE
3
P3.0 (RxD)
P3.1 (TxD)
P3.2 (INT0)
P3.3 (INT1 / MISO / PWM1)
P3.4 (T0/PWMC/PWM0/EXTCLK)
P3.5 (T1 / CONVST)
P3.6 (WR)
P3.7 (RD)
A,#data
PSEN
45
16
17
18
19
22
23
24
25
A,source
ORL
44
42
12
ORL
12
41
P2.1 / A9 / A17
SS
12
1,2
move source
to destination
P2.0 / A8 / A16
31
26
27
19
2
dest,A
30
29
SCLOCK
SDATA / MOSI
MISO
A,#data
MOV
28
P3.0 / RxD
P2.0 (A8 / A16)
P2.1 (A9 / A17)
P2.2 (A10 / A18)
P2.3 (A11 / A19)
P2.4 (A12 / A20)
P2.5 (A13 / A21)
P2.6 (A14 / A22 / PWM0)
P2.7 (A15 / A23 / PWM1)
MOV
RESET
18
28
29
30
31
36
37
38
39
direct,#data
17
16
single-pin
emulator
ANL
15
42
41
40
12
12
12
ALE
PSEN
EA
1,2
2
2
17
A,source
a “Data Acquisition System on a Chip”
16
MOV
logical AND
M
direct,A
FP
A,#data
ANL
Q
ANL
Data Transfer Operations
SP
1,2
M
A,source
C
ANL
by
te
s
O
S
pe C
rio
d
Logical Operations
by
te
s
O
S
pe C
rio
d
s
* INC DPTR increments the 24bit value DPP/DPH/DPL
s
decrement
14
15
16
17
18
19
20
21
22
23
24
25
26
INC
MicroConverter®
Quick Reference Guide
TxD
increment
1
ADuC832
52pin MQFP
TOP VIEW
(not to scale)
RxD
source
#data16 16bit constant included in instruction
CREF
P1.0 (ADC0 / T2)
P1.1 (ADC1 / T2EX)
P1.2 (ADC2)
P1.3 (ADC3)
P1.4 (ADC4)
P1.5 (ADC5 / SS)
P1.6 (ADC6)
P1.7 (ADC7)
INC
12
9
56pin CSP
TOP VIEW
(not to scale)
1
2
3
4
11
12
13
14
A
7
AVDD
39
38
37
36
35
34
33
32
31
30
29
28
27
15
INC
12
12
pin 1 identifier
1
2
3
4
5
6
7
8
9
10
11
12
13
RESET
SUBB A,#data
2
subtract from A 1,2
with borrow
2
42
41
40
39
38
37
36
35
34
33
32
31
30
29
pin 1 identifier
ADuC832
21
35
47
SUBB A,source
1
2
3
4
5
6
7
8
9
10
11
12
13
14
PRINTED IN U.S.A.
ADDC A,#data
add with carry
DGND
12
BIG MEMORY
P0.0 (AD0)
P0.1 (AD1)
P0.2 (AD2)
P0.3 (AD3)
P0.4 (AD4)
P0.5 (AD5)
P0.6 (AD6)
P0.7 (AD7)
12
DVDD
2
1,2
ADDC A,source
BIG MEMORY
ADuC832
6
A,#data
BIG MEMORY
20
34
48
ADD
Legend
5
Rn
AVDD
12
BIG MEMORY
AGND
1,2
15
16
17
18
19
20
21
22
23
24
25
26
27
28
A,source
BIG MEMORY
52
51
50
49
48
47
46
45
44
43
42
41
40
56
2
by
te
s
O
S
pe C
rio
d
1
ADD
BIG MEMORY
PIN FUNCTIONS
register addressing using R0-R7
Arithmetic Operations
add source to A
BIG MEMORY
43
44
45
46
49
50
51
52
s
M
Q
FP
INSTRUCTION SET
BIG MEMORY
G03203-2.5-9/02 (0)
BIG MEMORY
56
55
54
53
52
51
50
49
48
47
46
45
44
43
BIG MEMORY
SP
BIG MEMORY
C
BIG MEMORY
REV. 0
BIG MEMORY
BIG MEMORY
BIG MEMORY
DATA MEMORY:
BIG MEMORY
BIG MEMORY
BIG MEMORY
BIG MEMORY
BIG MEMORY
BIG MEMORY
ADCCON1
RAM, SFRs, user Flash/EE (all read/write)
lower RAM
details
(reserved)
PCON
(reserved)
(reserved)
87h
(reserved)
00h
DPP
00h 84h
DPH
00h 83h
DPL
07h 82h
SP
FFh 81h
P0
80h
TH1
00h 8Dh
TH0
00h 8Ch
TL1
TL0
00h 8Ah
00h 89h
TCON
90h
88h
FFh
TMOD
00h 8Bh
00h 9Eh
00h
(not used)
(not used)
(not used)
9Dh
(not used)
55h
(not used)
00h 9Bh
(not used)
00h 9Ah
(not used)
00h 99h
P1
98h
00h A7h
00h A6h
00h
(not used)
T3CON
T3FD
00h A5h
00h AFh
AEh
00h
DPCON
INTVAL
HOUR
00h
CFG832
PWMCON
(reserved)
B7h
00h BFh
00h BEh
00h
SPH
(not used)
(not used)
00h
00h BDh
00h
EDATA4
EDATA3
EDATA2
00h C7h
C6h
00h
00h CDh
TH2
00h
00h
EADRH
EADRL
(reserved)
D7h
00h
(reserved)
(reserved)
53h
PLLCON
(reserved)
(reserved)
DEh
PSMCON
DFh
00h
EFh
F7h
00h
(reserved)
04h F9h
SFR details
SPR1
F9h
0
SPR0
F8h
0
SPICON
F8h
04h
1
83h
1
84h
1
85h
1
86h
1
ADC Control register #1
ADC Control register #2
ADC interrupt flag
DMA mode enable
continuous conversion enable bit
single conversion start bit
input channel select bits:
0 - 7 = ADC0 - ADC7
8 = temperature sensor
9=DAC0, A=DAC1, B=AGND
ADCCON3
ADCCON3.7
ADCCON3.6
ADCCON3.5
ADCCON3.4
ADCCON3.3
ADCCON3.2
ADCCON3.1
ADCCON3.0
ADC Control register #3
ADCDATAL
DMAP,DMAH,DMAL
DMA address pointer
ADCGAINH
ADCGAINL
ADC Gain
calibration coefficients
ADCOFSH
ADCOFSL
ADC Offset
calibration coefficients
DACCON
DAC Control register
DACCON.7
DACCON.6
DACCON.5
DACCON.4
DACCON.3
DACCON.2
DACCON.1
DACCON.0
ModeSelect (0=12bit, 1=8bit)
DAC1 RangeSelect (0=VREF, 1=VDD)
DAC0 RangeSelect (0=VREF, 1=VDD)
Clear DAC1 (0=0V, 1=normal operation)
Clear DAC0 (0=0V, 1=normal operation)
SynchronousUpdate (1=asynchronous)
PowerDown DAC1 (0=off, 1=on)
PowerDown DAC0 (0=off, 1=on)
DAC1H,DAC1L
DAC1 data registers
DAC0H,DAC0L
DAC0 data registers
PLLCON
PLL Control register
PLLCON.7
PLLCON.6
PLLCON.5
PLLCON.4
PLLCON.3
PLLCON.2
PLLCON.1
PLLCON.0
oscillator powerdown control bit (0=XTAL on)
PLL lock indicator flag (0=out of lock)
(this bit must contain zero)
(this bit must contain zero)
“fast interrupt” control bit (0=normal)
3-bit clock divider value, “CD” (default=3):
CD
fCORE = 16,777,216Hz / 2
TIMECON Time Interval Counter Control Register
TIMECON.6
TIMECON.5
TIMECON.4
TIMECON.3
TIMECON.2
TIMECON.1
TIMECON.0
(this bit must contain 1)
INTVAL timebase select bits
[128th sec, seconds, minutes, hours]
single time interval control bit (0=reload&restart)
time interval interrupt bit, “TII”
time interval enable bit (0=disable&clear)
time clock enable bit (0=disable)
INTVAL
TIC Interval Register
HTHSEC TIC Elapsed 128th Second Register
SEC
TIC Elapsed Seconds Register
MIN
TIC Elapsed Minutes Register
HOUR
TIC Elapsed Hours Register
ECON
Data Flash/EE comand register
01h
02h
04h
05h
06h
READ page
PROGRAM page
VERIFY page
ERASE page
ERASE ALL
82h PROGRAM byte
0Fh EXIT ULOAD mode
F0h ENTER ULOAD mode
(all others reserved)
87h
* calibration coefficients are preconfigured at power-up to factory calibrated values
BIG MEMORY
BIG MEMORY
BIG MEMORY
BIG MEMORY
BIG MEMORY
BIG MEMORY
Watchdog Timer control register
watchdog timeout selection bits
0-7=[15.6,31.2,62.5,125,250,500,1000,2000]ms
8=0ms (immediate reset)
>8=reserved
watchdog interrupt response bit
watchdog status flag (1 indicates watchdog timeout)
watchdog enable control (0=disabled)
watchdog write enable bit (set to enable write)
PSMCON
PSMCON.6
PSMCON.5
PSMCON.4
PSMCON.3
PSMCON.2
PSMCON.1
PSMCON.0
Power Supply Monitor control register
PSM status bit (1=normal / 0=fault)
PSM interrupt bit
trip point select bits
[4.37V, 3.08V, 2.93V, 2.63V]
(this bit must contain zero)
(reserved)
PSM powerdown control (1=on / 0=off)
SP
Stack Pointer
Stack Pointer High byte
IE
Interrupt Enable register #1
EA
EADC
ET2
ES
ET1
EX1
ET0
EX0
enable inturrupts (0=all inturrupts disabled)
enable ADCI (ADC interrupt)
enable TF2/EXF2 (Timer2 overflow interrupt)
enable RI/TI (serial port interrupt)
enable TF1 (Timer1 overflow interrupt)
enable IE1 (external interrupt 1)
enable TF0 (Timer0 overflow interrupt)
enable IE0 (external interrupt 0)
IEIP2 Interrupt Enable/Priority register #2
IEIP2.6
IEIP2.5
IEIP2.4
IEIP2.3
IEIP2.2
IEIP2.1
IEIP2.0
priority of TII interrupt (time interval)
priority of PSMI interrupt (power supply monitor)
priority of ISPI interrupt (serial interface)
(this bit must contain zero)
enable TII interrupt (time interval)
enable PSMI (power supply monitor interrupt)
enable ISPI interrupt (serial interface)
IP
Interrupt Priority register
PSI
PADC
PT2
PS
PT1
PX1
PT0
PX0
priority
priority
priority
priority
priority
priority
priority
priority
TMOD
of ISPI/I2CI (serial interface interrupt)
of ADCI (ADC interrupt)
of TF2/EXF2 (Timer2 overflow interrupt)
of RI/TI (serial port interrupt)
of TF1 (Timer1 overflow interrupt)
of IE1 (external interrupt 1)
of TF0 (Timer0 overflow interrupt)
of IE0 (external interrupt 0)
Timer Mode register
TMOD.3/.7
gate control bit (0=ignore INTx)
TMOD.2/.6
counter/timer select bit (0=timer)
TMOD.1/.5
timer mode selecton bits
TMOD.0/.4
[13bitT, 16bitT/C, 8bitT/Creload, 2x8bitT]
(upper nibble = Timer1, lower nibble = Timer0)
TCON
TF1
TR1
TF0
TR0
IE1
IT1
IE0
IT0
Timer Control register
Timer1 overflow flag (auto cleared on vector
Timer1 run control (0=off, 1=run)
Timer0 overflow flag (auto cleared on vector
Timer0 run control (0=off, 1=run)
external INT1 flag (auto cleared on vector to
IE1 type (0=level trig, 1=edge trig)
external INT0 flag (auto cleared on vector to
IE0 type (0=level trig, 1=edge trig)
TH0,TL0
Timer0 registers
TH1,TL1
Timer1 registers
T2CON
Timer2 Control register
TF2
EXF2
RCLK
TCLK
EXEN2
TR2
CNT2
CAP2
to ISR)
to ISR)
ISR)
ISR)
overflow flag
external flag
receive clock enable (0=Timer1 used for RxD clk)
transmit clock enable (0=Timer1 used for TxD clk)
external enable (0=ignore T2EX, 1=cap/rld on T2EX)
run control (0=stop, 1=run)
timer/counter select (0=timer, 1=counter)
capture/reload select (0=reload, 1=capture)
TH2,TL2
RCAP2H,RCAP2L Timer2 Reload/Capture
Data Flash/EE data registers
SPICON
ISPI
WCOL
SPE
SPIM
CPOL
CPHA
SPR1
SPR0
SPI Control register
SPI inturrupt (set at end of SPI transfer)
write collision error flag
SPI enable (0=I2C enable, 1=SPI enable)
master mode select (0=slave)
clock polarity select (0=SCLK idles low)
clock phase select (0=leading edge latch)
SPI bitrate select bits
bitrate = Fcore / [2,4,8,16] (slave: SPR0=SS)
SPI Data register
I2CCON I2C Control register
MDO
MDE
MCO
MDI
I2CM
I2CRS
I2CTX
I2CI
master mode SDATA output bit
master mode SDATA output enable (0=disable)
master mode SCLK output bit
master mode SDATA input bit
master mode select bit (0=slave mode)
serial port reset
transmission direction status (0=RX,1=TX)
serial interface interrupt
I2CADD I2C Address register
I2C Data register
PWMCON PWM Control register
PWMCON.6 PWM mode bits [0=disabled, 1=single/var.res.,
PWMCON.5
2=twin/8bit, 3=twin/16bit, 4=dual/16bitNRZ,
PWMCON.4
5=dual/8bit, 6=dual/16bitRZ, 7=(reserved)]
PWMCON.3 PWM clock divide bits
PWMCON.2
PWM counter = clock / [1,4,16,64]
PWMCON.1 PWM clock source bits [1=FXTAL/15, 2=FXTAL,
PWMCON.0
3=T0 ext.int.rate, 4=FVCO(16.777MHz)]
PWM0H,PWM0L PWM0 data registers
DPCON
DPCON.6
DPCON.5
DPCON.4
DPCON.3
DPCON.2
DPCON.1
DPCON.0
T3CON
T3CON.7
T3CON.2
T3CON.1
T3CON.0
T3FD
BIG MEMORY
WDCON
EDATA1,EDATA2,EDATA3,EDATA4
Data Pointer Control register
data pointer auto-toggle enable (0=disable)
shadow data pointer mode control bits
[1=8052, 2=post-inc, 3=post-dec, 4=LSBtgl]
main data pointer mode control bits
[1=8052, 2=post-inc, 3=post-dec, 4=LSBtgl]
(not implemented to allow INC DPCON toggling)
data pointer select [0=main, 1=shadow]
Timer 3 Control register
Timer 3 baud rate enable (0=disable)
binary divide factor (DIV)
DIV = log[FCORE/(32·baudrate)] / log2
(rounded down)
Timer 3 Fractional Divider register
T3FD = (2·FCORE) / (baudrate·2DIV) - 64
BIG MEMORY
extended stack-pointer enable (0=disable)
PWM pins select (0=P2.6/P2.7,1=P3.4/P3.3)
DAC output buffer bypass (0=buffer enabled)
external clock select (0=internal clock)
(this bit must contain 0)
(this bit must contain 0)
(this bit must contain 0)
internal XRAM select (0=external XRAM)
EADRH,EADRL Data Flash/EE address registers
PWM1H,PWM1L PWM1 data registers
mnemonic
reset value
address
CFG832.7
CFG832.6
CFG832.5
CFG832.4
CFG832.3
CFG832.2
CFG832.1
CFG832.0
SPH
ADC Data registers
BIG MEMORY
CFG832 ADuC832 Configuration Register
PRE3
PRE2
PRE1
PRE0
WDIR
WDS
WDE
WDWR
busy indicator flag (0=ADC not active)
gain calibration disable (0=gain cal enabled)
number of averages selection bits:
[15,1,31,63]
cal clock divide select (0=ADCclk, 1=ADCclk/2)
cal mode select (0=device, 1=system)
cal type select (0=offset, 1=gain)
start calibration bit, cleared by hardware
ADCDATAH
80h
1
81h
1
82h
1
0
IT0
88h
0
IE0
89h
0
IT1
8Ah
0
8Bh
IE1
ADCI
DMA
CCONV
SCONV
CS3
CS2
CS1
CS0
BIG MEMORY BIG MEMORY
SFR DESCRIPTIONS
ADC mode (0=off, 1=on)
external Vref select bit (0=on-chip Vref)
conversion time = 16 / ADCclk
ADCclk = 16,777,216Hz / [8,4,16,32]
acquisition time select bits
acq time = [1,2,3,4] / ADCclk
Timer2 convert enable
external CONVST enable
ADCCON2
I2CDAT
these bits are contained in this byte
mnemonic
address
reset value
ADCCON1.7
ADCCON1.6
ADCCON1.5
ADCCON1.4
ADCCON1.3
ADCCON1.2
ADCCON1.1
ADCCON1.0
SPIDAT
0
TR0
8Ch
0
TF0
8Dh
0
TR1
8Eh
0
TF1
8Fh
1
90h
1
91h
1
92h
93h
1
1
95h
1
96h
1
97h
9Ch
0
9Dh
0
9Eh
0
9Fh
94h
9Bh
0
1
99h
0
9Ah
0
T2
0
0
98h
RI
A0h
1
A1h
1
TI
RB8
A2h
1
A3h
1
TB8
REN
A4h
1
A5h
1
SM2
SM1
A6h
1
A7h
SM0
A8h
0
A9h
0
AAh
0
ABh
0
ACh
0
ADh
0
AEh
0
AFh
T2EX
1
0
EX0
ET0
EX1
ET1
ES
ET2
EADC
EA
1
RXD
B0h
1
TXD
B1h
1
INT0
B2h
1
INT1
B3h
1
T0
B4h
1
T1
B5h
1
WR
B6h
1
RD
0
PT0
B9h
0
PX1
BAh
0
PT1
BBh
0
PS
BCh
0
PT2
BDh
0
PADC
BEh
0
PSI
BFh
WDS
C2h
0
WDIR
C3h
1
PRE0
C4h
0
PRE1
C5h
0
PRE2
C6h
0
PRE3
C7h
B7h
B8h
PX0
0
0
WDWR
C0h
0
C1h
WDE
0
0
CAP2
C8h
0
CNT2
C9h
0
TR2
CAh
0
EXEN2
CBh
0
TCLK
CCh
0
RCLK
CDh
0
EXF2
CEh
0
TF2
CFh
0
P
D0h
0
F1
D1h
0
OV
D2h
0
RS0
D3h
0
RS1
D4h
0
F0
D5h
0
AC
D6h
0
CY
D7h
0
0
CS0
D8h
E0h
0
0
CS1
D9h
E1h
0
0
CS2
DAh
E2h
0
0
CS3
E3h
DBh
0
0
E4h
DCh
0
DDh
0
CCONV SCONV
E5h
0
0
DMA
DEh
E6h
0
0
ADCI
DFh
R0
E7h
00h
0
0
E8h
R1
0
01h
E9h
1
0
R2
EAh
02h
0
2
EBh
R3
0
03h
000h
ECh
3
00h
0
R4
EDh
04h
0
4
EEh
R5
0
R6
05h
(16M bytes
addressable)
EFh
06h
5
2K bytes
I2CI
6
128 bytes
lower RAM
(direct or
indirect
addressing)
I2CTX
R7
I2CRS
07h
I2CM
R0
7
MDI
R1
08h
MCO
09h
8
MDE
9
external
data
memory
MDO
R2
internal
data
memory
0
0Ah
128 bytes
SFRs
upper RAM
(direct
(indirect
addressing
addressing
only)
only)
F0h
10
FFh
0
R3
F1h
0Bh
CFG832.0=0
0
11
CFG832.0=1
F2h
R4
0
0Ch
F3h
12
0
R5
F4h
R6
0Dh
7FFh
0
0Eh
13
( page 0 )
F5h
14
000h
0
R7
F6h
R0
0Fh
0
10h
15
F7h
16
MAP KEY
R1
SPICON
R2
11h
F8h
12h
17
0
18
SPR0
R3
F8h
R4
13h
0
14h
19
SPR1
20
4K bytes
(1K pages)
data
Flash/EE
(accessible
through
SFRs)
F9h
R5
1
R6
15h
CPHA
16h
21
FAh
22
0
R7
CPOL
17h
FFFFFFh
( page 1023 )
FBh
23
3FFh
0
R0
SPIM
R1
18h
FCh
19h
24
0
25
Register Bank 0
R2
Register Bank 1
1Ah
Register Bank 2
26
SPE
R3
FDh
1Bh
0
27
DATA MEMORY SPACE
(read/write area)
WCOL
R4
FEh
1Ch
0
28
ISPI
R5
FFh
1Dh
Register Bank 3
29
(not used)
R6
00h A4h
1Eh
I2CADD
30
00h A3h
00h
I2CDAT
01h
00h A2h
02h
SBUF
03h
FFh A1h
04h
SCON
05h
A0h
06h
R7
MIN
07h
1Fh
SEC
20h
31
HTHSEC
32
A0h
08h
TIMECON
10h
09h
00h A9h
11g
0Ah
P2
12h
0Bh
A8h
13h
0Ch
(reserved)
14h
0Dh
(reserved)
15h
0Eh
(reserved)
16h
0Fh
IEIP2
17h
21h
IE
22h
33
PWM1H
34
BCh
18h
00h B4h
19h
PWM1L
1Ah
00h B3h
1Bh
PWM0H
1Ch
00h B2h
1Dh
00h
1Eh
PWM0L
1Fh
00h B9h
23h
FFh B1h
35
P3
20h
B0h
21h
B8h
22g
EDATA1
23h
(reserved)
24h
(reserved)
25h
ECON
26h
IP
27h
2Xh
24h
C2h
28h
36
10h
30h
29h
C0h
31h
2Ah
(reserved)
32h
2Bh
00h CCh
33h
2Ch
(reserved)
34h
2Dh
00h CBh
35h
2Eh
CHIPID
36h
2Fh
CAh
37h
25h
(reserved)
26h
37
00h
38
WDCON
38h
C8h
39h
TL2
3Ah
00h D4h
3Bh
RCAP2H
3Ch
00h D3h
3Dh
RCAP2L
3Eh
D2h
3Fh
(reserved)
27h
00h
40h
T2CON
48h
41h
D0h
49h
42h
DMAP
4Ah
43h
DMAH
4Bh
44h
DMAL
4Ch
45h
(reserved)
4Dh
46h
PSW
4Eh
47h
DAC0L
4Fh
(reserved)
39
Bit Addressable
Area
(reserved)
28h
00h
29h
40
00h DAh
41
00h D9h
50h
D8h
58h
51h
00h
59h
52h
E0h
5Ah
53h
ADCCON2 ADCDATAL ADCDATAH (reserved)
5Bh
54h
(reserved)
5Ch
55h
(reserved)
5Dh
56h
(reserved)
5Eh
57h
(reserved)
5Fh
2Ah
(reserved)
2Bh
42
(reserved)
43
(reserved)
60h
00h
61h
ACC
62h
E8h
63h
ADCCON1
64h
(reserved)
65h
(reserved)
66h
(reserved)
67h
(reserved)
2Ch
(reserved)
44
(reserved)
68h
I2CCON
69h
SPIDAT
6Ah
(reserved)
6Bh
00h
6Ch
*00h F5h
6Dh
*00h F4h
6Eh
*20h F3h
6Fh
*00h F2h
2Dh
00h F1h
45
F0h
70h
(reserved)
78h
71h
(reserved)
79h
72h
04h
7Ah
73h
DACCON
7Bh
74h
00h FDh
7Ch
75h
DAC1H
7Dh
76h
00h FCh
7Eh
77h
DAC1L
7Fh
2Eh
00h FBh
2Fh
46
(bit addresses)
DAC0H
47
General Purpose
Area
00h FAh
30h
ADCOFSL ADCOFSH ADCGAINL ADCGAINH ADCCON3
...
48
B
7Fh
...
LSB
address
127
MSB
address
HEX
address
decimal
address
SFR MAP & RESET VALUES
LOWER RAM
BIG MEMORY
CHIPID
Chip ID Register (2X hex = ADuC832)
BIG MEMORY
BIG MEMORY
P0
Timer2 register
Port0 register (also A0-A7 & D0-D7)
P1
Port1 register (analog & digital inputs)
T2EX
T2
timer/counter 2 capture/reload trigger
timer/counter 2 external input
P2
Port2 register (also A8-A15 & A16-A23)
P3
Port3 register
RD
WR
T1
T0
INT1
INT0
TxD
RxD
external data memory read strobe
external data memory write strobe
timer/counter 1 external input
timer/counter 0 external input
external interrupt 1
external interrupt 0
serial port transmit data line
serial port receive data line
SCON
SM0
SM1
SM2
REN
TB8
RB8
TI
RI
Serial communications Control register
UART mode control bits baud rate:
00 - 8bit shift register - FOSC/12
01 - 8bit UART
- variable
10 - 9bit UART
- FOSC/64(x2)
11 - 9bit UART
- variable
in modes 2&3, enables multiprocessor communication
receive enable control bit
in modes 2&3, 9th bit transmitted
in modes 2&3, 9th bit received
transmit interrupt flag
receive interrupt flag
SBUF
PCON
PCON.7
PCON.4
PCON.3
PCON.2
PCON.1
PCON.0
Serial port Buffer register
Power Control register
double baud rate control
ALE disable (0=normal, 1=forces ALE high)
general purpose flag
general purpose flag
power-down control bit (recoverable with hard reset)
idle-mode control (recoverable with enabled interrupt)
PSW
Program Status Word
CY
AC
F0
RS1
RS0
OV
F1
P
carry flag
auxiliary carry flag
general purpose flag 0
register bank select control bits
active register bank = [0,1,2,3]
overflow flag
general purpose flag 1
parity of ACC
DPP
Data Pointer Page
DPH,DPL (DPTR)
Data Pointer
ACC
Accumulator
B
auxiliary math register
BIG MEMORY
BIG MEMORY