PIN FUNCTIONS
ADuC812
direct
8bit internal address (00h-FFh)
3
P1.2 / ADC2
@Ri
indirect addressing using R0 or R1
4
P1.3 / ADC3
source
any of [Rn, direct, @Ri]
dest
any of [Rn, direct, @Ri]
5
AVDD
#data
8bit constant included in instruction
6
AGND
39
38
37
36
35
34
33
32
31
30
29
28
27
ADuC812
52pin PQFP
TOP VIEW
(not to scale)
12
#data16 16bit constant included in instruction
7
CREF
1
12
bit
8bit direct address of bit
8
VREF
1,2
12
rel
signed 8bit offset
9
DAC0
DPTR *
1
24
addr11
11bit address in current 2K page
10
DAC1
DEC
A
1
12
addr16
16bit address
11
P1.4 / ADC4
DEC
source
1,2
12
* INC DPTR increments the 24bit value DPP/DPH/DPL
12
P1.5 / ADC5 / SS
MUL
AB
multiply A by B
1
48
13
P1.6 / ADC6
DIV
AB
divide A by B
1
48
Logical Operations
DA
A
decimal adjust
1
12
ANL
A,source
1,2
12
ANL
A,#data
2
12
14
P1.7 / ADC7
27
SDATA / MOSI
40
EA
direct,A
2
12
15
RESET
28
P2.0 / A8 / A16
41
PSEN
direct,#data
3
24
16
P3.0 / RxD
29
P2.1 / A9 / A17
42
ALE
17
P3.1 / TxD
30
P2.2 / A10 / A18
43
P0.0 / AD0
18
P3.2 / INT0
31
P2.3 / A11 / A19
44
P0.1 / AD1
19
P3.3 / INT1 / MISO
32
XTAL1 (in)
45
P0.2 / AD2
20
DVDD
33
XTAL2 (out)
46
P0.3 / AD3
21
DGND
34
DVDD
47
DGND
22
P3.4 / T0
35
DGND
48
DVDD
23
P3.5 / T1 / CONVST
36
P2.4 / A12 / A20
49
P0.4 / AD4
24
P3.6 / WR
37
P2.5 / A13 / A21
50
P0.5 / AD5
25
P3.7 / RD
38
P2.6 / A14 / A22
51
P0.6 / AD6
26
SCLOCK
39
P2.7 / A15 / A23
52
P0.7 / AD7
direct,A
2
12
ORL
direct,#data
MOV DPTR,#data16
3
24
XRL
A,source
MOVC A,@A+DPTR move from
code memory
MOVC A,@A+PC
1
24
XRL
A,#data
1
24
XRL
direct,A
MOVX A,@Ri
1
24
XRL
direct,#data
1
24
CLR
A
MOVX A,@DPTR
MOVX @Ri,A
2,3 12,24
move to/from
data memory
MOVX @DPTR,A
logical OR
logical XOR
clear A to zero
3
24
1,2
12
2
12
2
12
3
24
1
12
1
24
CPL
A
complement A
1
12
1
24
RL
A
rotate A left
1
12
push onto stack
2
24
RLC
A
...through C
1
12
direct
pop from stack
2
24
RR
A
rotate A right
1
12
XCH
A,source
exchange bytes 1,2
12
RRC
A
...through C
1
12
exchg low digits
12
SWAP A
swap nibbles
1
12
1
by
te
s
O
S
pe C
ri o
d
s
XCHD A,@Ri
Program Branching
ACALL addr11
LCALL addr16
call subroutine
Boolean Variable Manipulation
2
24
CLR
C
3
24
CLR
bit
RET
return from sub.
1
24
SETB C
RETI
return from int.
1
24
SETB bit
2
24
CPL
C
3
24
CPL
bit
2
24
ANL
C,bit
1
24
ANL
2
24
ORL
AJMP addr11
LJMP addr16
SJMP rel
JMP
@A+DPTR
JZ
rel
JNZ
jump
jump if A = 0
rel
jump if A not 0
CJNE A,direct,rel
CJNE A,#data,rel
CJNE Rn,#data,rel
compare and
jump if not
equal
CJNE @Ri,#data,rel
DJNZ Rn,rel
DJNZ direct, rel
NOP
decrement and
jump if not zero
no operation
clear bit to zero
set bit to one
1
12
2
12
1
12
2
12
1
12
2
12
AND bit with C
2
24
C,/bit
...NOTbit with C
2
24
C,bit
OR bit with C
2
24
2
24
ORL
C,/bit
3
24
MOV
C,bit
3
24
MOV
bit,C
complement bit
...NOTbit with C
move bit to bit
2
24
2
12
2
24
3
24
JC
rel
jump if C set
2
24
2
24
JNC
rel
jmp if C not set
2
24
2
24
JB
bit,rel
jump if bit set
3
24
3
24
JNB
bit,rel
jmp if bit not set
3
24
1
12
JBC
bit, rel
jmp&clear if set
3
define symbol
define internal memory symbol
define indirect addressing symbol
define external memory symbol
define internal bit memory symbol
define program memory symbol
reserve bytes of data memory
reserve bits of bit memory
store byte values in program memory
DW
ORG
END
CSEG
XSEG
DSEG
ISEG
BSEG
Flash/EEPROM:
8K bytes Flash/EE program memory
640 bytes Flash/EE data memory
microcontroller:
industry standard 8052
DC to 16MHz, up to 1.3MIPS, 32 I/O lines
other on-chip features: temperature sensor, power supply monitor,
watchdog timer, flexible serial interface ports,
precision voltage reference
PROGRAM MEMORY SPACE (read only)
FUNCTIONAL BLOCK DIAGRAM
FFFFh
external
program
memory
64K bytes
addressable
2000h
1FFFh
0000h
EA=1
internal
8K bytes
Flash/EE
EA=0
external
store word values in program memory
set segment location counter
end of assembly source file
select program memory space
select external data memory space
select internal data memory space
select indirectly addressed internal
data memory space
select bit addressable memory space
hardware
CONVST
23
ADC0
ADC1
ADC2
ADC3
ADC4
ADC5
ADC6
ADC7
1
2
3
4
11
12
13
14
ADuC812
INTERRUPT VECTOR ADDRESSES
ADC
control
&
calibration
12bit ADC
T/H
AIN
MUX
TEMP
sensor
Interrupt
Bit
Interrupt Name
PSMCON.5
IE0
ADCI
TF0
IE1
TF1
ISPI/I2CI
RI/TI
TF2/EXF2
Power Supply Monitor Interrupt
External Interrupt 0
End of ADC Conversion Interrupt
Timer0 Overflow Interrupt
External Interrupt 1
Timer1 Overflow Interrupt
SPI/I2C Interrupt
UART Interrupt
Timer2 Interrupt
43h
03h
33h
0Bh
13h
1Bh
3Bh
23h
2Bh
1
2
3
4
5
6
7
8
9
VREF
8
CREF
7
BUF
9
DAC0
DAC1
BUF
10
DAC1
22
T0
23
T1
1
T2
2
T2EX
18
INT0
19
INT1
256 x 8
user RAM
Flash/EE
2.5V
bandgap
reference
Vector Priority
within
Address Level
DAC1
DAC
control
640 x 8
data
(-3 mV/oC)
8K x 8
program
Flash/EE
24
ASSEMBLER DIRECTIVES
EQU
DATA
IDATA
XDATA
BIT
CODE
DS
DBIT
DB
dual, 12bit, 15µs, voltage output
1LSB DNL
by
te
s
O
S
pe C
ri o
ds
PUSH direct
POP
DAC:
8052
MCU
core
asynchronous
serial port
(UART)
www.analog.com/microconverter
watchdog
timer
power supply
monitor
downloader
debugger
BUF
16bit
counter
timers
synchronous
serial interface
(SPI or I2C)
OSC
33
ORL
32
1,2,3 24
XTAL2
12
XTAL1
12
2
P3.0 (RxD)
P3.1 (TxD)
P3.2 (INT0)
P3.3 (INT1 / MISO)
P3.4 (T0)
P3.5 (T1 / CONVST)
P3.6 (WR)
P3.7 (RD)
1,2
16
17
18
19
22
23
24
25
A,source
A,#data
12
dest,#data
ORL
ORL
SS
MOV
12
12
26
27
19
dest,source
2
1,2
SCLOCK
SDATA / MOSI
MISO
MOV
move source
to destination
12bit, 5µs, 8channel, self calibrating
0.5LSB INL & 70dB SNR
P2.0 (A8 / A16)
P2.1 (A9 / A17)
P2.2 (A10 / A18)
P2.3 (A11 / A19)
P2.4 (A12 / A20)
P2.5 (A13 / A21)
P2.6 (A14 / A22)
P2.7 (A15 / A23)
A,#data
dest,A
ADC:
28
29
30
31
36
37
38
39
MOV
MOV
the ADuC812 is:
single-pin
emulator
ANL
12
42
41
40
15
1,2
A,source
ALE
PSEN
EA
RESET
MOV
logical AND
17
by
te
s
O
S
pe C
rio
d
ANL
16
Data Transfer Operations
a “Data Acquisition System on a Chip”
TxD
decrement
RxD
INC
increment
P1.0 (ADC0 / T2)
P1.1 (ADC1 / T2EX)
P1.2 (ADC2)
P1.3 (ADC3)
P1.4 (ADC4)
P1.5 (ADC5 / SS)
P1.6 (ADC6)
P1.7 (ADC7)
source
1
2
3
4
11
12
13
14
INC
21
35
47
A
s
INC
MicroConverter®
Quick Reference Guide
DGND
12
pin 1 identifier
1
2
3
4
5
6
7
8
9
10
11
12
13
20
34
48
subtract from A 1,2
with borrow
2
12
DVDD
2
52
51
50
49
48
47
46
45
44
43
42
41
40
12
12
14
15
16
17
18
19
20
21
22
23
24
25
26
SUBB A,#data
2
1,2
by
te
s
O
S
pe C
rio
ds
SUBB A,source
P1.1 / ADC1 / T2EX
P0.0 (AD0)
P0.1 (AD1)
P0.2 (AD2)
P0.3 (AD3)
P0.4 (AD4)
P0.5 (AD5)
P0.6 (AD6)
P0.7 (AD7)
ADDC A,#data
add with carry
2
43
44
45
46
49
50
51
52
ADDC A,source
add source to A
P1.0 / ADC0 / T2
register addressing using R0-R7
6
A,#data
1
Rn
5
ADD
Legend
12
AVDD
1,2
AGND
A,source
G3697-5-10/99
ADD
PRINTED IN U.S.A.
Arithmetic Operations
by
te
s
O
S
pe C
rio
d
s
INSTRUCTION SET
REV. B
DATA MEMORY:
RAM, SFRs, user Flash/EE (all read/write)
SFR DESCRIPTIONS
R0
7
07h
R7
6
06h
R6
5
05h
R5
4
04h
R4
3
03h
R3
2
02h
R2
1
01h
R1
0
00h
R0
DAC0L
SPICON
00h
PCON
(not used)
(not used)
(not used)
(not used)
(not used)
00h
(not used)
EDATA4
(reserved)
(reserved)
DEh
(reserved)
PSMCON
DFh
20h
(reserved)
EFh
00h
ADCCON1
SPIDAT
F7h
87h
(reserved)
08h
(reserved)
R1
8
00h
R2
09h
DPP
0Ah
9
00h 84h
10
DPH
R3
ADCCON3.7
ADCCON3.6
ADCCON3.5
ADCCON3.4
ADCCON3.3
ADCCON3.2
ADCCON3.1
ADCCON3.0
mnemonic
address
reset value
SPR1
F9h
SPR0
0
F8h
SPICON
0
F8h
00h
* calibration coefficients are preconfigured at power-up to factory calibrated values
ADCDATAH
ADCDATAL
DACCON.7
DACCON.6
DACCON.5
DACCON.4
DACCON.3
DACCON.2
DACCON.1
DACCON.0
DAC1H,DAC1L
DAC1 data registers
DAC0H,DAC0L
DAC0 data registers
ECON
data EE/FLASH comand register
01h
02h
03h
1
80h
1
0
data EE/FLASH Data registers
ETIM1,ETIM2,ETIM3 EE/FLASH timing regs
81h
1
84h
master mode SDATA output bit
master mode SDATA output enable
master mode SCLK bit
master mode SDATA input bit
master mode select
serial port reset
transmission direction status
serial interface interrupt
I2C Address register
85h
MDO
MDE
MCO
MDI
I2CM
I2CRS
I2CTX
I2CI
SPI inturrupt (set at end of SPI transfer)
write collision error flag
SPI enable (0=disable SPI & enable I2C)
master mode select (0=slave)
clock polarity select (0=SCLK idles low)
clock phase select (0=leading edge latch)
SPI bitrate select bits
bitrate = Fosc / [4, 8, 32, 64]
I2CDAT
I2C Data register
1
1
83h
1
82h
1
SPI Control register
I2CADD
WDCON
Watchdog Timer control register
1
87h
86h
IT0
88h
0
data EE/FLASH address register
I2C Control register
89h
VERIFY
ERASE
ERASE ALL
EDATA1,EDATA2,EDATA3,EDATA4
I2CCON
0
IE0
IT1
0
04h
05h
06h
SPI Data register
0
IE1
READ
WRITE
(reserved)
SPIDAT
8Ch
8Bh
ModeSelect (0=12bit, 1=8bit)
DAC1 RangeSelect (0=VREF, 1=VDD)
DAC0 RangeSelect (0=VREF, 1=VDD)
Clear DAC1 (0=0V, 1=normal operation)
Clear DAC0 (0=0V, 1=normal operation)
SynchronousUpdate (1=asynchronous)
PowerDown DAC1 (0=off, 1=on)
PowerDown DAC0 (0=off, 1=on)
ISPI
WCOL
SPE
SPIM
CPOL
CPHA
SPR1
SPR0
0
TR0
TF0
8Dh
0
TR1
8Eh
ADC Data registers
DAC Control register
0
TF1
mnemonic
reset value
address
ADC Control register #3
busy indicator flag (0=ADC not active)
(this bit must contain zero)
(this bit must contain zero)
(this bit must contain zero)
(this bit must contain zero)
(this bit must contain zero)
(this bit must contain zero)
(this bit must contain zero)
DACCON
8Fh
these bits are contained in this byte
priority of ISPI/I2CI (serial interface interrupt)
priority of ADCI (ADC interrupt)
priority of TF2/EXF2 (Timer2 overflow interrupt)
priority of RI/TI (serial port interrupt)
priority of TF1 (Timer1 overflow interrupt)
priority of IE1 (external INT1)
priority of TF0 (Timer0 overflow interrupt)
priority of IE0 (external INT0)
ADCCON3
SPICON
8Ah
1
T2
1
T2EX
91h
1
92h
1
93h
1
94h
1
95h
1
1
97h
96h
RB8
TB8
SM1
90h
0
98h
TI
0
0
REN
9Ch
0
9Dh
0
SM0
9Fh
9Eh
0
SM2
9Bh
0
9Ah
0
99h
A0h
A1h
1
A4h
1
A7h
A6h
1
A5h
1
A3h
1
A2h
1
1
RI
1
0
A8h
0
A9h
0
0
ACh
0
AFh
AEh
0
ADh
0
ABh
0
AAh
1
EX0
B0h
B1h
ET0
EX1
B2h
B3h
ET1
ES
B4h
B5h
1
B6h
ET2
EA
B7h
RD
1
WR
EADC
T1
1
T0
PS
1
INT1
PT1
1
INT0
PX1
1
TXD
PT0
1
RXD
PX0
0
0
BEh
PT2
PSI
BFh
0
PADC
BDh
0
BCh
0
BBh
0
BAh
0
B9h
0
B8h
0
WDE
C0h
0
WDS
C1h
0
WDR2
C2h
0
WDR1
C3h
0
C4h
0
PRE0
C5h
0
PRE1
C6h
0
PRE2
C7h
CAP2
0
CAh
0
EXEN2
CBh
0
TCLK
CCh
RCLK
0
CFh
TF2
0
CEh
EXF2
0
CDh
TR2
0
C9h
CNT2
0
C8h
0
P
D0h
0
F1
D1h
0
OV
D2h
0
RS0
D3h
0
RS1
D4h
0
F0
D5h
0
AC
D6h
0
CY
D7h
0
0
D8h
E0h
0
0
CS0
CS1
D9h
E1h
0
0
CS2
E2h
DAh
0
0
CS3
E3h
DBh
0
0
DCh
E4h
0
0
DDh
E5h
CCONV SCONV
0
0
DMA
E6h
DEh
0
0
ADCI
E7h
DFh
0
E8h
0
E9h
0
EBh
0
ECh
0
EDh
EEh
0
MDO
EFh
MDE
0
MCO
MDI
I2CM
0
EAh
I2CTX
I2CRS
F2h
0
F3h
0
F4h
0
F5h
0
F6h
0
F7h
MAP KEY
SFR details
FFh
ISPI
lower RAM
details
I2CI
0
F0h
F1h
0
0
0
F8h
0
SPR0
SPR1
F9h
0
CPHA
FAh
0
CPOL
FBh
0
FCh
0
SPIM
SPE
FDh
0
WCOL
000000h
FEh
00h
128 bytes
lower RAM
(direct or
indirect
addressing)
0
Register
Bank 0
128 bytes
SFRs
upper RAM
(direct
(indirect
addressing
addressing
only)
only)
Interrupt Priority register
PSI
PADC
PT2
PS
PT1
PX1
PT0
PX0
00h 83h
0Bh
FFh
enable PSMI (power supply monitor interrupt)
enable ISPI/I2CI (serial interface interrupt)
IP
ADC Offset
calibration coefficients
DPL
11
Register
Bank 1
Interrupt Enable register #2
IE2.1
IE2.0
07h 82h
R4
(16MEG
addressable)
IE2
ADCOFSH
ADCOFSL
SP
R5
0Ch
( page 0 )
ADC Control register #2
ADC interrupt flag
DMA mode enable
continuous conversion enable bit
single conversion start bit
input channel select bits
0000 - 0111 = ADC0 - ADC7
1000 = temperature sensor
1111 = “HALT” command (DMA mode only)
ADC Gain
calibration coefficients
FFh 81h
0Dh
12
00h
external
data
memory
enable inturrupts (0=all inturrupts disabled)
enable ADCI (ADC interrupt)
enable TF2/EXF2 (Timer2 overflow interrupt)
enable RI/TI (serial port interrupt)
enable TF1 (Timer1 overflow interrupt)
enable IE1 (external interrupt 1)
enable TF0 (Timer0 overflow interrupt)
enable IE0 (external interrupt 0)
ADCGAINH
ADCGAINL
P0
13
ADCI
DMA
CCONV
SCONV
CS3
CS2
CS1
CS0
EADRL
Register
Bank 2
Interrupt Enable register #1
EA
EADC
ET2
ES
ET1
EX1
ET0
EX0
ADC power control bits
[shtdn, norm, autoshtdn, autostby]
conversion time = 15.5 / ADCclk
ADCclk = Mclk / [1,2,4,8]
acquisition time select bits
acq time = [1,2,3,4] / ADCclk
Timer2 convert enable
external CONVST enable
ADCCON2
FFFFFFh
640 bytes
(160 pages)
data
Flash/EE
(accessible
through
SFRs)
IE
ADCCON1.7
ADCCON1.6
ADCCON1.5
ADCCON1.4
ADCCON1.3
ADCCON1.2
ADCCON1.1
ADCCON1.0
ADC Control register #1
DMAP,DMAH,DMAL DMA address pointer
80h
R6
(not used)
0Eh
00h
14
TH1
R7
00h 8Dh
R0
0Fh
TH0
10h
15
00h 8Ch
16
TL1
R1
00h 8Bh
R2
11h
TL0
12h
17
00h 8Ah
18
TMOD
R3
00h 89h
R4
13h
TCON
14h
19
88h
20
(not used)
R5
(not used)
15h
(not used)
21
(not used)
R6
(not used)
R7
16h
(not used)
17h
22
( page 159 )
FFh
23
9Fh
P1
R0
90h
R1
18h
(not used)
19h
24
(not used)
25
(not used)
R2
55h
1Ah
I2CADD
26
DATA MEMORY SPACE
(read/write area)
Register
Bank 3
00h 9Bh
R3
I2CDAT
1Bh
00h 9Ah
R4
27
SBUF
1Ch
00h 99h
R5
28
SCON
R6
1Dh
98h
1Eh
29
(not used)
30
(not used)
R7
(not used)
1Fh
(not used)
31
(not used)
00h
(not used)
01h
FFh
02h
P2
03h
A0h
04h
(not used)
05h
(not used)
06h
(not used)
07h
(not used)
20h
(not used)
32
00h
08h
IE2
09h
00h A9h
0Ah
A8h
0Bh
FFh
0Ch
IE
0Dh
B0h
0Eh
(not used)
0Fh
(not used)
21h
(not used)
33
(not used)
10h
ADCCON1
(not used)
11g
(not used)
12h
P3
13h
00h BFh
14h
EDATA3
15h
00h BEh
16h
EDATA2
17h
00h BDh
22h
EDATA1
34
04h BCh
18h
ETIM2
19h
52h BBh
1Ah
ETIM1
1Bh
00h BAh
1Ch
ECON
1Dh
00h B9h
1Eh
IP
1Fh
B8h
23h
00h
35
EADRL
20h
C6h
21h
(reserved)
22g
C9h
23h
ETIM3
24h
C4h
25h
(not used)
26h
(not used)
27h
(not used)
24h
00h
36
WDCON
28h
C0h
30h
29h
(reserved)
31h
2Ah
00h
32h
2Bh
TH2
33h
2Ch
00h CDh
34h
2Dh
00h CCh
35h
2Eh
00h CBh
36h
2Fh
CAh
37h
25h
00h
26h
37
C8h
38
00h
38h
TL2
39h
00h D4h
3Ah
RCAP2H
3Bh
00h D3h
3Ch
RCAP2L
3Dh
D2h
3Eh
(reserved)
3Fh
00h
27h
T2CON
40h
39
D0h
48h
41h
(reserved)
49h
42h
(reserved)
4Ah
43h
DMAP
4Bh
44h
DMAH
4Ch
45h
DMAL
4Dh
46h
(reserved)
4Eh
47h
Bit Addressable
Area
PSW
4Fh
28h
(reserved)
29h
40
(reserved)
41
(reserved)
50h
00h
58h
51h
00h DAh
59h
52h
00h D9h
5Ah
53h
D8h
5Bh
54h
00h
5Ch
55h
E0h
5Dh
56h
ADCCON2 ADCDATAL ADCDATAH (reserved)
5Eh
57h
(reserved)
5Fh
2Ah
(reserved)
2Bh
42
(reserved)
43
(reserved)
60h
(reserved)
68h
61h
(reserved)
69h
62h
00h
6Ah
63h
ACC
6Bh
64h
E8h
6Ch
65h
(reserved)
6Dh
66h
(reserved)
6Eh
67h
(reserved)
6Fh
2Ch
(reserved)
2Dh
44
(reserved)
45
(reserved)
70h
I2CCON
71h
(reserved)
72h
00h
73h
*00h F5h
74h
*00h F4h
75h
*20h F3h
76h
*00h F2h
77h
F0h
2Eh
00h F1h
(not used)
46
(reserved)
78h
04h
79h
DACCON
7Ah
00h FDh
7Bh
DAC1H
7Ch
00h FCh
7Dh
DAC1L
7Eh
00h FBh
7Fh
DAC0H
2Fh
00h FAh
47
(bit addresses)
ADCOFSL ADCOFSH ADCGAINL ADCGAINH ADCCON3
30h
00h F9h
48
General Purpose
Area
B
...
LSB
address
7Fh
...
MSB
address
127
F8h
LOWER RAM
HEX
address
decimal
address
SFR MAP & RESET VALUES
PRE2
PRE1
PRE0
WDR1
WDR2
WDS
WDE
watchdog timeout selection bits
timeout=[16,32,64,128,256,512,1024,2048]ms
watchdog timer refresh bits
set sequentialy to refresh watchdog
watchdog status flag
watchdog enable
PSMCON Power Supply Monitor control register
PSMCON.7
PSMCON.6
PSMCON.5
PSMCON.4
PSMCON.3
PSMCON.2
PSMCON.1
PSMCON.0
SP
(not used)
PSM status bit (1=normal / 0=fault)
PSM interrupt bit
trip point select bits
[4.63V, 4.37V, 3.08V, 2.93V, 2.63V]
AVDD/DVDD fault indicator (1=AVDD / 0=DVDD)
PSM powerdown control (1=on / 0=off)
Stack Pointer
TMOD
Timer Mode register
TMOD.3/.7
gate control bit (0=ignore INTx)
TMOD.2/.6
counter/timer select bit (0=timer)
TMOD.1/.5
timer mode selecton bits
TMOD.0/.4
[13bitT, 16bitT/C, 8bitT/Creload, 2x8bitT]
(upper nibble = Timer1, lower nibble = Timer0)
TCON
TF1
TR1
TF0
TR0
IE1
IT1
IE0
IT0
Timer Control register
Timer1 overflow flag (auto cleared on vector to ISR)
Timer1 run control (0=off, 1=run)
Timer0 overflow flag (auto cleared on vector to ISR)
Timer0 run control (0=off, 1=run)
external INT1 flag (auto cleared on vector to ISR)
IE1 type (0=level trig, 1=edge trig)
external INT0 flag (auto cleared on vector to ISR)
IE0 type (0=level trig, 1=edge trig)
TH0,TL0
Timer0 registers
TH1,TL1
Timer1 registers
T2CON
Timer2 Control register
TF2
EXF2
RCLK
TCLK
EXEN2
TR2
CNT2
CAP2
overflow flag
external flag
receive clock enable (0=Timer1 used for RxD clk)
transmit clock enable (0=Timer1 used for TxD clk)
external enable (0=ignore T2EX, 1=cap/rld on T2EX)
run control (0=stop, 1=run)
timer/counter select (0=timer, 1=counter)
capture/reload select (0=reload, 1=capture)
TH2,TL2
Timer2 register
RCAP2H,RCAP2L Timer2 Reload/Capture
P0
Port0 register (also A0-A7 & D0-D7)
P1
Port1 register (analog & digital inputs)
T2EX
T2
timer/counter 2 capture/reload trigger
timer/counter 2 external input
P2
Port2 register (also A8-A15 & A16-A23)
P3
Port3 register
RD
WR
T1
T0
INT1
INT0
TxD
RxD
external data memory read strobe
external data memory write strobe
timer/counter 1 external input
timer/counter 0 external input
external interrupt 1
external interrupt 0
serial port transmit data line
serial port receive data line
SCON Serial communications Control register
SM0
SM1
SM2
REN
TB8
RB8
TI
RI
UART mode control bits baud rate:
00 - 8bit shift register - FOSC/12
01 - 8bit UART
- TimerOverflowRate/32(x2)
10 - 9bit UART
- FOSC/64(x2)
11 - 9bit UART
- TimerOverflowRate/32(x2)
in modes 2&3, enables multiprocessor communication
receive enable control bit
in modes 2&3, 9th bit transmitted
in modes 2&3, 9th bit received
transmit interrupt flag
receive interrupt flag
SBUF
Serial port Buffer register
PCON Power Control register
PCON.7
PCON.4
PCON.3
PCON.2
PCON.1
PCON.0
double baud rate control
ALE disable (0=normal, 1=forces ALE high)
general purpose flag
general purpose flag
power-down control bit (recoverable with hard reset)
idle-mode control (recoverable with enabled interrupt)
PSW
Program Status Word
CY
AC
F0
RS1
RS0
OV
F1
P
carry flag
auxiliary carry flag
general purpose flag 0
register bank select control bits
active register bank = [0,1,2,3]
overflow flag
general purpose flag 1
parity of ACC
DPP
Data Pointer Page
DPH,DPL (DPTR) Data Pointer
ACC
Accumulator
B
auxiliary math register