Recap from last class
 Basic compilation optimization
 Expression simplification
 Dead code elimination
 Function inlining
 Loop optimizations
 Register allocation
 Optimization for embedded systems
 Optimizing for execution time
• Execution time analysis: Program path, instruction timing
• Execution time metrics: Average-case, worst-case
• Execution time measurement: trace analysis
 Optimizing for energy/power
• Measurement, sources of energy consumption, cache
 Optimizing for program size
• Reduce data size and code size
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ECE 455/555
Embedded System Design
Power Management - I
Wei Gao
Fall 2015
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The Power Problem
 Microprocessors improve performance at the cost of
power!
 Performance/watt remains low.
 Solutions
 Microprocessors offer features (hardware support) for
controlling power consumption.
 Software performs power management.
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Outline
 Hardware support
 Power management policy
 Power manager
 Holistic approach
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CMOS Power Consumption
 All digital systems are built with CMOS
 CMOS: Complementary Metal-Oxide Semiconductor
 A common technology for constructing integrated circuits
 Voltage drops
 Power consumption of a CMOS is proportional to the
square of the power supply voltage (V2).
 Toggling
 CMOS uses higher power when having more activity
 Leakage
 Even when CMOS is inactive, some charge leaks out of the
circuit’s nodes
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General Power-Saving Features
To deal with toggling
Run at lower clock frequency (slower)
Reduce activity by disabling function units when not in
use.
To deal with leakage
Eliminate leakage current by disconnecting parts from
power supply when not in use.
To deal with voltage drops
Reduce power supply voltage to the lowest level that
provides required performance
Pentium MMX: 2.8v
i7: ~1.5v
Cortex A8: 1.2v
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Clock Gating
 Applicable to clocked digital components
 Processors, controllers, memories
 Stop the clock  stop signal propagation in circuits
 Pros
 Simple
 Very short transition time if only clock distribution is
stopped while clock generation is not stopped
 Cons
 Clock itself still consumes energy
 Cannot prevent power leaking – exist as long as power
supply is connected
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Dynamic Voltage Scaling
 Why voltage scaling?
 Power ∝ V2
• Reduce power supply voltage  save energy
 Lower clock frequency allows lower voltage
• Tradeoff between performance and battery lifetime
• Overclocking? Raise voltage for better stability
 Why dynamic?
 Power consumption is not a constant.
• Depending on current workloads.
• Peak computing rate is usually much higher than average.
 Have to be dynamic to respond to power consumption variations.
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Dynamic Voltage Scaling
 Changing voltage takes time
 Need to stabilize power supply and clock
 Continuous and discrete voltage are both possible
 Many microprocessors have discrete power modes
• Pentium: discrete voltage levels at 0.1v
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Outline
 Hardware support
 Power management policy
 Power manager
 Holistic approach
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Power Management Styles
 Static Power Management
 Does not depend on activity.
 Example: user-activated power-down mode.
• Laptop monitor changes to low-power state when unplugged
 Dynamic Power Management (DPM)
 Automatic action based on activity.
 Example: automatically disabling function units.
• Monitor automatically turns off after no activity for a certain
period of time
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Dynamic Power Management
 Goals: Energy conservation AND good performance
 Need tradeoff between conflicting goals!
 Fundamental premises
 Systems have varying workloads during operation
• Running workloads: higher power and better performance
• Idling: lower power and worse performance
 It is possible to predict the fluctuations of workload with
some degree of accuracy
• Daytime vs. nighttime
 Performed by a Power Manager
 React to or predict workload variations
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Problem Formulations
of Dynamic Power Management
 Minimize power under performance constraints
 Real-time constraint
OR
 Optimize performance under power constraints
 Battery lifetime constraint
 Best server performance within the capacity of the power
supply and cooling facilities
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Cost of Dynamic Power Management
 Power management is not free
 Going into/out of an inactive mode costs:
 time;
 energy.
 Must determine if going into mode is worthwhile.
 Can model CPU power states with Power State
Machine (PSM)
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PSM Example: SA-1100
 SA-1100 is a StrongARM processor from Intel
 Designed to provide sophisticated power management
capabilities controlled by the on-chip power manager
 Three power modes:
 Run: normal operation.
 Idle: stops CPU clock, with I/O logic still powered.
 Sleep: shuts off most of chip activity
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SA-1100 SLEEP
 RUN  SLEEP
 (30 µs) Flush to memorize CPU states (registers)
 (30 µs) Reset processor state and wakeup event
 (30 µs) Shut down clock
 SLEEP  RUN
 (10 ms) Ramp up power supply
 (150 ms) Stabilize clock
 (negligible) CPU boot
 Overhead of sleep to run is much larger
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SA-1100 Power State Machine
Prun = 400 mW
run
10 µs
160 ms
90 µs
10 µs
idle
Pidle = 50 mW
90 µs
sleep
Psleep = 0.16 mW
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Baseline: Greedy Policy
 Immediately goes to sleep when system becomes
idle
 Works when transition time is negligible
 Ex. between IDLE and RUN in SA-1100
 Doesn’t work when transition time is long!
 Ex. between SLEEP and RUN/IDLE in SA-1100
 Need better solutions!
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Break-Even Time TBE
 Definition
 Minimum idle time required to compensate the cost of entering an
inactive state
• Cost: transition time and extra power
 Enter an inactive state is beneficial only if idle time is longer
than the break-even time
 Break-even time can be viewed as transition overhead
 Ex. going to Hawaii is worthwhile only if vacation is long enough
 Assumptions
 Cannot delay workload to extend idle time
 An ideal power manager (PM) knows how long the idle time is going to
be
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Break-Even Time TBE
 TBE of an inactive state is the total time for entering and
leaving the state
 Assumption: transition doesn’t cause extra power consumption
 TBE = TTR = TOn,Off + TOff,On
 Ex. TBE = 160 ms + 90 µs for SLEEP in SA-1100
Prun = 400 mW
run
10 µs
10 µs
idle
Pidle = 50 mW
90 µs
90 µs
160 ms
Power consumption during
transition ≈ Prun
sleep
Psleep = 0.16 mW
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Break-Even Time When PTR > POn
 PTR: Power consumption during transition
 POn: Power consumption when active
 TBE must include additional inactive time to
compensate extra power consumption during
transition.
Prun = 400 mW
run
10 µs
10 µs
idle
Pidle = 50 mW
90 µs
90 µs
160 ms
sleep
Psleep = 0.16 mW
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Break-Even Time When PTR > POn
 TBE = TTR + TTR(PTR - POn)/(POn - POff)
 TTR(PTR – POn): extra energy consumed for transition
 /(Pon-Poff): the idle time needed to compensate this energy
consumption back
 It is easier to save power with a shorter TBE
Prun = 400 mW
 Shorter TTR
run
• IDLE in SA-1100
 Higher difference between
10 µs
POn – POff
• SLEEP in SA-1100
 Lower PTR
10 µs
idle
Pidle = 50 mW
ECE 455/555 Embedded System Design
90 µs
90 µs
160 ms
sleep
Psleep = 0.16 mW
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Energy Saving Calculation
 Given an idle period Tidle > TBE
 ES(Tidle) = (Tidle - TTR)(POn - POFF) + TTR(POn – PTR)
• POn > PTR: total = idle saving + transition saving
• POn < PTR: total = idle saving - transition cost
 Achievable power saving depends on workload!
 Distribution of idle periods
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Summary
 Hardware support




CMOS power consumption and features
Clock gating
Supply shutdown
Dynamic voltage scaling
 Dynamic power management
 Energy conservation and performance
 Adjusts power mode to adapt to workload variations
 Baseline: greedy policy
 Break-even time TBE
• When PTR ≤ POn
• When PTR > POn
 Energy saving
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Reading
 Textbook: 3.6
 Required: Sections I, II, III.A, III.B, IV of
L. Benini, A. Bogliolo and G. De Micheli, "A Survey of
Design Techniques for System-Level Dynamic Power
Management,” IEEE Transactions on VLSI, pp. 299316, June 2000.
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Announcement & Reminder
 Lab 3 is due today at 5pm
 Midterm statistics
 Class average: 84.8
 90-100: 11
 80-89: 11
 70-79: 4
 <70: 4
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