Reminder
 Lab 2 is due next Wednesday (10/7)
 Bring your work to the lab and demonstrate it to the TA
 The TA will check you off
 Project midterm presentation next Wednesday
(10/7) and Friday (10/9)
 Presentations are in reverse order
• Wed: groups 10-6, Fri: groups 5-1
 8-min presentation + 2-min Q & A
 Your progress on the course project
• System architecture designs, block diagrams, system design
choices
• Midterm report is due before class (minimum 3 pages)
• Send both the midterm report and presentation slides before class
ECE 455/555 Embedded System Design
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Recap from Last Class
 Caches
 Cache mediates between CPU and memory system
 Average memory access time
 Cache replacement policy
 Random
 Least recently used (LRU)
 Cache organizations
 Direct-mapped cache
 N-way set-associative
ECE 455/555 Embedded System Design
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ECE 455/555
Embedded System Design
Memory Systems and Devices
Wei Gao
Fall 2015
3
Memory Management Unit
 Memory size is not large enough for all applications?
 Memory management unit (MMU)
 Provides a larger virtual memory than physical memory
 Translates logical addresses to physical addresses
logical
address
CPU
memory
management
unit
physical
address
ECE 455/555 Embedded System Design
main
memory
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Memory Management Tasks
 Allows programs to move in physical memory during
execution.
 Allows virtual memory:
 memory images kept in secondary storage;
 images returned to main memory on demand during
execution.
 Page fault: request for location not resident in
memory.
ECE 455/555 Embedded System Design
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Address Translation
 Requires some sort of register/table
 To allow arbitrary mappings of logical to physical
addresses.
 To effectively manage memory
 Two basic schemes:
 Segmented: arbitrarily sized region, usually large
 Paged: uniformly sized region, usually small
 How do you cut a cake?
 Segmentation and paging can be combined (x86).
ECE 455/555 Embedded System Design
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Segments and Pages
Page 1
page 1
page 2
segment 1
Segment 1
memory
segment 2
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Segment Address Translation
 MMU maintains a segment register for currently
active segment; logical address is just offset
Segment register
segment base address
logical address
+
segment lower bound
segment upper bound
range
check
range
error
physical address
ECE 455/555 Embedded System Design
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Page Address Translation
 Logical addresses include page number
 Page base address is store in a page table
Logical address
page
offset
page i base
concatenate
Page table
Physical address
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Memory Devices
 Types of memory devices
 RAM (Random-Access Memory)
• Address can be read in any order, unlike magnetic disk/tape
• Usually used for data storage
• DRAM vs. SRAM.
 ROM (Read-Only Memory)
• Usually used or program storage
• Mask-programmed vs. field-programmable.
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Memory Device Organization
 Data stored in a 2-D
array of memory cells
 Address split into row
and column address
 n=r+c
 Enable controls the tri-
stating of data onto the
memory’s pins
 R/W controls the
direction of data
transfer
n
r
Memory array
c
R/W’
Enable
Data
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RAM (Random-Access Memory)
 SRAM (Static RAM)
 Faster, usually used for caches
 Easier to integrate with logic.
 Higher power consumption.
 DRAM (Dynamic RAM)
 Structurally simpler
• Only1 transistor and 1 capacitor are required per bit, compared
with 6 transistors used in SRAM
 Can reach very high density
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Typical Generic SRAM
 CE’ is the chip enable
input. CE’ = 1, data pins are
disabled
 R/W’=1 means the current
operation is read; R/W’=0
means write
 Adrs is the address for read
or write
 Data is a bundle of signals
for data transfer
CE’
a
n
ECE 455/555 Embedded System Design
R/W’
Adrs
Data
SRAM
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Generic SRAM Timing
Read operation
 CE’s is set to 0 to
enable the chip
with R/W’=1
 An address is put
on the address
lines
 After some delay,
data appear on
the data lines
CE’
R/W’
Adrs
Data
From SRAM
read
ECE 455/555 Embedded System Design
From CPU
write time
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Generic DRAM Device
 The interface of DRAM is
more complex
CE’
 To minimize the # of pins
R/W’
 Address line provides
only half of the address
RAS’
 (RAS’) row address select
 (CAS’) column address
select
b
n
CAS’
DRAM
Adrs
Data
ECE 455/555 Embedded System Design
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Generic DRAM Timing
 First, RAS’ is set to 0 and row part of address is on the
address lines
 Next, CAS’ is set to 0 and column part of address is on
CE’
R/W’
RAS’
CAS’
Adrs
row
address
column
address
Data
data
ECE 455/555 Embedded System Design
time
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Page Mode Access of DRAM
 Slower than SRAM, how to improve DRAM performance?
 Supply one row address and many column addresses
 Programs often access several locations in the same memory region
CE’
R/W’
RAS’
CAS’
Adrs
Data
row
adrs
col
adrs
data
col
adrs
data
ECE 455/555 Embedded System Design
col
adrs
data
time
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Read-Only Memory (ROM)
 Factory-programmed ROM
 Not programmable in the lab
 Also called Mask-programmed ROM
 Field-programmable ROM
 Programmable once only
• Cheapest but less flexible (e.g., Antifuse-programmable ROM)
 Re-programmable ROM
• UV-erasable PROM
• Flash PROM
– Modern form of electrically erasable PROM
– Reprogrammed inside a typical system, such as Tmotes
– Can be erased in blocks instead of a whole chip
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Summary
 Caches
 Cache mediates between CPU and memory system
 Average memory access time
 Cache organizations
 Direct-mapped cache
 N-way set-associative
 Memory management: segment/page based
 Memory devices
 RAM (Random Access Memory) vs. ROM (Read-Only
Memory)
 Memory device organization
 SRAM (Static RAM) vs. DRAM (Dynamic RAM)
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Reading
 Textbook: Sections 3.5, 4.4
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