ECE 351
Digital Systems Design
Final Review
Wei Gao
Spring 2016
1
Final Exam




When: Thursday May 5, 8:00am – 10:00am
Where: Min Kao 405
20% of your final grade
What about: Everything covered in this course
 Closed-book, closed-notes, no laptop, no discussion
 All included in class slides (as well as textbook, assigned papers)
 Questions: similar to those in mid-term
• Definitions, designs, computations, etc.
• Programming questions
 Make your answers short to include only key points
• Do answer every question, DON’T leave blank
 Final project report due on May 5 before the final exam
 Return your Basys board and Pmods to the TA before the final exam
 Remember to submit your SAIS review before next Monday,
May 2
ECE 351 Digital Systems Design
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First Half of the Semester
 Design abstraction of digital systems
 Basics of combinatorial logic
 VHDL basics
 Entity, architecture, packages, signal, components, data
types, operators
 VHDL design methodology
 Structural design
 Behavioral design
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Design Abstraction of Digital Systems
 At what level can we design?
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Design Abstraction of Digital Systems
 What does abstraction give us?
 The higher in abstraction we go, the more complex &
larger the system becomes
 But we pass over more details about how it performs
(hardware, speed, fine tuning, etc)
 Where is VHDL?
 System : Chip : Register : Gate
 Describe systems in two ways:
• Structural
• Behavioral
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VHDL: Declare Entities in Port Mode
 Identifies direction of data flow through the port
 All ports must have an identified mode:
entity dumb_circuit is
port ( in1, in2, in3 : in std_logic;
out1, out2 : out std_logic);
end dumb_circuit;
…
out1 <= in1 and in2;
out2 <= out1 or in3;
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VHDL Architecture
 The entity describes the I/O of the device, the
architecture describes what it does/is.
 External interface vs. internal contents
architecture my_architecture_name of my_circuit is
-- declarative section
begin
Entity name for which you
-- activity statements
are describing the
end my_architecture_name;
architecture
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Entity/Architecture Pair
 <= : signal assignment -> wiring
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Component Wiring
 Signals
 We want to interconnect components within an
architecture, we need "signals" to do this
 Define signals within an architecture
Internal "Signal"
External “ports”
Internal "Components"
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Component Instantiation
 After the "begin" keyword, we can start adding
components and connecting signals
 We add components with "Component Instantiation“
 Syntax
label : component-name port map (port => signal, ……) ;
 label: a unique reference designator for that component
 component-name: same as being declared
 the signals with in the ( ) of the port map define how signals are
connected to the ports of the instantiated component
• Component instantiation = connecting signals to the component ports
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Numerical Operators
 Works on types INTEGER, REAL
 The types of the input operands must be the same
 List of operators
• +
"addition“
• "subtraction“
• *
"multiplication“
• /
"division“
• mod "modulus“
• rem “remainder”
• abs
"absolute value“
• **
"exponential"
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Numerical Operators
 Modulus:
 A mod B: A = B*N + (A mod B)
 Has the sign of B and an absoulate value less than that of B
 Remainder:
 A rem B: A = (A/B) * B + (A rem B)
 Has the sign of A and an absolute value less than that of B
 Example:
 5 rem 3 = 2, 5 mod 3 = 2
A mod B = A rem B if A
 (-5) rem 3 = -2, (-5) mod 3 = 1
and B have the same
 (-5) rem (-3)= -2, (-5) mod (-3)= -2
sign
 5 rem (-3)= 2, 5 mod (-3)= -2
 9 rem (-4) = 1 , (-9) mod 4 = 3
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Shift Operators
 List of operators
•
•
•
•
•
•
sll
srl
sla
sra
rol
ror
"shift left logical“
"shift right logical“
"shift left arithmetic“
"shift right arithmetic“
"rotate left“
"rotate right“
 Logical shift: padding with 0
• “1100” sll 1 = “1000”, “1100” srl 2 = “0011” “0101” srl 3 = “0000”
 Arithmetic shift: padding with right-hand/left-hand bit
• “1100” sla 1 = “1000”, “1100” sra 2 = “1111” “0101” sla 2 = “0111”
 Rotate shift: padding with rotated bit
• “1100” rol 1 = “1001”, “1100” ror 2 = “0011” “0111” ror 3 = “1110”
ECE 351 Digital Systems Design
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VHDL Structural Design
 Signals
 We want to interconnect components within an
architecture, we need "signals" to do this
 Define signals within an architecture
Internal "Signal"
External “ports”
Internal "Components"
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VHDL Behavioral Design
 Concurrent domain – architecture
 Describes activities that happen simultaneously
 Component instances, CSAs, processes
 Sequential domain -- within a process
 Describes activities that happen in a defined order similar
to standard programming languages
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Starting and Stopping a Process
 There are two ways to start and stop a process
 Sensitivity list
 Wait statement
 Sensitivity list
 A list of signal names
 The process will begin executing if there is a change on any of the
signals in the list
ex) FLOP : process (clock)
begin
Q <= D;
end process FLOP;
 Each time there is a change on "clock", the process will execute ONCE.
 The process ends after the last statement
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More Examples
good_or : process(a,b)
begin
c <= a or b;
end process good_or;
weird_or : process(b)
begin
c <= a or b;
end process weird_or;
 Process Executes in zero time, and signals are not
updated until the process “suspends”
 Lead to different results produced by the synthesizer!
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Signal vs. Variable

Signal
Variable
has type (type, value, time)
has type (type, value)
assignment with <=
assignment with :=
declared outside of the process
declared in process
assignment takes place
when process suspends
assignment is immediate
always exists
only exists when process executes
Use signals for values go outside of a process -> hardware signals
Use variables to compute values for signals within processes
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State Machine Design
 The steps in a state machine design include
 1) Word Description of the Problem
 2) State Diagram
 3) State/Output Table
 4) State Variable Assignment
 5) Choose Flip-Flop type
 6) Construct F (next state logic)
 7) Construct G (output logic)
 8) Logic Diagram
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State Machine Design
 The steps in a state machine design include
 1) Word Description of the Problem
 2) State Diagram
 3) State/Output Table
 4) State Variable Assignment
 5) Choose Flip-Flop type
 6) Construct F (next state logic)
 7) Construct G (output logic)
 8) Logic Diagram
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Second Half of the Semester
 Medium scale integrated circuits (MSI) design
 Encoder/decoder
 Multiplexer
 Tri-state buffer
 Counters
 Arithmetic operators
 Designs in both structural and behavioral domains!!
 FPGA power analysis
 FPGA timing analysis
 Von Neumann computer architecture
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Integrated Circuit Scaling
 Integrated Circuit Scales
SSI - Small Scale Integrated Circuits
Example
# of Transistors
Individual Gates
10's
MSI - Medium Scale Integrated Circuits MUX, Decoder
100's
LSI - Large Scale Integrated Circuits
RAM, ALU's
1k - 10k
VLSI - Very Large Scale Integrated
Circuits
microprocessors
100k - 1M
ULSI - Ultra Large Scale Integrated
Circuits
Modern
microprocessors
> 1M
SoC - System on Chip
Microcomputers
SoP - System on Package
Different
technology
blending
VLSI: designs that cannot
be done using schematics
or by hand
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Encoder
 An encoder output is a simple OR structure that
looks at the incoming signals
ex)
4-to-2 encoder
I3 I2 I1 I0 Y1 Y0
0 0 0 1 0 0
0 0 1 0 0 1
0 1 0 0 1 0
1 0 0 0 1 1
Y1 = I3 + I2
Y0 = I3 + I1
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Priority Encoders
 A generic encoder does not know what to do when
multiple input bits are asserted
 To handle this case, we need to include prioritization
 If a bit with higher priority is asserted, all the other asserted bits
are shadowed
 We decide the list of priority (usually MSB to LSB) where
the truth table can be written as follows:
ex)
4-to-2 encoder
ECE 351 Digital Systems Design
I3 I2 I1 I0 Y1 Y0
1 x x x 1 1
0 1 x x 1 0
0 0 1 x 0 1
0 0 0 1 0 0
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Implementing Counters
 State machine that produces a straight binary count
 for n-flip-flops, 2n counts can be produced
 The Next State Logic "F" is a combinational SOP/POS circuit
 The speed will be limited by the Setup/Hold and
Combinational Delay of "F“
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Counter Variations
 Ripple counter
 Shift register
 Ring counter
 Johnson counter
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Multiplexer
 Gates are combinational logics which generate an
output depending on the current inputs
 What if we wanted to create a “Digital Switch” to
pass along the input signal?
 This type of circuit is called a “Multiplexer”
ex) truth table of Multiplexer
Sel
0
1
Out
A
B
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Implementation of Multiplexer
 We can use the behavior of an AND gate to build this
circuit:
X∙0 = 0
X∙1 = X
“Block Signal”
“Pass Signal”
 We can then use the behavior of an OR gate at the
output state to combine the signals into one output
 A 0 input has no effect
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Tri-State Buffers
 Example
ex) truth table of Tri-State Buffer
ENB
0
1
Out
Z
In
ex) truth table of Bus Transceiver
Tx/Rx
0
1
ECE 351 Digital Systems Design
Mode
Receive from Bus (Rx)
Drive Bus (Tx)
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Comparators
 A 2-Bit Digital Comparator would look like:
AB
0 0
0 1
1 0
1 1
(A=B)
(A>B)
(A<B)
EQ
1
0
0
1
GT
0
0
1
0
LT
0
1
0
0
EQ = (A⊕B)'
GT = A·B'
LT = A'·B
 Write the output logic first from truth table, then implement
the logic
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Addition – Half Adder
 One bit addition can be accomplished with an XOR gate
(modulo sum 2)
0
+0
0




1
+0
1
0
+1
1
1
+1
10
Notice that we need to also generate a “Carry Out” bit
The “Carry Out” bit can be generated using an AND gate
This type of circuit is called a “Half Adder”
It is only “Half” because it doesn’t consider a “Carry In”
bit
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Addition – Full Adder
 To create a full adder, we need to include the “Carry In”
in the Sum
Cin A B
0 0 0
0 0 1
0 1 0
0 1 1
1 0 0
1 0 1
1 1 0
1 1 1
Cout
0
0
0
1
0
1
1
1
Sum
0
1
1
0
1
0
0
1
Sum = A ⊕ B ⊕ Cin
Cout = Cin∙A + A∙B + Cin∙B
 You could also use two "Half Adders" to accomplish the
same thing
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Addition – Ripple Carry Adder
 Cascading full adders together will allow the Cout’s
to propagate through the circuit
 This configuration is called a Ripple Carry Adder
Sum = A ⊕ B ⊕ Cin
Cout = Cin∙A + A∙B + Cin∙B
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Ripple Carry Subtractor
 In a ripple carry subtractor, intermediate Bout's are
fed into Bin's, which is a double inversion
Addition
Subtraction
S = A ⊕ B ⊕ Cin
Cout = A∙B + A∙Cin + B∙Cin
D = A ⊕ B' ⊕ Bin'
Bout' = A∙B' + A∙Bin' + B'∙Bin'
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"Shift and Add" Multipliers
 Example of Binary Multiplication using our "by hand" method
11
x 13
33
11
+
1 4 3
1011
x
1101
1011
0000
1011
+1011
10001111
- multiplicand
- multiplier
- these are the individual multiplicands
- the final product is the sum of all multiplicands
 This is simple and straight forward. BUT, the addition of the
individual multiplicand products requires as many as n-inputs.
 We would really like to re-use our Full Adder circuits, which
only have 3 inputs.
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Division
 Division - "Shift and Subtract"
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Process Technology Types
 SRAM
 In-system programmable and
re-programmable
 Requires external boot PROM
 System cache
 Xilinx, Altera, Lattice, Atmel
 Antifuse
 One-time programmable
 Programmable Logic Devices (PLDs) and structured ASICs
 Actel, QuickLogic/Aeroflex
 Flash
 Flash-erase EPROM, reprogrammable
(some in-system programmable)
 System BIOS
 Lattice, Actel
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Types of Power
 Startup
 SRAM devices have startup transients but flash and
antifuse do not
 Static
 Increases exponentially with temperature
 Dynamic
 Design-Specific
 When both transistors in a logic gate are temporarily
turned on during switching, get very small current surge.
With millions of transistors...
 P = f * C * V^2 ( Each component power = frequency *
capacitive load * voltage swing squared)
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Reducing Power Consumption
 Make sure you have the details of the power
constraints
 Power restriction and/or current limit?
 Device always running or low duty cycle?
 Think about overall architecture
 i.e. Could the microprocessor be put into the FPGA?
 Lower Clock Frequency
 Split clock domains
 Gate clock
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Setup / Hold Time
 Data on “D” of Flipflop must be present at “setup
time” before clock edge, and remain on “D” for “hold
time” after clock edge.
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Review: Combinatorial Delay
Combinatorial Logic introduces
a delay, output of this logic
could be moving around during this time
Time difference between time when D
input is stable till time that D input is
required to be stable is called slack, i.e.
clk period – delay = slack
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Timing Variables
 Temperature
 Propagation time through logic elements is increased with
increasing temperature
 Supply Voltage
 Propagation time through logic elements is decreased with
increasing voltage
 Process Variation
 Timing is affected by variations in the silicon, resistance,
capacitance of routing grid, etc.
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Timing Hazards
 If this is used as the control input to a state machine,
what could happen?
 Ensure synchronous design
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Metastability
When transition on D occurs NOT ONLY within the setup/hold window, but
within the much smaller window of time where the flop “accepts” new
data, flipflop may be in an illegal state for indefinite period of time
 Could theoretically be infinite amount of time before state resolves to
legal state. Practically there is enough noise to push it one way or the
other.
 Still, resolution time will be variable, and events with longer resolution
times are possible, but their likelihood decreases exponentially with time.
 𝑀𝑀𝑀𝑀𝑀𝑀𝑀𝑀 = 𝑒𝑒 𝐾𝐾2 𝑡𝑡 /(𝐾𝐾1 � 𝐹𝐹𝑐𝑐𝑐𝑐𝑐𝑐𝑐𝑐𝑐𝑐 � 𝐹𝐹𝑑𝑑𝑑𝑑𝑑𝑑𝑑𝑑 )

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Block Diagram of the Central Processing
Unit (CPU)
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Processing Unit
 Registers within the processing unit
 Instruction Registers (IR)
• Holds the Opcode that is read from memory
• Passes the Opcode to the Control Unit as a test signal
 Memory Address Register (MAR)
• Holds the current address being sent to memory
 Program Counter (PC)
• Tracks the address of which instruction is being executed
• MAR tracks PC when executing instruction
 ALU Operand Register (Z)
• Holds one of the inputs to the ALU
• The other input comes from one of the user-controlled registers
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Control Unit Sub-Operations
 1. Fetch
 2. Decode
 3. Fetch operands
 4. Execute
 5. Store results
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Von Neumann Bottleneck
 We have seen that the von Neumann computer is
serial in its execution of instructions
 This is good for simplicity, but can limit performance
 There are many techniques to improve the
performance of this computer
 Functional Timing
 Memory Architecture
 Algorithmic Branch Prediction
 Pipelines
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