Announcements
 Announcement of Lab 4
 Operation and implementation of PS/2 interface on Basys2
board
 Each student checks out one PS/2 mouse from the TA
• Return the mouse back after completion of Lab 4
 Due Monday 4/4 6pm
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Recap from the last class
 Implementing the basic system components of MSI
using VHDL
 Combinatorial logic
 Structural model vs. behavioral model
 Encoder
 Multiplexer / Demultiplexer
 Tri-state buffer
 Comparator
 Iterative vs. non-iterative
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ECE 351
Digital Systems Design
Medium Scale Integrated Circuits - 2
Wei Gao
Spring 2016
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Implementing Counters in MSI
 Special name of any clocked sequential circuit whose
state diagram is a circle
 There are many types of counters, each suited
for particular applications
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1. Binary Counter
 State machine that produces a straight binary count
 for n-flip-flops, 2n counts can be produced
 The Next State Logic "F" is a combinational SOP/POS circuit
 The speed will be limited by the Setup/Hold and
Combinational Delay of "F“
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2. Toggle Flop
 A D-Flip-Flop can product a "Divide-by-2" effect by
feeding back Qn to D
 This topology is also called a "Toggle Flop"
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3. Ripple Counter
 Cascaded Toggle Flops can be used to form rippled
counter
 There is no Next
State Logic
 Slower than
a straight binary
counter due to
waiting for
the "ripple“
 This is good for
low power,
low speed apps
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4. Synchronous Counter with ENABLE
 Sn enable can be included in a "Synchronous" binary counter
using Toggle Flops
 The enabled is implemented by AND'ing the Q output prior to the next
toggle flop
 This gives us the "ripple" effect, but also gives the ability to run
synchronously
 A little faster, but still less gates than a straight binary circuit
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5. Shift Register
 A chain of D-Flip-Flops that pass data to one another
 This is good for
"pipelining“
 Also good for
Serial-to-Parallel
conversion
 For n-flip-flops,
the data is present
at the final state
after n clocks
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6. Ring Counter
 Feeding the output of a shift register back to the
input
 Also called a
"One Hot“
 The first flip-flop
needs to reset to
1, while the
others reset to 0
 For n flip-flops,
there will be n
counts
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7. Johnson Counter
 Feeding the inverted output of a shift register back to
the input
 This gives more
states with the
same reduced
gate count
 All flip-flops can
reset to 0
 For n flip-flops,
there will be 2n
counts
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Counters in VHDL
 Strong type casting in VHDL can make modeling counters
difficult
 The reason for this is that the STANDARD and STD_LOGIC
Packages do not define "+", "-", or inequality operators for
BIT_VECTOR or STD_LOGIC_VECTOR types
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Counters in VHDL
 IEEE Packages
 STD_LOGIC
 STD_LOGIC_UNSIGNED
 STD_LOGIC_ARITH
 Use the STD_LOGIC_UNSIGNED Package
 This package defines "+" and "-" functions for





STD_LOGIC_VECTOR
We can use +1 just like normal
The vector will wrap as suspected (1111 - 0000)
One catch is that we can't assign to a Port
We need to create an internal signal of STD_LOGIC_VECTOR for
counting
We then assign to the Port at the end
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Counters in VHDL
 Using STD_LOGIC_UNSIGNED
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity counter is
Port ( Clock
Reset
Direction
Count_Out
end counter;
-- call the package
: in STD_LOGIC;
: in STD_LOGIC;
: in STD_LOGIC;
: out STD_LOGIC_VECTOR (3 downto 0));
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Counters in VHDL
 Using STD_LOGIC_UNSIGNED
architecture counter_arch of counter is
signal count_temp : std_logic_vector(3 downto 0);
begin
process (Clock, Reset)
begin
if (Reset = '0') then
count_temp <= "0000";
elsif (Clock='1' and Clock'event) then
if (Direction='0') then
count_temp <= count_temp + '1';
else
count_temp <= count_temp - '1';
end if;
end if;
end process;
Count_Out <= count_temp;
end counter_arch;
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Counters in VHDL
 Use integers for the counter and then convert back
to STD_LOGIC_VECTOR
 STD_LOGIC_ARITH is a Package that defines a conversion




function
The function is: conv_std_logic_vector (ARG, SIZE)
Functions are defined for ARG = integer, unsigned, signed,
STD_ULOGIC
SIZE is the number of bits in the vector to convert to, given
as an integer
We need to keep track of the RANGE and Counter
Overflow
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Counters in VHDL
 Using STD_LOGIC_ARITH
use IEEE.STD_LOGIC_ARITH.ALL;
entity counter is
Port ( Clock
Reset
Direction
Count_Out
end counter;
-- call the package
: in STD_LOGIC;
: in STD_LOGIC;
: in STD_LOGIC;
: out STD_LOGIC_VECTOR (3 downto 0));
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Counters in VHDL
 Using STD_LOGIC_ARITH
architecture counter_arch of counter is
signal count_temp : integer range 0 to 15;
begin
process (Clock, Reset)
begin
if (Reset = '0') then
count_temp <= 0;
elsif (Clock='1' and Clock'event) then
if (count_temp = 15) then
count_temp <= 0;
else
count_temp <= count_temp + 1;
end if;
end if;
end process;
Count_Out <= conv_std_logic_vector (count_temp, 4);
end counter_arch;
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Pros and Cons
 Using integers allows a higher level of abstraction
and more functionality can be included
 Easier to write unsynthesizable code or code that
produces unwanted logic
 Both are synthesizable when written correctly
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Ring Counters in VHDL
 To mimic the shift register behavior, we need access to the
signal value before and after clock'event
 Consider the following concurrent architecture ….
begin
signal assignments:
 Since they are executed
concurrently, it is equivalent to
end architecture…
Q0=Q1=Q2=Q3, or a simple wire
ECE 351 Digital Systems Design
Q0 <= Q3;
Q1 <= Q0;
Q2 <= Q1;
Q3 <= Q2;
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Ring Counters in VHDL
 Since a process doesn't assign the signal values until it
suspends, we can use this to model the "before and
after" behavior of a clock event.
process (Clock, Reset)
begin
if (Reset = '0') then
Q0<='1'; Q1<='0'; Q2<='0'; Q3<='0';
elsif (Clock'event and Clock='1') then
Q0<=Q3; Q1<=Q0; Q2<=Q1; Q3<=Q2;
end if;
end process
 notice that the signals DO NOT appear in the sensitivity list. If
they did the process would continually execute and not be
synthesized as a flip-flop structure
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Johnson Counters in VHDL
process (Clock, Reset)
begin
if (Reset = '0') then
Q0<='0';
Q1<='0'; Q2<='0'; Q3<='0';
elsif (Clock'event and Clock='1') then
Q0<=not Q3;
Q1<=Q0; Q2<=Q1; Q3<=Q2;
end if;
end process
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Multiple Processes
 We can now use State Machines to control the
start/stop/load/reset of counters
 They are independent processes that interact with
each other through signals
 A common task for a state machine is:
 1) at a certain state, load and enable a counter
 2) go to a state and wait until the counter reaches a certain
value
 3) when it reaches the certain value, disable the counter
and continue to the next state
 Since the counter runs off of a clock, we know how
long it will count between the start and stop
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Summary
 An important category of VHDL program is
implementation of counters
 Binary counter
 Ripple counter
 Shift register
 Ring/Johnson counters
 Implementing counters in VHDL
 Choices of using different packages
 Pros and cons
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