ECE 351
Digital Systems Design
Midterm Review
Wei Gao
Spring 2016
1
Midterm Exam



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When: Tuesday (3/8) 5:00 – 7:00pm
Where: Min Kao 405
15% of your final grade
What about: Everything from the beginning of class
 10 questions, each of which may have 1-3 subquestions
• Definitions, designs, computations, etc.
 Closed-book, closed-notes, no laptop, no discussion
 All included in class slides (as well as textbook, assigned
papers)
 Make your answers short to include only key points
• Don’t leave ANY question as blank
• Try to write whatever you can remember or imagine
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Combinatorial Digital Logic
 Used in computer circuits to perform Boolean
Algebra
 Practical computer circuits contain a mixture of
combinatorial and sequential logic
 Produce specific output from given inputs
 Two implementation methods
 A sum of products (SOP)
 A product of sums (POS)
 Visualized using truth table
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Using SOP and POS interchangably
 SOP and POS expressions are equivalent
SOP Expression :
f(a,b) = a’·b + a·b’
is equal to
POS Expression :
f(a,b) = (a+b) · (a'+b')
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Design Abstraction of Digital Systems
 At what level can we design?
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Design Abstraction of Digital Systems
 What does abstraction give us?
 The higher in abstraction we go, the more complex &
larger the system becomes
 But we pass over more details about how it performs
(hardware, speed, fine tuning, etc)
 Where is VHDL?
 System : Chip : Register : Gate
 Describe systems in two ways:
• Structural
• Behavioral
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VHDL Basics
 1. Entity
 2. Architecture
 3. Packages
 4. Signal
 5. Components
 6. Data types
 7. Operators
 8. Generics & constants
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1. VHDL: Entity-based language
 Entity: unit in digital circuit design
 A entity describes the name of the unit, its ports,
and the types and directions of those ports
 Port: an entry into or out of the design entity
• Communicate with other entities via ports
 Example
entity my_circuit is
port (
a : in std_logic;
b : in std_logic;
c: out std_logic );
end my_circuit;
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Port Mode
 Identifies direction of data flow through the port
 All ports must have an identified mode:
entity dumb_circuit is
port ( in1, in2, in3 : in std_logic;
out1, out2 : out std_logic);
end dumb_circuit;
…
out1 <= in1 and in2;
out2 <= out1 or in3;
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2. Architecture
 The entity describes the I/O of the device, the
architecture describes what it does/is.
 External interface vs. internal contents
architecture my_architecture_name of my_circuit is
-- declarative section
begin
Entity name for which you
-- activity statements
are describing the
end my_architecture_name;
architecture
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Entity/Architecture Pair
 <= : signal assignment -> wiring
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3. VHDL Packages
 Adding on functionality
 VHDL allows us to define our own data types and
operators
 A set of types, operators, functions, procedures… is called
a "Package“
 A set of packages are kept in a "Library"
 Analogy
 Built-in keywords/operators vs. customized functions in
C/C++
 Header files
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Common IEEE Packages
 In the IEEE library, there are common Packages that
we use
 STD_LOGIC_1164
 STD_LOGIC_ARITH
 STD_LOGIC_SIGNED
library
use
use
use
IEEE;
IEEE.STD_LOGIC_1164.ALL;
IEEE.STD_LOGIC_ARITH.ALL;
IEEE.STD_LOGIC_SIGNED.ALL;
 Libraries are defined before the entity declaration
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4. VHDL Signal
 A single bit is considered a Scalar quantity
 A bus (or multiple bits represented with one name) is
called a Vector
 In VHDL, we can define a signal bus as:
data_bus
or
data_bus
: in bit_vector (7 downto 0);
: in bit_vector (0 to 7);
 The Most Significant Bit (MSB) is ALWAYS on the left of
the range description:
 data_bus : in bit_vector (7 downto 0);
• data_bus(7) = MSB
 data_bus : in bit_vector (0 to 7);
• data_bus(0) = MSB
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VHDL Signal
 There are "Internal" and "External" signals
 Internal - are within the Entity's Interface
 External - are outside the Entity's Interface and connect it
to other systems
 Where do you declare internal and external signals?
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5. Component Declarations
 Now include the pre-existing entities "xor2" & "or2"
into our "TOP" design
entity TOP is
port (A,B,C
X
end entity TOP;
: in
: out
STD_LOGIC;
STD_LOGIC);
architecture TOP_arch of TOP is
component xor2
port (In1, In2 : in
STD_LOGIC;
Out1
: out
STD_LOGIC);
end component;
The port declarations
should match
component or2
port (In1, In2 : in
STD_LOGIC;
Out1
: out
STD_LOGIC);
end component;
begin
-- declaration of xor2 component
-- declaration of or2 component
…..
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Component Wiring
 Signals
 We want to interconnect components within an
architecture, we need "signals" to do this
 Define signals within an architecture
Internal "Signal"
External “ports”
Internal "Components"
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Component Instantiation
 After the "begin" keyword, we can start adding
components and connecting signals
 We add components with "Component Instantiation“
 Syntax
label : component-name port map (port => signal, ……) ;
 label: a unique reference designator for that component
 component-name: same as being declared
 the signals with in the ( ) of the port map define how signals are
connected to the ports of the instantiated component
• Component instantiation = connecting signals to the component ports
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6. VHDL Data Types
 Scalar data types (built into VHDL)
 Scalar means that the type only has one value at any given
time
 Boolean: values TRUE or FALSE
• NOT 0 or 1!!!
 Character: values are all symbols in the 8-bit ISO8859-1 set
 Integer: the range comes from +/- 232
• 4 bytes for each integer
• What about C/C++?
 Real: values are fractional numbers from -1.0E308 to
+1.0E308
 Bit: values {'0', '1'}
• Used for logic gates
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VHDL Data Types
 Array Data Types (Built into VHDL)
 Bit vector
• Vector of bits, values {'0', '1'}
• Array values are represented with double quotes (i.e., "0010")
• This type can be used for logic gates: signal assignments
• First element of array has index=0
 String
• Vector of characters
Message
: string (1 to 10) := "message here…"
• First element in array has index=1
• E.g.:
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7. VHDL Operators
 Data types define both "values" and "operators"
 Each data type is only associated to a specific set of
operators
• Integer: +/-/…
• Boolean/bit: AND/OR/….
 There are "Pre-Determined" data types
 Pre-determined = Built-In = STANDARD Package
 We can add additional types/operators by including other
Packages
 We'll first start with the STANDARD Package that comes
with VHDL
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Numerical Operators
 Works on types INTEGER, REAL
 The types of the input operands must be the same
 List of operators
• +
"addition“
• "subtraction“
• *
"multiplication“
• /
"division“
• mod "modulus“
• rem “remainder”
• abs
"absolute value“
• **
"exponential"
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Numerical Operators
 Modulus:
 A mod B: A = B*N + (A mod B)
 Has the sign of B and an absoulate value less than that of B
 Remainder:
 A rem B: A = (A/B) * B + (A rem B)
 Has the sign of A and an absolute value less than that of B
 Example:
 5 rem 3 = 2, 5 mod 3 = 2
A mod B = A rem B if A
 (-5) rem 3 = -2, (-5) mod 3 = 1
and B have the same
 (-5) rem (-3)= -2, (-5) mod (-3)= -2
sign
 5 rem (-3)= 2, 5 mod (-3)= -2
 9 rem (-4) = 1 , (-9) mod 4 = 3
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Shift Operators
 List of operators
•
•
•
•
•
•
sll
srl
sla
sra
rol
ror
"shift left logical“
"shift right logical“
"shift left arithmetic“
"shift right arithmetic“
"rotate left“
"rotate right“
 Logical shift: padding with 0
• “1100” sll 1 = “1000”, “1100” srl 2 = “0011” “0101” srl 3 = “0000”
 Arithmetic shift: padding with right-hand/left-hand bit
• “1100” sla 1 = “1000”, “1100” sra 2 = “1111” “0101” sla 2 = “0111”
 Rotate shift: padding with rotated bit
• “1100” rol 1 = “1001”, “1100” ror 2 = “0011” “0111” ror 3 = “1110”
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8. VHDL Generics & Constants
 It is very useful to be able to design using
variables/parameters instead of hard coded values
 ex) width of bus, delay, loop counters, etc
 VHDL Provides two methods for this functionality
 1) Generics
 2) Constants
 Similar but have subtle differences
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VHDL Design Methodology
 We can specify the functionality in an architecture in
two ways
 Structural design: text based schematic, manual
instantiation of another system
• Re-presentation of the system architecture
• Consists of components, signals, ports, etc
• Wiring via signal assignments
• Suitable for describing combinatorial logic
 Behavioral design: abstract description of functionality
• Procedural description of system functionality
• Consists of processes, structural system statements
• Suitable for describing sequential logic
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VHDL Structural Design
 Signals
 We want to interconnect components within an
architecture, we need "signals" to do this
 Define signals within an architecture
Internal "Signal"
External “ports”
Internal "Components"
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Generate Statement
 There are times when we want to instantiate a large
number of the same component (ex. on a bus)
 VHDL has a "generate" statement that allows us to
instantiate multiple components using a loop
structure
 Syntax:
label : for identifier in range generate
component instantiation
end generate;
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Generate Statement
 Example: instantiate 8 inverters assuming X and Y are
busses of equal width
 X, Y: bit vector
begin
Gen1 : for i in 1 to 8 generate
U1 : INV1 port map ( In1=>X(i), Out1=>Y(i) );
end generate;
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Behavioral VHDL Design
 We've learned the basic constructs of VHDL
 Entity, architecture, packages, etc
 We've learned how to use structural VHDL to
instantiate lower-level systems and to create textbased schematics
 Now we want to go one level higher in abstraction
and design using "Behavioral Descriptions" of HW
 When we design at the Behavioral level, we now rely on
Synthesis tools to create the ultimate gate level schematic
• We don’t directly instantiate hardware components, but let the
synthesizer understand our specification and do the job!
 We need to be aware of what we CAN and CAN'T synthesis
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VHDL Domains
 Concurrent domain – architecture
 Describes activities that happen simultaneously
 Component instances, CSAs, processes
 Sequential domain -- within a process
 Describes activities that happen in a defined order similar
to standard programming languages
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Starting and Stopping a Process
 There are two ways to start and stop a process
 Sensitivity list
 Wait statement
 Sensitivity list
 A list of signal names
 The process will begin executing if there is a change on any of the
signals in the list
ex) FLOP : process (clock)
begin
Q <= D;
end process FLOP;
 Each time there is a change on "clock", the process will execute ONCE.
 The process ends after the last statement
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More Examples
good_or : process(a,b)
begin
c <= a or b;
end process good_or;
weird_or : process(b)
begin
c <= a or b;
end process weird_or;
 Process Executes in zero time, and signals are not
updated until the process “suspends”
 Lead to different results produced by the synthesizer!
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Signals in Processes
 Rules of a Process
 Signals cannot be declared inside of a process
 Assignment to a signal takes effect only after the process suspends
• Until it suspends, signals keeps their previous value
 Only the last signal assignment to a signal in the list has an effect
• There's no use making multiple assignments to the same signal.
DOIT : process (A,B)
begin
A <= '0';
B <= '0';
Y <= A+B;
end process DOIT;
-- initially A=2, B=2… then A changes to 7
Y=? 7+2 not 7+0
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Signal vs. Variable

Signal
Variable
has type (type, value, time)
has type (type, value)
assignment with <=
assignment with :=
declared outside of the process
declared in process
assignment takes place
when process suspends
assignment is immediate
always exists
only exists when process executes
Use signals for values go outside of a process -> hardware signals
Use variables to compute values for signals within processes
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Sequential Statements in VHDL
 If/then/else
 Case statements
 Loop in VHDL
 Range attributes
 for i in vec’range loop
• visits elements in the array from left to right
 for i in vec’reverse_range loop
• in reverse order in which they were specified
 for i in vec’low to vec’high loop
• low to high, regardless of how they were specified
 Exit statement
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Latching in Case Statements
 What if some possible choices are not included in the case
statement?
show_latch : process(sel,a,b)
begin
case sel is
when “00” =>
nibble_out <= a(3 downto 0);
when “01” =>
nibble_out <= a(7 downto 4);
when “10” =>
nibble_out <= b(3 downto 0);
end case;
end process show_latch;
when sel is not one of the three choices
nibble_out stays the same regardless of
changing a,b
 Straightforward solution: when others
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Latch Inference
case sel is
end case;
when “00” =>
nibble_out <= a(3 downto 0);
when “01” =>
nibble_out <= a(7 downto 4);
when “10” =>
nibble_out <= b(3 downto 0);
FlipFlop: process
Disable when “11”
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Synchronous Design
 In a purely synchronous system, all flip-flops in the
design are clocked by the same clock.
 All the system components are globally synchronized
 Asynchronous Preset / Clear are not used except for
initialization
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Setup/Hold Time
 Describe the timing requirements on the data input
of a flip-flop or register with respect to the clock
input
 Setup time (T1): the length of time that the data must be
available and stable before the active clock edge.
 Hold time (T2): the length of time that the data to be
clocked into the flip-flop must remain available and stable
after the active clock edge. T1 T2
Input
Clock
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Input Synchronization
 Synchronize asynchronous inputs to system so that
entire system can be designed in a synchronous
manner
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FSM Representation
 From XST user guide:
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State Machine Design
 The steps in a state machine design include
 1) Word Description of the Problem
 2) State Diagram
 3) State/Output Table
 4) State Variable Assignment
 5) Choose Flip-Flop type
 6) Construct F (next state logic)
 7) Construct G (output logic)
 8) Logic Diagram
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General Picture of State Machine Design
Process 1
Case current_state is
when idle =>
next_state <= grab_data;
when grab_data =>
next_state <= wait_ack;
when wait_ack =>
if go_pulse = ‘1’ then
next_state <= send_data;
else
next_state <= abort;
end if;
… etc.
Process 2
If reset = ‘1’ then
current_state <= idle;
Elsif rising_edge(clk) then
current_state <= next_state
End if;
Process 3
Signal_sending <= ‘1’ when current_state = send_data else ‘0’;
Machine_ready <= ‘1’ when current_state = idle else ‘0’;
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State Encoding
type traffic_states is (red, yellow, green, fl_yellow, f_red, turn_arrow );
signal current_state, next_state : traffic_states;
 Sequential states: encodes the states as binary
numbers
 000, 001, 010, 011, 100, 101
 Is this the only way of encoding?
 Encoding options
 One-hot encoding
 Compact encoding
 Gray encoding
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State Encoding
 Why might state encoding make a difference?
 Speed: combinatorial decode of the state variable to
determine outputs and next state can be made simpler via
one-hot for instance.
 State transitions: if combinatorial decode of output is
desired to have no glitches, the encoding makes a
difference.
 Size: how many FF’s are
required to represent all
your states?
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Illegal States
 Given our states: (red,yellow,green,fyellow,fred,turn_arrow)
 000, 001, 010, 011, 100, 101
 If they are encoded as above, we have 2 illegal states
 Undefined in FSM
 What will logic do when those states are encountered?
case current_state is
when red => next_State <= turn_arrow;
when turn_arrow => next_state <= green;
when green => next_state <= yellow….
…etc.
 We don’t really know…
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Dealing with Illegal States
 Consequences of illegal state entering is unknown, but
frequently result is “wedged” machine, which doesn’t
recover
 The system will stuck once entering an illegal state
 Faulty Reset Circuitry (or none) could have you power-up
in an illegal state
 The initial system state would be random!
 Single-Event-Upsets in radiation environments can cause
a flop to toggle, leaving your state machine in an illegal
state
 Synchronization Errors on inputs
 Setup/hold violation
 Metastability
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