Reminders
 Lab 2 is due Tuesday, Feb 23 at 5pm
 Show up at the lab and let the TA check out your results
 We will announce Lab 3 next Tuesday
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Recap from last class
 Latching
 Unspecified conditions in case statements
 Latch inference by synthesizer
 Storage elements
 Registers
 D-FlipFlops
 Synchronous design
 Setup/hold time
 Clock stew
 Example: 2-digit decimal counter
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ECE 351
Digital Systems Design
Behavioral VHDL Design - 3
Wei Gao
Spring 2016
3
Example: 2-digit Decimal Counter
 Use of registers and FlipFlops
 Count 2 digits in decimal, for simple display to a 2-
digit LED screen.
 Display: ldigit and mdigit, 4 bit each
entity bcdctr is
port ( clk : in std_logic;
reset : in std_logic;
en : in std_logic;
bcd : out std_logic_vector(
7 downto 0)
);
end bcdctr;
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Architecture Design
architecture behavior of bcdctr is
signal mdigit : std_logic_vector(3 downto 0);
signal ldigit : std_logic_vector(3 downto 0);
begin
lcnt : process(clk,reset)
begin
if reset = ‘0’ then
ldigit <= “0000”;
elsif rising_edge(clk) then
if en = ‘1’ then
if ldigit = “1001” then
ldigit <= “0000”;
else ldigit <= ldigit +
“0001”;
end if;
end if;
end if;
end process lcnt;
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Architecture Design
mcnt : process (clk,reset)
begin
if reset='0' then
mdigit <= "0000";
elsif clk='1' and clk'event then
if (ldigit="1001") and (en='1') then
if mdigit = “1001” then
mdigit <= “0000";
else mdigit <= mdigit + “0001”;
end if;
end if;
end if;
end process mcnt;
bcd(3 downto 0) <= ldigit;
bcd(7 downto 4) <= mdigit;
end behavior;
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State Machines
 Finite State Machines (FSM) are a key tool of logic
design
 State memory: D-FlipFlops
 A synthesizer can perform state optimization on
FSMs to minimize the circuit
area / delay
 This optimization is only available
if the FSM model fits templates
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Worked Example
 Smart battery charger
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Mealy Machine
 Outputs depend on states AND inputs
 Input change causes an immediate output change
 Asynchronous signals
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Moore Machine
 Outputs are functions solely of the current state
 Outputs change synchronously with state changes
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State Machine Design
 The steps in a state machine design include
 1) Word Description of the Problem
 2) State Diagram
 3) State/Output Table
 4) State Variable Assignment
 5) Choose Flip-Flop type
 6) Construct F (next state logic)
 7) Construct G (output logic)
 8) Logic Diagram
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Hello-World Example: Sequence Detector
 1) Design a machine by hand that takes in a serial bit
stream and looks for the pattern “1011”.
 When the pattern is found, a signal called “Found” is
asserted
 You must store and recall the historic
system state
 2) State diagram
 If pattern is invalidated, restart from the
beginning
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Hello-World Example: Sequence Detector
 3) State/output table
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Hello-World Example: Sequence Detector
 4) State (Binary) Variable Assignment
 5) Choose Flip-Flop Type
 99% of the time we use D-Flip-Flop
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Hello-World Example: Sequence Detector
 6) Construct Next State Logic “F”
In
0
 Q1* = Q1’∙Q0∙In’ + Q1∙Q0’∙In
Q1
Q1 Q0
00
0
0
1
In
0
1
2
3
01
1
0
6
7
11
0
0
4
5
10
0
1
Q0
In
0
 Q0* = Q0’∙In
0
1
In
ECE 351 Digital Systems Design
Q1
Q1 Q0
1
00
0
1
2
3
01
0
0
6
7
Q0
11
0
0
4
5
10
0
1
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Hello-World Example: Sequence Detector
 7) Construct Output Logic “G”
In
 Found = Q1∙Q0∙In
0
00
0
1
In
Q1
Q1 Q0
1
0
0
2
3
01
0
0
6
7
11
0
1
4
5
10
0
0
Q0
 8) Logic Diagram
 For large designs, this becomes impractical
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State Machines in VHDL
 1. State memory
 2. Next state logic “F”
 3. Output logic “G”
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Summary
 State machines
 Mealy machine
 Moore machine
 State machine design steps
 Hello-world example: sequence detector
 State machine in VHDL
 State memory
 Next state logic
 Output logic
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