Course Project
 Clarifications on project document submissions
 Project document is required for each phase of the project
• Follow the format of academic research paper
• Two-column IEEE format
 Project midterm report
• High-level description of the technical approach
• Details of some of the system components
• > 3 pages
 Project final report
• Every technical details of the project
• Experimental results
• > 7 pages
 Check out your pMods from the TA and start working
 Let me know ASAP if you need any additional pMods
 Ordering may take time
ECE 351 Digital Systems Design
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Recap of Last Class
 Process execution
 Start & stop
 Only update signals when process suspends
 Signals vs. variables
 Update at different times
 Used in different places
 Variable operations
 If/then statements
 Case statements
 Looping syntax
 Dynamic range attributes
 Exit statement
 White loop
ECE 351 Digital Systems Design
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ECE 351
Digital Systems Design
Behavioral VHDL Design - 2
Wei Gao
Spring 2016
3
Storage Elements
 Storage is described behaviorally by conditionally
defining the value of a signal (or variable) for only a
subset of the possible conditions.
 For example:
 Latch: “Copy the input to the output (only) when the
enable signal is high”
 Register: “Copy the input to the output (only) when there
is a rising edge on a clock signal”
ECE 351 Digital Systems Design
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Recall Case Statements
 Example: a 2-to-1 MUX
architecture mux_2to1_arch of mux_2to1 is
begin
MUX : process (A,B,Sel)
begin
case (Sel) is
when '0'
=> Out1 <= A;
when '1'
=> Out1 <= B;
when others
=> Out1 <= A;
end case;
end process MUX;
end architecture mux_2to1_arch;
ECE 351 Digital Systems Design
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Latching in Case Statements
 What if some possible choices are not included in the case
statement?
show_latch : process(sel,a,b)
begin
case sel is
when “00” =>
nibble_out <= a(3 downto 0);
when “01” =>
nibble_out <= a(7 downto 4);
when “10” =>
nibble_out <= b(3 downto 0);
end case;
end process show_latch;
when sel is not one of the three choices
nibble_out stays the same regardless of
changing a,b
 Straightforward solution: when others
ECE 351 Digital Systems Design
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Latch Inference (Synthesis)
 1) Synthesizer detects signals which are to be latched
 Those that aren’t assigned new value under every
condition
 nibble_out
 2) Extract the set of conditions that cause each signal
to be assigned a value, and use the or of those
conditions to enable the latch
 “00” or “01” or “10”
 3) Done on each signal independently, so each
process can have a mixture of combinational and
latched outputs.
ECE 351 Digital Systems Design
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Latch Inference (Synthesis)
 4) Synthesizers typically have a limit of complexity for
which they can analyze for latching.
 5) For simplicity and clarity specify latching when
desired very clearly:
if en=‘1’ then
if sel=‘0’ then z<= a;
else z<= b;
end if
end if;
ECE 351 Digital Systems Design
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Illustrating Latch Inference
case sel is
end case;
when “00” =>
nibble_out <= a(3 downto 0);
when “01” =>
nibble_out <= a(7 downto 4);
when “10” =>
nibble_out <= b(3 downto 0);
Disable when “11”
ECE 351 Digital Systems Design
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Registers (FlipFlops)
 synthesizer recognizes this
template and will happily
build a D-Flop for us.
process (clk)
begin
if clk=‘1’ and clk’event then
Q <= D;
end if;
end process;
Either rising or falling
edge of clock signal
ECE 351 Digital Systems Design
Edge-triggered
D type FlipFlop
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D-Flop Variants
process (clk)
begin
if (clr = ‘0’) then
Q<=‘0’;
elsif rising_edge(clk) then
Q <= D;
end if;
end process;
ECE 351 Digital Systems Design
Another
enabling signal
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D-Flop Variants
process (clk)
begin
if (clr = ‘0’) then
Q<=‘0’;
elsif rising_edge(clk) then
if E = ‘1’ then
Q <= D;
end if;
end if;
end process;
ECE 351 Digital Systems Design
Double enabling
signals
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Synchronous Design
 In a purely synchronous system, all flip-flops in the
design are clocked by the same clock.
 All the system components are globally synchronized
 Asynchronous Preset / Clear are not used except for
initialization
ECE 351 Digital Systems Design
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Typical Synchronous System
ECE 351 Digital Systems Design
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Synchronous System Issues
 Why Synchronous Logic?
 We can reduce the millions of steps of analysis and timing
verification of our system to a few manageable ones:
 1. What is the maximum clock frequency that design can
run at?
• Logic propagation delay + setup time
• Synthesizer’s job
 2. Clock stew
 3. Identify limited asynchronous inputs and deal
accordingly
ECE 351 Digital Systems Design
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Setup/Hold Time
 Describe the timing requirements on the data input
of a flip-flop or register with respect to the clock
input
 Setup time (T1): the length of time that the data must be
available and stable before the active clock edge.
 Hold time (T2): the length of time that the data to be
clocked into the flip-flop must remain available and stable
after the active clock edge. T1 T2
Input
Clock
ECE 351 Digital Systems Design
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Clock Stew
If flops u32 and u33 get clocked
significantly earlier than U34,
the value in U33 may be lost,
since by the time U34 is clocked
to take U33’s old data, U33’s
new data has already made it to
its Q output.
ECE 351 Digital Systems Design
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Clock Stew
ECE 351 Digital Systems Design
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Global Clock buffers
 Xilinx provides hardware resources to guarantee
negligible clock-skew for a limited number of clocks
 Signals for these buffers
come in on special pins
or are buffered from the
logic via special cell.
 Global clocks are limited
in number by the
hardware
ECE 351 Digital Systems Design
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Input Synchronization
 Synchronize asynchronous inputs to system so that
entire system can be designed in a synchronous
manner
ECE 351 Digital Systems Design
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Example: 2-digit Decimal Counter
 Use of registers and FlipFlops
 Count 2 digits in decimal, for simple display to a 2-
digit LED screen.
 Display: ldigit and mdigit, 4 bit each
entity bcdctr is
port ( clk : in std_logic;
reset : in std_logic;
en : in std_logic;
bcd : out std_logic_vector(
7 downto 0)
);
end bcdctr;
ECE 351 Digital Systems Design
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Architecture Design
architecture behavior of bcdctr is
signal mdigit : std_logic_vector(3 downto 0);
signal ldigit : std_logic_vector(3 downto 0);
begin
lcnt : process(clk,reset)
begin
if reset = ‘0’ then
ldigit <= “0000”;
elsif rising_edge(clk) then
if en = ‘1’ then
if ldigit = “1001” then
ldigit <= “0000”;
else ldigit <= ldigit +
“0001”;
end if;
end if;
end if;
end process lcnt;
ECE 351 Digital Systems Design
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Architecture Design
mcnt : process (clk,reset)
begin
if reset='0' then
mdigit <= "0000";
elsif clk='1' and clk'event then
if (ldigit="1001") and (en='1') then
if mdigit = “1001” then
mdigit <= “0000";
else mdigit <= mdigit + “0001”;
end if;
end if;
end if;
end process mcnt;
bcd(3 downto 0) <= ldigit;
bcd(7 downto 4) <= mdigit;
end behavior;
ECE 351 Digital Systems Design
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Summary
 Latching
 Unspecified conditions in case statements
 Latch inference by synthesizer
 Storage elements
 Registers
 D-FlipFlops
 Synchronous design
 Setup/hold time
 Clock stew
 Example: 2-digit decimal counter
ECE 351 Digital Systems Design
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Reading Assignment
 Textbook Chapter 17
ECE 351 Digital Systems Design
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