Reminders
 Lab 1 is due today at 5pm
 Show up at the lab and let the TA check out your results
 Project proposal presentation this Thursday 2/11
 Submit your 1-page proposal document AND presentation
slides by 2/11 before class
 Each group will have 8 minutes for presentation and 2-3
minutes for Q&A
 Announcement of Lab 2
 Single-port Block RAM
 Due Tuesday 2/23
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Recap from last class
 VHDL Generics and constants
 “marcos” for convenient program reconfiguration
 Global vs. local variables
 Supported types: integer, time
 Values may need to be initialized in advance
 Illustrative example: decoder design
 Use fundamental functional blocks through components
 Declare internal signals appropriately
 Behavioral design overview
 Concept of process
ECE 351 Digital Systems Design
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ECE 351
Digital Systems Design
Behavioral VHDL Design - 1
Wei Gao
Spring 2016
3
Process
 A series of sequential statements that must be
executed in order
 Syntax
name : process (sensitivity list)
Specify when to execute
the process
declarations
begin
sequential statements
end process name;
Variables valid only within
the process
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Process Execution
 Real systems start on certain conditions
 They then perform an operation
 They then wait for the next start condition
ex)
Button pushed?
Clock edge present?
Reset?
Change on Inputs?
 To mimic real HW, we want to be able to START and STOP
processes
 Otherwise, the simulation would get stuck in an infinite
loop or "hang”
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Process Execution
 Processes execute in Sequence
 These are NOT concurrent
 Difficult to describe hardware
ex)
name : process (sensitivity list)
begin
sequential statement;
sequential statement;
sequential statement;
end process name;
ECE 351 Digital Systems Design
Sequential signal
assignments
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Starting and Stopping a Process
 There are two ways to start and stop a process
 Sensitivity list
 Wait statement
 Sensitivity list
 A list of signal names
 The process will begin executing if there is a change on any of the
signals in the list
ex) FLOP : process (clock)
begin
Q <= D;
end process FLOP;
 Each time there is a change on "clock", the process will execute ONCE.
 The process ends after the last statement
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More Examples
good_or : process(a,b)
begin
c <= a or b;
end process good_or;
weird_or : process(b)
begin
c <= a or b;
end process weird_or;
 Process Executes in zero time, and signals are not
updated until the process “suspends”
 Lead to different results produced by the synthesizer!
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Wait Statements
 The keyword "wait" can be used inside of a process to
start/stop it
 The process executes the sequences 1-by-1 until hitting the
wait statement
 We don't use "waits" and "sensitivity lists" together
DOIT : process
Begin
statement 1;
statement 2;
statement 3;
end process DOIT;
DOIT : process
Begin
statement 1;
statement 2;
wait;
end process DOIT;
(No Start/Stop Control, loops
forever)
(w/ Start/Stop Control, executes until
"wait" then stops)
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Wait Statements
 We need to have a conditional operator associated
with the wait statement, otherwise it just stops the
process and it will never start again
 The wait statements can be followed by keywords "for" or
"until" to describe the wait condition
 The wait statement can wait for:
 1) type-expression
 2) condition
ex) wait for 10ns;
wait for period/2;
ex) wait until Clock='1‘;
wait until Data>16;
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Signals in Processes
 Rules of a Process
 Signals cannot be declared inside of a process
 Assignment to a signal takes effect only after the process suspends
• Until it suspends, signals keeps their previous value
 Only the last signal assignment to a signal in the list has an effect
• There's no use making multiple assignments to the same signal.
DOIT : process (clk, A,B)
begin
A <= '0';
B <= '0';
Y <= A+B;
end process DOIT;
-- initially A=7, B=2
Y=? 7+2 not 7+0
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Signals in Processes
 What if we need this behavior?
DOIT : process (A,B)
begin
A <= '0';
B <= '0';
Y <= A+B;
end process DOIT;
-- initially A=7, B=2
-- we WANT A to be assigned '0'
-- we WANT B to be assigned '0'
-- we WANT Y to be assigned A + B = 0
 We need something besides a Signal to hold the
interim value
 We use “variables”
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Variables
 Allow us to assign values during the sequence of
statements
 Signals in processes are only assigned their value when the
process suspends
 Variables are defined within a process
 Assignments to variables are made using ":=" instead
of "<=“
 Used in generics & constants
 Assignments take place immediately
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Variables
 Example
DOIT : process (A,B) -- a change on A or B will trigger this process
variable temp : integer := 0;
begin
temp := 2;
B <= temp + 1; B=? 2+1 not 0+1
end process DOIT;
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Signal vs. Variable

Signal
Variable
has type (type, value, time)
has type (type, value)
assignment with <=
assignment with :=
declared outside of the process
declared in process
assignment takes place
when process suspends
assignment is immediate
always exists
only exists when process executes
Use signals for values go outside of a process -> hardware signals
Use variables to compute values for signals within processes
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Variable Operations
 If / Then Statements
 Used ONLY within a process
 VHDL has the following:
• - if, then
• - if, then, else
• - if, then, elsif, then
• - if, then, elsif, then, else
 Logical operators allowed in Boolean Expression
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If/Then Statements

Example: a 2-to-1 MUX
architecture mux_2to1_arch of mux_2to1 is
begin
MUX : process (A,B,Sel)
begin
if (Sel = '0') then
Out1 <= A;
elsif (Sel = '1') then
Out1 <= B;
else
Out1 <=A;
-- this isn't necessary, just for illustration
end if;
end process MUX;
end architecture mux_2to1_arch;
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Case Statements
 Example: a 2-to-1 MUX
architecture mux_2to1_arch of mux_2to1 is
begin
MUX : process (A,B,Sel)
begin
case (Sel) is
when '0'
=> Out1 <= A;
when '1'
=> Out1 <= B;
when others
=> Out1 <= A;
end case;
end process MUX;
end architecture mux_2to1_arch;
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Case Statements
 Used ONLY within a process
 Better for larger input combinations, If/Then's can
get too long
 Works nice on vectors
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Looping in Process
 Usually used to operate vectors
 Index used as vector pins
 Basic use is similar to normal programming language
 Example:
For i in 7 downto 0 loop
if (a(i) = '0') then
Count_Aux := Count_Aux + 1;
Count_Aux: variable
end if;
end loop;
Count <= Count_Aux; Count: signal
 Not necessary to define i
 Implicit definition as integer
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Range Attributes
 Specifying loop bounds explicitly is very inflexible
when traversing through a vector
 for i in vec’range loop
 visits elements in the array from left to right
 for i in vec’reverse_range loop
 in reverse order in which they were specified
 for i in vec’low to vec’high loop
 low to high, regardless of how they were specified
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Range Attributes
 Example
process (a)
begin
end process;
Count_Aux := "000";
for i in a’range loop
if (a(i) = '0') then
Count_Aux := Count_Aux + 1;
end if;
end loop;
Count <= Count_Aux;
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Exit Statement
 Analogous to “break” in C++
 Example
for i in vec'reverse_range loop
exit when vec(i) = '1';
result := result + "00001";
end loop;
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While Loop Syntax
 Must have defined range at compile time to be synthesized
process(vec)
variable result : std_logic_Vector(4 downto 0) := “00000”;
variable i : integer := 0;
begin
while i< 16 loop
exit when vec(i) = '1';
result := result + 1;
i := i + 1;
end loop;
count <= result;
end process;
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Summary
 Process execution
 Start & stop
 Only update signals when process suspends
 Signals vs. variables
 Update at different times
 Used in different places
 Variable operations
 If/then statements
 Case statements
 Looping syntax
 Dynamic range attributes
 Exit statement
 White loop
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Announcement of Lab 2
 Write VHDL code and implement on Basys2 board
the single-port Block RAM with 8 addresses and 16bit words
 Use signal initialization (0xFFFF, 0xEEEE, …) for the BRAM
 Built-in signal in architecture
 Alternative methods: use TEXTIO or CORE GENERATOR
 Implement a 3-bit cyclic up-counter to single-step
through the addresses with debounced BTN0.
 Step through BRAM addresses and display the word
as 4 HEX digits on 7-segment displays.
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Announcement of Lab 2
 Lab 2 is due Feb 23rd 5:00pm
 You need to work on your own
 No collaboration is allowed on ALL labs
 You need to have the TA to check off your code
during the lab hours
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