ECE351
DigitalSystemsDesign
ExperimentalEnvironmentSetup
WeiGao
Spring2016
1
DigilentBasys2Spartan-3EFPGABoard
§  XilinxSpartan3-EFPGA
§  JTAGprogrammingvia
on-boardUSB2port
§  Programmingenvironment
§  ISEWebPACKDesignSoKware
•  YourVHDLprogrammingIDE
•  hRp://www.xilinx.com/support/download.html
§  ADEPTsoKwaretocommunicatewiththeFPGAboard
•  hRp://www.digilenWnc.com/Products/Detail.cfm?
NavPath=2,66,828&Prod=ADEPT2
ECE351DigitalSystemsDesign
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ProgrammingEnvironment
§  ISEWebpack
§  v14.1isinstalledoncomputersinMK224
§  Bothversions14.1and14.7workforBasys2boards
§  RequestfreepersonallicensesfromDigilentwebsite
§  Vivado
§  DoesnotsupportSpartan-3FPGAs
§  Support7-seriesFPGAs:Virtex-7,Kintex-7,ArWx-7,etc
•  Basys3boards
§  YouneedtorequestlicensesfromITstaff
§  Vivado2014.4isinstalledoncomputersinMK224
§  Otherplaces
§  Programmingclinic(MK416)
§  StudentOrganizaWonsSuite(MK217)
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ProgrammingFlow
ECE351DigitalSystemsDesign
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ISEWebpack
§  CreateyourownVHDLproject
§  Family:Spartan3E
§  Device:XC3S100E
§  Package:CP132
§  Step1:generatetheVerilog(.v)file(textfile)
§  Step2:generatetheTestBenchandrunsimulaWon
§  Step2:generatetheconfiguraWonfile(.ucf)
§  Step3:“Synthesize”:checkforerrors
§  Step4:“Implementdesign”:compileyourVHDLcode
§  Step5:“GenerateProgrammingFile”:generate
the.bitfiletobeuploadedtotheFPGAboard
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ADEPTSoCware
§  AutomaWcallydetecttheconnectedFPGAboard
§  Self-containedtesWngprogram
§  Uploadthe.bitfiletotheFPGAboard
§  MoredetailedinstrucWoncouldbefoundat:
§  hRp://web.calstatela.edu/faculty/cliu/EE244/BASys2/EE
%20244%20Tutorial%20for%20programming%20the
%20BASYS.pdf
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Recapoflastclass
§  Architecture
§  ImplementaWonofenWWes
§  OpWonalitems
§  Packages
§  Adding-onfuncWonality
§  IEEEpackages:standards
§  Datatypes
Scalar
Array
Physical
User-defined
§  STD_LOGIC
§
§
§
§
ECE351DigitalSystemsDesign
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ECE351
DigitalSystemsDesign
VHDLOperatorsandSignal
Assignment
WeiGao
Spring2016
8
VHDLOperators
§  Datatypesdefineboth"values"and"operators"
§  Eachdatatypeisonlyassociatedtoaspecificsetof
operators
•  Integer:+/-/…
•  Boolean/bit:AND/OR/….
§  Thereare"Pre-Determined"datatypes
§  Pre-determined=Built-In=STANDARDPackage
§  WecanaddaddiWonaltypes/operatorsbyincludingother
Packages
§  We'llfirststartwiththeSTANDARDPackagethatcomes
withVHDL
ECE351DigitalSystemsDesign
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LogicalOperators
§  WorksontypesBIT,BIT_VECTOR,BOOLEAN
§  Bitvectorsmustbesamelength
§  Theresultisalwaysthesametypeastheinput
§  Listofoperators
•  NOT
•  AND
•  NAND
•  OR
•  NOR
•  XOR
•  XNOR
§  Recall:anANDgate
§  Out1<=In1ANDIn2
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NumericalOperators
§  WorksontypesINTEGER,REAL
§  Thetypesoftheinputoperandsmustbethesame
§  Listofoperators
•  +
"addiWon“
•  -
"subtracWon“
•  *
"mulWplicaWon“
•  /
"division“
•  mod "modulus“
•  rem “remainder”
•  abs "absolutevalue“
•  **
"exponenWal"
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NumericalOperators
§  Modulus:
§  AmodB:A=B*N+(AmodB)
§  HasthesignofBandanabsoulatevaluelessthanthatofB
§  Remainder:
§  AremB:A=(A/B)*B+(AremB)
§  HasthesignofAandanabsolutevaluelessthanthatofB
§  Example:
§  5rem3=2,5mod3=2
AmodB=AremBifA
§  (-5)rem3=-2,(-5)mod3=1
andBhavethesame
§  (-5)rem(-3)=-2,(-5)mod(-3)=-2
sign
§  5rem(-3)=2,5mod(-3)=-1
1
3
§  9rem(-4)=,(-9)mod4=
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RelaSonalOperators
§  Usedtocompareobjects
§  Objectsmustbeofsametype
§  OutputisalwaysBOOLEAN(TRUE,FALSE)
§  Worksontypes:BOOLEAN,BIT,BIT_VECTOR,CHARACTER,
INTEGER,REAL,TIME,STRING
§  Listofoperators:
•  =
•  /=
•  <
•  <=
•  >
•  >=
"equal“
"notequal“
"lessthan“
"lessthanorequal“
"greaterthan“
"greaterthanorequal"
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ShiCOperators
§  Worksonone-dimensionalarrays
§  WorksonarraysthatcontaintypesBIT,BOOLEAN
§  Theoperatorrequires
•  1)AnOperand
•  2)NumberofShiKs
(whatistobeshiKed)
(specifiedasanINTEGER)
§  AnegaWvenumberofshiKsisvalidandreversesthe
direcWonoftheshiK
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ShiCOperators
§  Listofoperators
•
•
•
•
•
•
sll
srl
sla
sra
rol
ror
"shiKleKlogical“
"shiKrightlogical“
"shiKleKarithmeWc“
"shiKrightarithmeWc“
"rotateleK“
"rotateright“
§  LogicalshiK:paddingwith0
•  “1100”sll1=“1000”,“1100”srl2=“0011” “0101”srl3= “0000”
§  ArithmeWcshiK:paddingwithright-hand/leK-handbit
•  “1100”sla1=“1000”,“1100”sra2=“1111” “0101”sla2= “0111”
§  RotateshiK:paddingwithrotatedbit
•  “1100”rol1=“1001”,“1100”ror2=“0011” “0111”ror3=“1110”
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ConcatenaSonOperator
§  Combinesobjectsofsametypeintoanarray
§  Theorderispreserved
§  &:concatenate
§  Example:New_Bus<=(Bus1(7:4)&Bus2(3:0))
§  Workonbothscalarandarraydatatypes
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STD_LOGIC_1164Operators
§  ToexpandthedatatypeswehaveinVHDL,we
includetheIEEEPackage"STD_LOGIC_1164“
§  Thisgivesusthedatatypes
§  STD_LOGIC
§  STD_LOGIC_VECTOR
§  Thisgivesusallofthenecessaryoperatorsforthese
types
§  Logical,Numerical,RelaWonal,ShiK
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AssignmentOperators
§  Theassignmentoperatoris<=
§  TheResultsisalwaysontheLeK,Operandsonthe
Right
§  Typesneedtoallbeofthesametype
§  Needtowatchthelengthofarrays!
§  Examples
§  a<=borc
§  Out1<=In1sla2
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DelayedSignalAssignments
§  DelayModeling
§  VHDLallowsustoincludeWminginformaWoninto
assignmentstatements
§  Thisgivesustheabilitytomodelreal-worldgatedelay
§  Weusethekeyword"aKer"inourassignmentfollowedby
aWmeoperand.
•  Ex)B<=notAaKer2ns;
Time:Non-synthesizablephysical
datatype
§  VHDLhastwotypesofWmingmodelsthatallowmore
accuraterepresentaWonofrealgates
•  1)InerWalDelay(default)
•  2)TransportDelay
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InerSalDelay
§  IftheinputhastwoedgetransiWonsinlessWmethan
theinerWaldelay,thepulseisignored
§  Iftheinputpulsewidthissmallerthanthedelay,itis
ignored
§  Thismodelsthebehavioroftryingtochargeupthegate
capacitanceofaMOSFET
ex)B<=AaKer5ns;
anypulseslessthan5nsinwidthareignored.
ECE351DigitalSystemsDesign
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TransportDelay
§  Transportdelaywillalwayspassthepulse,nomaRer
howsmallitis.
§  Thismodelsthebehavioroftransmissionlines
§  Wehavetoexplicitlycalloutthistypeofdelayusingthe
"transport"keyword
ex) B<=transportAaKer5ns;
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Summary
§  VHDLoperators
§  Logicoperators
§  Numericaloperators:modrem
§  RelaWonaloperators
§  ShiKoperators:logical,arithmeWc,rotate
§  ConcatenaWonoperator
§  Assignmentoperator
§  Signalassignment
§  Delayedassignments:inerWalvs.transportdelay
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Reading
§  Textbook2.4-2.5
§  AusefulonlineVHDLencyclopedia
§  hRp://www.csee.umbc.edu/portal/help/VHDL/
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