ECE 351
Digital Systems Design
Digital Logic Review
Wei Gao
Spring 2016
1
Combinatorial Digital Logic
 Used in computer circuits to perform Boolean
Algebra
 Practical computer circuits contain a mixture of
combinatorial and sequential logic
 Produce specific output from given inputs
 Write Boolean expressions from the truth table
 Two implementation methods
 A sum of products (SOP)
 A product of sums (POS)
 Visualized using truth table
ECE 351 Digital Systems Design
2
Boolean Expressions using SOP
 Summation of all minterms resulting in the truth
table
 Minterm: expression for an input configuration which
yields a TRUE output
 AND’ing all inputs 1s
Truth Table
ab
out
00
0
01
1
10
1
11
0
minterm m1 = a’·b
minterm m2 = a·b’
 SOP expression: f(a,b) = a’·b + a·b’
ECE 351 Digital Systems Design
3
Boolean Expressions using POS
 multiplication of all maxterms resulting in the truth
table
 Maxterm: expression for an input configuration which
yields a FALSE output
 OR’ing all inputs 0s
Truth Table
ab
out
00
0
01
1
10
1
11
0
maxterm m0 = a+b
maxterm m3 = a'+b’
 POS Expression : f(a,b) = (a+b) · (a'+b')
ECE 351 Digital Systems Design
4
Using SOP and POS interchangably
 SOP and POS expressions are equivalent
SOP Expression :
f(a,b) = a’·b + a·b’
is equal to
POS Expression :
f(a,b) = (a+b) · (a'+b')
ECE 351 Digital Systems Design
5
Combinatorial Logic Gates
 Output depends on the logic value of the inputs
 Priority: NOT>AND>OR
 No storage or “state”
 Stateful: sequential logic
ECE 351 Digital Systems Design
6
Combinatorial Logic Gates
NOT
out = in’ = in f(in) = in’ = in
OR
out = a+b
f(a,b) = a+b
AND
out = a·b
f(a,b) = a·b
ECE 351 Digital Systems Design
7
Combinatorial Logic Gates
XOR
out = a⊕b
f(a,b) = a⊕b
NOR
out = a+b
f(a,b) = a+b
NAND
out = a·b
f(a,b) = a·b
ECE 351 Digital Systems Design
8
DeMorgan’s Theorem
 Inverting the output of any gate results in the same
function as the opposite gate (AND/OR) with
inverted inputs
ECE 351 Digital Systems Design
9
Sequential Logic
 Concept of “Storage Element”
 With Storage, logic functions can depend on current & past
values of inputs
 Sequential State Machines can be created
 D-Flip-Flop
 On timing event (i.e., edge of clock input), D input goes to
Q output
CLK
D
Q
Q
D
Q
Q
tc2q
ECE 351 Digital Systems Design
10
State Machine
 2-bit counter
00
01
1) Number of States?
2) Number of bits to encode states?
:4
: 2n=4, n=2
For this counter, we can make the outputs be the state codes
11
10
ECE 351 Digital Systems Design
11
State Machine Implementation
 2-bit Gray Code Counter
00
01
11
STATE
Current Next
Acur Bcur
Anxt Bnxt
0
0
1
1
0
1
1
0
0
1
1
0
Anxt Logic
Bnxt Logic
Bcur
0 1
Acur 0
1
1
1
0
0
Bcur
0 1
0
1
0
1
Acur 0
1
10
A
B
A
Q
1
0
0
Bnxt = Acur’
Anxt = Bcur
D
1
D
counter
output
Q
B
Q
Q
CLK
ECE 351 Digital Systems Design
12
ECE 351
Digital Systems Design
VHDL Overview
Wei Gao
Spring 2016
13
Entity-based language
 Entity: unit in digital circuit design
 A entity describes the name of the unit, its ports,
and the types and directions of those ports
 Port: an entry into or out of the design entity
• Communicate with other entities via ports
 Example
entity my_circuit is
port (
a : in std_logic;
b : in std_logic;
c: out std_logic );
end my_circuit;
ECE 351 Digital Systems Design
14
Signal values
 IEEE 1164 standard defines nine values for a digital
signal:
 1: logic value 1
 0: logic value 0
 U: unitialized
 Z: high impedance
 X: forcing unknown
 W: weak unknown
 L: weak 0
 H: weak 1
 “-”: don’t care
ECE 351 Digital Systems Design
15
Port Mode
 Identifies direction of data flow through the port
 All ports must have an identified mode:
ECE 351 Digital Systems Design
16
Port Example
entity dumb_circuit is
port ( in1, in2, in3 : in std_logic;
out1, out2 : out std_logic);
end dumb_circuit;
…
out1 <= in1 and in2;
out2 <= out1 or in3;
out1 is being “read” – not
allowed!
 This is where mode “buffer” is useful
 If out1 was declared in the entity as “buffer” instead of “out”,
there would be no error
 Cause other problems though -> avoid the use of buffer mode
ECE 351 Digital Systems Design
17
std_logic_vector
 std_logic_vector is simply an array where each
element is of type std_logic.
entity mux2x8 is
port ( bus_a : in std_logic_vector(7 downto 0);
bus_b : in std_logic_vector(7 downto 0);
sel : in std_logic
bus_out : out std_logic_vector(7 downto 0));
end mux2x8;
 In the architecture, individual bits can be referred to :
bus_out(7) <= bus_a(7) when sel = ‘0’ else bus_b(7);
 The whole bus can be assigned to with a bitstring:
bus_out <= “11110000”;
ECE 351 Digital Systems Design
18
Architecture
 The entity describes the I/O of the device, the
architecture describes what it does/is.
 External interface vs. internal contents
architecture my_architecture_name of my_circuit is
-- declarative section
begin
Entity name for which you
-- activity statements
are describing the
end my_architecture_name;
architecture
ECE 351 Digital Systems Design
19
Describing architecture practically
 Of what pieces is it composed, and how are they
connected?
 The architecture is described by defining its sub-
elements and how they are put together.
ECE 351 Digital Systems Design
20
Describing architecture practically
ECE 351 Digital Systems Design
21
Describing architecture practically
 How does it respond to inputs, what do its outputs do?
 Clock description:
 Verbal description:
The entity cnt3bit behaves in such a way that each rising edge of the incoming
clock, the outputs cnt2-0 will update such that the next value of cnt2-0 will be
the previous value of those outputs + 1, where cnt0 is considered the LSB, and
cnt2 is considered the MSB of a 3-bit unsigned binary number. Additionally,
when our output vector reaches 7 (111) it will wrap around to 000 on the next
clock.
 VHDL description????
ECE 351 Digital Systems Design
22
Entity/Architecture Pair
 <= : signal assignment -> wiring
ECE 351 Digital Systems Design
23
Conditional signal assignment
 Same syntax as regular signal assignment, multiple
branches allowed
conditional_out <= a when
sel1 = '0'
else
b when sel2 = '1'
else
a xor b when sel3 = '0‘
else
not b;
Must end with
unconditioned else
ECE 351 Digital Systems Design
24
Conditional signal assignment
 Some synthesizers will be smart enough to realize
that conditions are independent
Z<= a when sel = ‘1’ else
b when sel = ‘0’ else
c;
ECE 351 Digital Systems Design
25
Behavioral vs. Structural
 VHDL supports both means of describing
architecture, and both means will be useful
 Even in the same architecture…
 Structural VHDL
 Helps break down a design into subsections for ease of
understanding, and design
 Instantiate user defined
models, or built-in macros
that are product specific
(forfeit technology
independence)
ECE 351 Digital Systems Design
26
Summary
 Digital logic review
 Boolean expressions using SOP/POS
 Combinatorial logic gates
 DeMorgan’s theorem
 Sequential logic & state machine
 VHDL review
 Entity vs. architecture
 Port mode
 Signal values
 Describing architecture: signal assignment
 Behavioral vs. structural VHDL
ECE 351 Digital Systems Design
27