AN ABSTRACT OF THE DISSERTATION OF
Zhimin Li for the degree of
Doctor of Philosophy in
Electrical and Computer Engineering presented
on January 27, 2006.
Title: Design of a 14-bit Continuous-Time Delta-Sigma A/D Modulator
with 2.5MHz Signal Bandwidth
Abstract approved:
Terri S. Fiez
In recent years, there has been growing interest in both industry and
academia to use continuous-time (CT) Δ-Σ A/D converters for wideband wireless
and wireline communication applications.
So far no reported CT Δ-Σ A/D modulator achieves 14-bit or higher
dynamic range (DR) with more than 2MHz signal bandwidth (equivalently 4MS/s).
This dissertation presents the realization of a continuous-time (CT) Δ-Σ A/D
modulator providing 80.5dB SNDR and 85dB DR with 5MS/s output data rate in a
2.5V 0.25µm CMOS process. The modulator has a single-stage dual-loop
architecture allowing large quantizer delay. A 17-level quantizer is used to increase
resolution and non-return-to-zero DACs are adopted to reduce clock jitter
sensitivity. Capacitor tuning is utilized to overcome time-constant variation. Onchip self-calibration is implemented to suppress DAC nonlinearity. Combining
techniques to address various design challenges, the modulator consumes 50mW
with 60MHz sampling rate.
© Copyright by Zhimin Li
January 27, 2006
All Rights Reserved
Design of a 14-bit Continuous-Time Delta-Sigma A/D Modulator with
2.5MHz Signal Bandwidth
by
Zhimin Li
A DISSERTATION
submitted to
Oregon State University
in partial fulfillment of
the requirements for the
degree of
Doctor of Philosophy
Presented January 27, 2006
Commencement June 2006
Doctor of Philosophy dissertation of Zhimin Li
presented on January 27, 2006.
APPROVED:
Major Professor, representing Electrical and Computer Engineering
Director of the School of Electrical Engineering and Computer Science
Dean of the Graduate School
I understand that my dissertation will become part of the permanent collection of
Oregon State University libraries. My signature below authorizes release of my
dissertation to any reader upon request.
Zhimin Li, Author
ACKNOWLEGEMENTS
I highly appreciate the many people who have made important contribution
to this research work and who have made my life in Oregon State University an
enjoyable and unforgettable experience. In particular, I would like to express my
sincere appreciation to my advisor, Dr. Terri Fiez, for her consistent technical and
financial support on my study and research in OSU, for her constant confidence
and encouragement, and for her guidance in writing papers/thesis and making
presentations.
I would like to thank Dr. Jim Coakley for his time and kindness by serving
on my program committee.
I gained great benefits from the classes offered by Dr. Gábor Temes, Dr.
Kartikeya Mayaram and Dr. Un-Ku Moon. I also thank them for serving on my
program committee and for their valuable suggestions during the meetings for my
Ph.D. program.
I am very grateful to Dr. Bertan Bakkaloglu, who opened door to CT Δ-Σ
A/D converters to me when I interned at Texas Instruments.
I am indebted to Cheeboon Law for his help on designing the initial version
of the DAC circuits. I sincerely thank James Ayers, Triet Le, Thomas Brown,
Minfang Su, Xuhan Xie and all other current and former members in the AMS
group for their help and friendship. Among them, Robert Batten, Ruoxin Jiang and
Madhu Chennam deserve special recognition for their contributions to this work.
Robert offered numerous valuable suggestions during every stage of my research.
His help was particularly essential and indispensable when I designed the PCB and
measured my chip. He was even not free of my disturbing when he was far away in
Newfoundland for vacation. Ruoxin and Madhu, though have left OSU for a few
years, always kindly and patiently answered my phone calls to discuss my technical
questions.
I am grateful for the many fruitful discussions with fellow students in EECS,
especially José Silva, Jipeng Li, Xuesheng Wang, Pavan Hanumolu, Min-Gyu Kim,
Gil-Cho Ahn and Jie Fang.
I would like to thank Ferne Simendinger, Sarah O’Leary, Morgan Garrison,
Clara Knutson, Brian Lindsay and Tina Batten for their smiles and warm hearts to
me whenever I walked into ECE office for help.
I am grateful to Todd Shechter, for his patient and timely help on any
computer hardware/software problems I have encountered.
I appreciate Dr. Jim Hellums and Mr. John Muza for offering me internship
opportunities at Texas Instruments and their technical guidance to me during my
time at TI. The nine-month internship has given me very valuable experience in
industry.
I would like to acknowledge the support of CDADIC (Center for the Design
of Analog-Digital Integrated Circuits), Texas Instruments and DARPA on this
project.
Finally, I would like to thank my wife, Qing Yang, and my whole family for
their unconditional love, support and encouragement during my sixty-four months
of PhD studying.
TABLE OF CONTENTS
Page
1. INTRODUCTION ...............................................................................................1
1.1 Motivation ......................................................................................................1
1.2 Dissertation Organization ..............................................................................3
2. OVERVIEW OF OVERSAMPLING Δ-Σ A/D CONVERTERS........................5
2.1 A brief introduction to Δ-Σ A/D converters...................................................5
2.2 Common architectures for Δ-Σ A/D converters .............................................9
2.2.1 Single-stage topology............................................................................9
2.2.2 Multi-stage topology ...........................................................................12
3. CONTINUOUS-TIME Δ-Σ A/D MODULATOR LOOP FILTER DESIGN ...15
3.1 Transformation of a DT Δ-Σ modulator to a CT Δ-Σ modulator .................15
3.2 Inherent anti-aliasing filtering......................................................................21
4. NON-IDEALITIES IN OVERSAMPLING Δ-Σ A/D MODULATORS ..........26
4.1 OpAmp non-idealities ..................................................................................26
4.1.1 OpAmp in DT integrators ...................................................................26
4.1.2 OpAmp in CT integrators....................................................................28
4.2 Quantizer non-idealities ...............................................................................31
4.2.1 Quantizer delay ...................................................................................31
4.2.2 Comparator offset ...............................................................................34
4.2.3 Comparator hysteresis.........................................................................35
4.2.4 Comparator metastability ....................................................................36
4.3 Clock Jitter ...................................................................................................36
4.3.1 Clock jitter in DT modulators .............................................................36
4.3.2 Clock jitter in CT modulators with rectangular DAC shapes .............37
4.3.3 Clock jitter in CT modulators with non-rectangular DAC shapes......44
TABLE OF CONTENTS (Continued)
Page
4.4 Multi-bit DAC element mismatch................................................................46
4.5 Loop filter coefficient variation ...................................................................51
4.6 Comparison between DT and CT Δ-Σ A/D modulators ..............................51
4.6.1 Implementation ...................................................................................51
4.6.2 Low voltage operation ........................................................................52
4.6.3 Operation speed...................................................................................52
4.6.4 Power consumption.............................................................................52
4.6.5 Anti-aliasing filter requirement...........................................................53
4.6.6 Clock jitter sensitivity .........................................................................53
4.6.7 Sensitivity to process variation ...........................................................53
4.6.8 Loop filter scalability with clock frequency .......................................54
5. SYSTEM LEVEL DESIGN...............................................................................55
5.1 Modulator topology......................................................................................55
5.1.1 Modulator order and number of quantizer levels................................55
5.1.2 Choice of DAC pulse shape ................................................................57
5.1.3 Loop filter architecture........................................................................59
5.2 Time constant variation................................................................................65
5.3 Multi-bit DAC mismatch .............................................................................66
6. CIRCUIT AND LAYOUT LEVEL DESIGN ...................................................69
6.1 Loop filter design .........................................................................................69
6.2 First stage R-C integrator .............................................................................70
6.2.1 The OpAmp in the R-C integrator ......................................................71
6.2.2 Modulator front-end noise analysis.....................................................73
6.3 Gm-C transconductor design .......................................................................76
6.4 DAC with current calibration.......................................................................79
TABLE OF CONTENTS (Continued)
Page
6.4.1 Charge injection ..................................................................................81
6.4.2 Clock feedthrough...............................................................................81
6.4.3 Glitch at source node of M4 and M5 ..................................................81
6.4.4 Low jitter clock generation .................................................................84
6.5 Summing block ............................................................................................85
6.6 Sample and hold...........................................................................................86
6.7 Quantizer ......................................................................................................89
6.8 Output driver ................................................................................................93
6.9 Clock generator ............................................................................................93
6.10 Time constant tuning..................................................................................95
6.11 Layout design considerations.....................................................................97
7. TEST SETUP AND EXPERIMENTAL RESULTS .......................................100
7.1 Test board design .......................................................................................100
7.2 Test environment setup ..............................................................................102
7.3 Measurement results ..................................................................................103
7.4 Comparison between this work and reported designs................................108
8. CONCLUSION................................................................................................111
8.1 Summary ....................................................................................................111
8.2 Future work ................................................................................................112
BIBLIOGRAPHY..................................................................................................114
APPENDICES .......................................................................................................120
Appendix A: Map loop filter HC(s) to single-stage dual-loop coefficients......121
LIST OF FIGURES
Figure
Page
1.1 Number of papers on Δ-Σ A/D converters in ISSCCs. ........................................2
2.1 Block diagram of an oversampling A/D converter. .............................................5
2.2 Basic architecture of a Δ-Σ A/D modulator. ........................................................6
2.3 Linearized Δ-Σ A/D Model. .................................................................................7
2.4 A general Δ-Σ A/D modulator structure...............................................................9
2.5 Δ-Σ A/D modulator with CIFF single-stage topology. ......................................10
2.6 Δ-Σ A/D modulator with CIFB single-stage topology.......................................11
2.7 2-2 MASH Δ-Σ A/D modulator. ........................................................................13
3.1 A DT Δ-Σ A/D modulator. .................................................................................16
3.2 A CT Δ-Σ A/D modulator. .................................................................................16
3.3 DAC feedback impulse responses (a) NRZ (b) RZ (c) HRZ. ............................18
3.4 SNDR of 2nd-order modulators with DT and CT loop filters.............................21
3.5 A general CT Δ -Σ A/D modulator block diagram. ...........................................22
3.6 Another block diagram of CT Δ -Σ A/D modulators. ........................................23
3.7 A new representation of the CT Δ -Σ A/D modulator........................................23
3.8 Frequency response of inherent anti-aliasing function of a 2nd-order CT
modulator. .........................................................................................................25
3.9 Frequency response of signal transfer function (STF) of a 2nd-order CT
modulator. .........................................................................................................25
4.1 Typical switched-capacitor integrator................................................................27
4.2 Typical R-C integrator used in CT Δ-Σ A/D modulators...................................29
4.3 The non-ideal first stage integrator of a CT modulator......................................30
LIST OF FIGURES (Continued)
Figure
Page
4.4 Excess loop delay on NRZ DACs (a) ideal DAC (b) DAC with delay. ............32
4.5 Excess loop delay on RZ DACs (a) ideal DAC (b) DAC with delay. ...............32
4.6 Excess loop delay on HRZ DACs (a) ideal DAC (b) DAC with delay. ............33
4.7 Input offset cancellation of a comparator...........................................................35
4.8 Simplified typical CT Δ-Σ A/D modulator. .......................................................38
4.9 NRZ DAC output with and without clock jitter.................................................38
4.10 Single-bit NRZ, RZ and HRZ DAC feedback pulse with jitter noise..............41
4.11 Multi-bit NRZ, RZ and HRZ DAC feedback pulses with jitter noise. ............42
4.12 Pulse shape of SCR DAC.................................................................................44
4.13 R-C integrator with SCR DAC feedback. ........................................................45
4.14 Δ-Σ A/D modulator model including DAC mismatch error. ...........................46
4.15 Switched-capacitor integrator with 4-bit DAC feedback.................................47
4.16 Continuous-time integrator with 4-bit DAC feedback.....................................48
4.17 Illustration of DWA. ........................................................................................49
4.18 Current calibration principle during (a) Calibration (b) Operation..................50
4.19 Block diagram for a N-bit current steering DAC with calibration...................50
5.1 Peak SNDR versus maximum out-of-band NTF gain........................................56
5.2 SNDR versus input amplitude for a fifth-order CT Δ-Σ A/D modulator...........57
5.3 SNDR sensitivity to clock jitter. ........................................................................58
5.4 A fifth-order CT Δ-Σ A/D modulator with a single-stage, single-loop
architecture........................................................................................................59
LIST OF FIGURES (Continued)
Figure
Page
5.5 SNDR versus quantizer delay of the modulator in Figure 5.3. ..........................60
5.6 Improved fifth-order CT Δ-Σ A/D modulator alleviating quantizer delay
requirement. ......................................................................................................61
5.7 SNDR versus quantizer delay of the modulator in Figure 5.6. ..........................63
5.8 Frequency response of the STF of the fifth-order modulator with CIFF
architecture........................................................................................................64
5.9 SNDR for -3dBFS input versus normalized time constant. ...............................66
5.10 Output spectrum of the CT modulator for -3dBFS input.................................68
6.1 Simplified block diagram of the fifth-order CT Δ-Σ A/D modulator. ...............70
6.2 First stage R-C integrator with current steering DAC. ......................................71
6.3 Telescopic OpAmp in the R-C integrator. .........................................................72
6.4 CMFB circuit in the telescopic OpAmp. ...........................................................73
6.5 Attenuations of non-idealities for different stages in the loop filter. .................77
6.6 Second stage Gm-C integrator architecture. ......................................................78
6.7 Gain boosting OpAmp for the PMOS current mirror. .......................................78
6.8 Gain boosting OpAmp for the NMOS current mirror........................................79
6.9 A current cell in DAC1. .....................................................................................80
6.10 Low-swing, high-crossing signal generation in current steering DAC............82
6.11 High crossing, low swing complementary digital signals generator................83
6.12 Synchronizing circuit for each cell in DAC1...................................................84
6.13 Low-jitter on-chip clock generation.................................................................85
6.14 Summing block. ...............................................................................................86
LIST OF FIGURES (Continued)
Figure
Page
6.15 Sampling and hold stage. .................................................................................87
6.16 Summing block, S&H block and comparator. .................................................88
6.17 Modified loop topology of the modulator........................................................89
6.18 17-level quantizer.............................................................................................90
6.19 Comparator.......................................................................................................91
6.20 Wallace tree decoder. .......................................................................................92
6.21 Output driver of the CT modulator. .................................................................93
6.22 Clock generator. ...............................................................................................94
6.23 Variable delay cell. ..........................................................................................95
6.24 Two types of integrators used in this design (a) R-C integrator (b) Gm-C
integrator. ..........................................................................................................96
6.25 Tunable capacitor array....................................................................................96
6.26 Chip die photo. .................................................................................................98
6.27 Current steering DAC layout with symmetrical sequence...............................99
7.1 Two PCB boards for testing the prototype chips .............................................100
7.2 The testing boards (a) daughter board (b) mother board..................................101
7.3 Assembled testing boards.................................................................................101
7.4 Experimental test setup. ...................................................................................102
7.5 SNDR, SNR and SFDR versus input amplitude with a clock frequency of
60 MHz and an input frequency of 100 KHz..................................................103
7.6 Output spectrum with calibration for -2.5dBFS 200KHz input.......................104
7.7 Output spectrum without calibration for -2.5dBFS 200KHz input..................104
LIST OF FIGURES (Continued)
Figure
Page
7.8 SNDR versus tuning code for -2.5dBFS 200KHz input signal........................105
7.9 Output spectrum of two-tone test for -9dBFS inputs .......................................106
7.10 Output spectrum of two-tone test for -12dBFS inputs ...................................106
LIST OF TABLES
Table
Page
3.1 s-domain equivalent for z-domain partial fraction expansion............................19
4.1 Simulated and calculated second-order low-pass DT and CT modulator
SNR...................................................................................................................40
4.2 Comparison between DT and CT Δ-Σ modulators ............................................54
7.1 Peak SNDR with different input frequencies...................................................107
7.2 Summary of the measured chip results. ...........................................................108
7.3 Performance summary of reported design and this work.................................109
To my beloved parents and family
Design of a 14-bit Continuous-Time Delta-Sigma A/D Modulator with
2.5MHz Signal Bandwidth
1. INTRODUCTION
1.1 Motivation
Oversampling Δ-Σ A/D converters were traditionally and are still widely
used for low-frequency, medium-to-high resolution applications, such as
instruments [Ker92], audio [Ito94, Fuj97] and voice [Zwa96, Gri03]. In the last
decade, there has been a growing trend in wireless and wireline communications to
move analog-to-digital conversion towards the system front-end. This implies that
more signal processing is shifted from the analog domain to the digital domain. As
a result, high-performance digital systems can be realized and the advancement in
digital CMOS process can be fully utilized. However, as the interface between
analog and digital data, A/D converters have to provide higher dynamic range to
accommodate weak analog input signals accompanied by significant noise and
interference. Therefore, designing Δ-Σ A/D converters with MHz signal
bandwidths and no less than 14-bit dynamic range is a challenging topic for both
industry and academia.
To date, most reported MHz range Δ-Σ A/D converters are implemented
using switched-capacitor (SC) techniques [Bro97, Jia01, Fuj00, Vle01, Tab03,
Bal04, Bos05], mainly due to mature design methodologies and robustness. Δ-Σ
A/D converters employing SC circuits are also commonly referred to as discretetime (DT) converters. However, recently, continuous-time (CT) Δ-Σ A/D
converters have attracted more interest. Figure 1.1 shows the number of papers
addressing Δ-Σ A/D conversions in recent ISSCCs (International Solid-State
Circuit Conference). It demonstrates the continuously increasing attention and
interest that CT Δ-Σ A/D converters have received.
Compared with DT converters, CT converters have the advantages of lower
power consumption and inherent anti-aliasing filtering, hence extending battery life
2
and reducing system complexity which are especially important for portable
wireless devices. Moreover, absence of stringent settling requirements enables CT
converters to digitize signals up to several hundred MHz, which is still not possible
for their DT counterparts.
14
Number of papers
12
CT DSM PAPERS
ALL DSM PAPERS
10
8
6
4
2
0
2001
2002
2003
Year
2004
2005
Figure 1.1 Number of papers on Δ-Σ A/D converters in ISSCCs.
Besides all the advantages CT Δ-Σ A/D converters have over their DT
counterparts, they do face some design challenges to achieve high resolution for
wide input bandwidth. They are more sensitive to clock jitter and feedback loop
delay than DT Δ-Σ A/D modulators and, they suffer from the large loop
coefficients uncertainty due to the process variations of resistors and capacitors.
These are the major reasons that of all the reported CT Δ-Σ A/D converters to date,
3
there are very few that can achieve wide bandwidth (≥1MHz) and high resolution
(≥14b dynamic range) at the same time. They either have high resolution for low
bandwidth [Zwa97, Bre00, Vel03, Das05], or have high bandwidth but low
resolution [Vel02, Kap03, Bre04, Uen04]. S. Yan presented a CT Δ-Σ A/D
modulator achieving 14b dynamic range [Yan04], but its conversion bandwidth is
only 1.1MHz, targeting ADSL application.
This research targets a 14-bit dynamic range, 2.5-MHz input signal
bandwidth (equivalently, 5MSPS) Δ-Σ A/D modulator by using continuous-time
design techniques. Various design techniques have been utilized to address the
aforementioned design challenges. The modulator with such specifications can find
application in wideband wireless, wireline communication systems such as
ADSL2+, high-speed scientific instruments, medical imaging and vibration
analysis [Tex03].
1.2 Dissertation Organization
This dissertation covers the theoretical analysis of CT Δ-Σ A/D converters,
the system level and the circuit level design of a wideband, high resolution CT Δ-Σ
A/D modulator, and the measurement of the prototype chips.
Chapter 2 reviews the basic concepts of Δ-Σ A/D converters, existing
wideband DT and CT Δ-Σ A/D converters. Chapter 3 talks about general design
methodologies for CT A/D converters. The mapping from a discrete-time
architecture to a continuous-time architecture is discussed.
Chapter 4 describes the design issues for Δ-Σ A/D modulators with both DT
and CT implementations. Effects of various non-idealities and potential solutions to
deal with them are discussed. Thorough comparisons between DT and CT design
techniques are also made.
Chapter 5 presents details of system level design of a wideband, high
resolution CT A/D modulator. Important simulation results are included.
4
Chapter 6 covers details of analog and digital block designs of this CT A/D
modulator. Layout design is also discussed.
Chapter 7 offers measurement setup and results.
Chapter 8 concludes this research project and proposes recommendations
for future improvement of this work.
5
2. OVERVIEW OF OVERSAMPLING Δ-Σ A/D CONVERTERS
2.1 A brief introduction to Δ-Σ A/D converters
The system architecture of a general oversampling Δ-Σ A/D Converter (low
pass or band pass) is shown in Figure 2.1 [Joh97]. The analog input first passes
through an anti-aliasing filter to attenuate out-of-band frequency components so
that its output becomes band-limited and, aliasing due to sampling inside the
following Δ-Σ A/D modulator, can be suppressed. The Δ-Σ A/D modulator converts
the analog signal to a high speed, low-resolution digital signal. The last stage,
called the decimation filter, converts the modulator output into a high-resolution
digital signal at a lower speed usually equal to twice the frequency of the desired
signal bandwidth.
Δ-Σ A/D converters employ oversampling techniques to push quantization
noise and errors due to imperfect analog circuits into a higher frequency band and
remove them by digital filtering so that high in-band signal-to-noise ratio can be
obtained. Compared with Nyquist rate A/D converters, Δ-Σ A/D converters achieve
high resolution without placing stringent requirements on analog blocks. Thus, it is
very suitable for modern CMOS IC technologies.
Analog
input
Anti-aliasing
filter
Δ -S A/D
modulator
Digital
filter (LP or BP)
OSR
Digital output
Decimation filter
Analog
Digital
Figure 2.1 Block diagram of an oversampling A/D converter.
6
As the core of a Δ-Σ A/D converter, the analog modulator normally has
three imperative components as shown in Figure 2.2.
1. Loop filter, H(z)
To represent the CT converter, H(z) shall be replaced by H(s). The loop
filter has large gain within the signal band while it attenuates out-of-band signals.
A loop filter is realized by switched-capacitor integrators in a DT implementation
and continuous-time integrators in a CT implementation.
2. Quantizer
The quantizer works as an internal A/D converter to generate the modulator
output. Its output can be single-bit or multi-bit. A single-bit quantizer is realized by
a comparator. A multi-bit quantizer is normally realized by a flash ADC to obtain
high speed conversion.
3. Feedback DAC
The feedback DAC is employed to convert the digital modulator output to
analog and subtract it from the modulator input. It is normally implemented with a
charge-redistribution DAC in DT converters while current-steering DACs are used
in CT converters.
Loop Filter
x
+
H(z)
e Quantizer
u
DAC
Figure 2.2 Basic architecture of a Δ-Σ A/D modulator.
y
7
Since the quantizer is essentially non-linear, Δ-Σ A/D modulators can not be
considered as a linear feedback system. However, if quantization noise inherent in
quantizing can be modeled as white noise, the nonlinear quantizer can thus be
approximated as an adder as shown in Figure 2.3.
Loop Filter
x
+
H(z)
e
u
y
DAC
Figure 2.3 Linearized Δ-Σ A/D Model.
In both Figure 2.2 and Figure 2.3 , x denote the input analog signal, u is the
quantizer input, y is the quantizer output and e is the quantization noise. The
system transfer function can be easily derived in Z-domain as:
H ( z)
1
X ( z) +
E ( z)
1 + H ( z)
1 + H ( z)
= STF ( z ) ⋅ X ( z ) + NTF ( z ) ⋅ E ( z )
Y ( z) =
(2.1)
Where STF (z ) and NTF (z ) are the signal transfer function and noise
transfer function, respectively From the equation above we see that poles of H (z )
become the zeros of NTF (z ) , hence inside the input signal bandwidth where H (z )
>>1 ,
Y ( z) ≈ X ( z)
(2.2)
8
In other words, the output signal contains unfiltered input plus high-passed
quantization noise (for the case of a low-pass converter) or band stopped
quantization noise (for the case of a band-pass converter). Since quantization noise
is largely pushed out-of-band, high in-band signal-to-noise ratio (SNR) can be
obtained.
The linearized Δ-Σ A/D modulator model is only valid when quantization
error is statistically independent of the input signal [Nor97] which is approximately
satisfied with a high-order (>2) converter. In addition, the analysis and equations
based on this model cannot predict the tones in output spectrum and stability of the
modulator. Despite its drawback, this model has been used widely because it does
predict the noise shaping and signal-to-noise ratio (SNR) quite well. Time-domain
stimulations are normally adopted to check tonal behavior and modulator stability.
For an Lth order modulator with a noise transfer function of (1 − z −1 ) L , the
total in-band quantization noise can be calculated as:
PN = ∫
+ fB
− fB
S QS ( f )df ≈ (
π 2L
)(
2L + 1 M
1
)
2 L +1
Δ2
,
12
M >> 1
(2.3)
where S QS ( f ) is the quantization noise power spectral density (PSD), M is the
oversampling ratio (OSR), ∆ is the quantizer step size, L is the modulator loop
order and fB is the signal bandwidth.
The dynamic range (DR) is:
DR =
Ps 3 2 L + 1 N
= (
)(2 − 1) 2 M 2 L +1 , M >> 1
PN 2 π 2 L
(2.4)
where N is the number of quantizer bits.
The ENOB (effective number of bits) of the converter can therefore be
derived as:
ENOB =
DR − 1.76
6.02
(2.5)
9
Figure 2.4 shows a more general model of a Δ-Σ A/D modulator. In this
model, the input signal and the feedback signal go through different loop filters,
G(z) and H(z), respectively. In such a case, the modulator output can be derived as:
Y ( z) =
G(z)
x
-
G( z)
1
X ( z) +
E( z)
1 + H ( z)
1 + H ( z)
(2.6)
e
u
y
H(z)
Figure 2.4 A general Δ-Σ A/D modulator structure.
The model shown in Figure 2.2 is actually a special but rather popular case
of the general model where the input signal and the feedback signal share the same
filtering path, in other words, G ( z ) = H ( z ) .
2.2 Common architectures for Δ-Σ A/D converters
There are two major types of topologies for Δ-Σ A/D modulators that
depend on the number of the quantizers used in Δ-Σ A/D modulators, single-stage
and multi-stage.
2.2.1 Single-stage topology
In a single-stage Δ-Σ A/D modulator, there is only one quantizer. The
digital output of the quantizer is the input to the DAC. The output of the DAC is
10
subtracted from the analog input signal and (or) the intermediate integrator outputs.
Two general single-stage topologies are:
1. Chain of integrators with weighted feedforward summation and local
resonator feedbacks (CIFF) [Nor97].
2. Chain of integrators with distributed feedback, distributed feedforward,
and local resonator feedbacks (CIFB) [Nor97].
a1
a2
a3
a4
X
+
∫
∫
∫
k1
∫
∫
a5
Y
k2
DAC
Figure 2.5 Δ-Σ A/D modulator with CIFF single-stage topology.
Figure 2.5 shows the fifth-order Δ-Σ A/D modulator with CIFF single-stage
topology. In this topology, the input signal and feedback signal go through the
same loop filter H (z ) , hence the noise and signal transfer functions can be
expressed as:
NTF ( z ) =
1
1 + H ( z)
(2.7)
STF ( z ) =
H ( z)
1 + H ( z)
(2.8)
11
As a result, once the loop filter H (z ) has been set for optimum noise
shaping, the STF (z ) is fixed accordingly. In some cases, this could lead to STF (z )
peaking at high frequencies, resulting in loop instability [Nor97].
The effect of the two local resonator feedback coefficients is to shift the
poles of the loop filter, or, the zeros of the NTF (z ) , to some in-band frequencies
other than DC. Thus, the in-band quantization noise power can be further reduced.
This optimum zero-placement technique is very useful especially for wideband
high resolution Δ-Σ A/D modulators where the oversampling ratios are low.
X
b1
b4
b3
b2
b5
k1
+
∫
a1
+
∫
a2
k1
k2
+
a3
∫
∫
∫
a4
Y
a5
DAC
Figure 2.6 Δ-Σ A/D modulator with CIFB single-stage topology.
Figure 2.6 shows a fifth-order Δ-Σ A/D modulator with CIFB single-stage
topology. In this topology, the added feedforward paths from the input signal to
each integrator’s summing junction allow some independence in specifying
NTF (z ) and STF (z ) . For this case, the input signal and feedback signal go through
different loop filters, say, G (z ) and H (z ) , respectively. Hence the noise and signal
transfer functions can be expressed as:
12
NTF ( z ) =
1
1 + H ( z)
(2.9)
STF ( z ) =
G( z)
1 + H ( z)
(2.10)
By properly choosing b1~b5, the desired STF (z ) can be obtained.
Similar to the CIFF topology, optimum in-band NTF (z ) notches can be
realized by the local resonator feedbacks to improve the signal-to-noise ratio.
One drawback of this topology is that all integrator outputs will contain
both input signal as well as filtered quantization noise since they are subtracted
from the feedback signal directly. This will make the signal swing at each
integrator’s output large. Hence, the linearity will be worse. In addition, the
multiple feedback DACs will consume a lot more area and power especially when
multi-bit quantizers/DACs are used.
A well known shortcoming of the single-stage topology is that only firstorder modulators are unconditionally stable when single-bit quantizers are used.
High-order single-stage modulators can be stabilized by methods such as:
1. Lower the forward loop gain. The implications are that the noise-shaping
efficiency is lowered.
2. Use multi-bit quantizers. However, in such case multi-bit DACs have to
be used and the DAC mismatch errors have to be suppressed by some measures so
as not to increase the in-band noise floor and generate tones.
3. Add “sensing-and-resetting” circuitry to detect the loop instability and
reset the integrators to pull the modulators back to stable status. This technique,
however, results in more complicated circuitry and may introduce extra in-band
noise [Nor97].
2.2.2 Multi-stage topology
Another approach to realize Δ-Σ A/D modulators is to cascade several loworder (≤2) modulators. The advantage of this type of topology is that since each
13
stage is stable, the overall modulator should also be stable. Such a structure is also
called MASH (Multi-stAge noise SHaping) [Joh97]. The basic idea of MASH,
taking a two-stage modulator as an example, is to feed the quantization error of the
first stage into the second stage. The digital outputs of the two stages are combined
through digital cancellation logic so that the first stage quantization error is
removed and only the noise shaped second stage quantization error is left.
Figure 2.7 shows a 2-1 MASH modulator. “2-1” means the first stage is a
second-order modulator and the second stage is a first-order modulator.
Analog Blocks
Digital Cancellation Logic
e1
u
1
1 − Z −1
+
y1
Z −1
1 − Z −1
Z −1
e2
-e1
+
−1
Z
1 − Z −1
y2
(1 − Z
−1
)2
y
Figure 2.7 2-2 MASH Δ-Σ A/D modulator.
The outputs of both stages can be derived as:
Y1 ( z ) = z −1U ( z ) + (1 − z −1 ) 2 E1 ( z )
(2.11)
Y2 ( z ) = − z −1 E1 ( z ) + (1 − z −1 ) E 2 ( z )
(2.12)
After the digital cancellation logic, the final modulator output is:
Y ( z ) = z −1Y1 ( z ) + (1 − z −1 ) 2 Y2 ( z ) = z −2U ( z ) + (1 − z −1 ) 3 E 2 ( z )
(2.13)
14
Therefore the first stage quantization noise is cancelled out and only the
shaped second stage quantization noise is left in the final output. The overall
modulator exhibits the characteristics of third-order noise shaping.
The multi-stage Δ-Σ A/D modulators can have more than two stages and the
later stages do not necessarily have to be Δ-Σ A/D modulator. They can be Nyquistrate ADC as well [Bro97].
A well-known problem of multi-stage modulators is the mismatch between
analog loop transfer functions and digital noise cancellation logic. As seen from Eq.
(2.13) , the perfect cancellation of the first stage quantization noise depends on the
perfect matching between the first stage noise transfer function and the digital
cancellation logic. In reality, the digital cancellation logic can be made very
accurately while the analog blocks are always relatively coarse especially in
submicron digital processes. In such cases, some portion of the first stage
quantization noise will leak to the final modulator output and may eventually limit
the performance no matter how many stages are cascaded. It is based on this
consideration that second-order loops are normally used as the first stages of multistage topologies to reduce the amplitude of the leaked quantization noise. Multi-bit
quantizers can also be used to further reduce this leaked error [Bro97, Fuj00], at the
cost of adding DAC mismatch errors through the use of multi-bit DACs in the first
stage which can not be cancelled.
It should be noted that the mismatch between the analog and digital
circuitry is more serious for CT MASH modulators than DT MASH modulators.
This is because the matching in DT MASH modulators normally depends on
capacitor matching which can be better than 0.1%. However, the matching in CT
MASH modulators is limited by the very coarse time constant that depends on
resistor and capacitor variations. That is why almost all CT Δ-Σ A/D modulators
are implemented with single-stage architectures with very few exceptions [Bre04].
15
3. CONTINUOUS-TIME Δ-Σ A/D MODULATOR LOOP FILTER
DESIGN
Once the modulator type (band-pass or low-pass), order of the loop filter
and oversampling ratio are determined based on the dynamic range requirement,
the loop filter function of a DT Δ-Σ A/D modulator can be found in a
straightforward way by using commercial filter design packages, or with the help of
the widely used delta-sigma design toolbox [Sch00]. By contrast, the loop filter
design of a CT Δ-Σ A/D modulator is nontrivial in that it has a strong dependence
on the pulse shape of the feedback DAC. There are a few commonly used pulse
shapes for the feedback DAC. Each of them has its advantages and disadvantages.
This chapter will discuss the procedure to choose feedback DAC pulse shapes and
design the loop filter function for CT Δ-Σ A/D modulators.
3.1 Transformation of a DT Δ-Σ modulator to a CT Δ-Σ modulator
Because DT modulator loop filters can be easily designed, a CT modulator
loop filter can be derived by first finding the equivalent DT modulator loop filter
and then transforming it to continuous-time.
Thus, the question is: “What condition must be satisfied to equalize a DT
and CT modulator?”
Figure 3.1 and Figure 3.2 show a DT modulator and a CT modulator,
respectively. Unlike the DT modulator, in a CT modulator, the sampling is not at
the front-end input, but at the input to the quantizer. There is no doubt that if they
produce the same output bit sequence in the time-domain for the same time instant,
they can be considered equivalent. This “same-output” condition can be satisfied
by ensuring the inputs to both quantizers are the same at each sampling instant.
16
T
X(z)
X(s)
+
U(z)
H(z)
V(z)
u(n)
Y(z)
DAC
Figure 3.1 A DT Δ-Σ A/D modulator.
XC(s)
+
HC(s)
V(s)
T
UC(s) UC(z)
uC(n)
YC(z)
HDAC(s)
Figure 3.2 A CT Δ-Σ A/D modulator.
Observing the two internal open loop nodes from the quantizer outputs to
the quantizer inputs in both modulators, we can see that both open loops have
sampled-data outputs and inputs.
As mentioned above, the two modulators are equivalent if their quantizers
have the same inputs at each sampling instant, which means
x ( n) = xC (t ) t = nTS
(3.1)
This can be satisfied if the open loop impulse responses are the same at
sampling instants, which can be written as [Thu91].
Z −1 ( H ( z )) = L−1 ( H DAC ( s ) H C ( s )) t = nTs
(3.2)
17
Or in the time-domain [Sho95]
h(n) = [rˆD (t ) * hC (t )] t = nTS
(3.3)
where h(n), rˆD (t ) and hC (t ) are the impulse responses of the DT loop filter H (z ) ,
the CT feedback DAC and the CT loop filter H C (s ) , respectively.
This transformation between the DT and CT domains is called the Impulse
Invariant Transformation (IIT), as implied by its name [Gar86].
Although forward Euler integration, backward Euler integration, bilinear
transformation and midpoint integration [Gre86] are well known and popular in
linear filter designs for transforming DT filters to CT filters and vice versa, they are
not used to transform DT Δ-Σ modulators to CT Δ-Σ modulators. This is because a
Δ-Σ modulator is essentially a nonlinear system, unlike a linear filter. Therefore its
behavior cannot be described solely in frequency domain as in a linear filter. To
find an equivalent DT Δ-Σ modulator for a CT Δ-Σ modulator, a time-domain DTCT transformation method has to be used. The impulse invariant transformation
(IIT) is one such method.
To actually perform the transformation, the DAC feedback pulse shape has
to be decided first according to Eq. (3.2) and Eq. (3.3). Different pulse shapes result
in different transformations between the DT and CT modulators. We will see
shortly there are practical advantages of some over others. There are three
commonly used rectangular DAC feedback pulses: non-return-to-zero (NRZ),
return-to-zero (RZ) and half-delay-return-to-zero (HRZ) [Che00]. Their impulse
responses are shown in Figure 3.3.
DACs with NRZ shapes provide constant output over a full period; DACs
with RZ shapes produce constant valid output only from 0 to T/2 and DACs with
HRZ produce a half clock cycle delayed version of RZ. It should be mentioned that
theoretically it is feasible to have the transition time not at T/2. However, this will
18
complicate the clock signal generation circuit, hence it is not an attractive DAC
shape option.
Figure 3.3 DAC feedback impulse responses (a) NRZ (b) RZ (c) HRZ.
The transfer function of NRZ, RZ and HRZ can be described by the same
equation:
H DAC ( s ) =
exp( −αs ) − exp( − β s )
s
(3.4)
where α and β are valid feedback starting and ending times, respectively.
So we have
⎧ α = 0, β = T
⎪
⎨α = 0, β = 0.5T
⎪α = 0.5T , β = T
⎩
NRZ
RZ
HRZ
(3.5)
After determining the DAC feedback pulse shape and its transfer function,
the impulse invariant transform can be executed following the steps below.
Step1: Write H (z ) as a partial fraction expansion.
Step2: Convert each partial fraction from z-domain to s-domain.
Step3: Recombine the results from step 2 to get H C (s ) .
Detailed mathematical treatment for step 2 can be found in [Sho95]. Table
3.1 lists commonly used first-order and second-order z to s transforms for NRZ, RZ
and HRZ DAC pulse shapes.
19
Table 3.1 s-domain equivalent for z-domain partial fraction expansion
s-domain
equivalent
General
NRZ
zk
zk=1
General
RZ
zk
zk=1
General
HRZ
zk
zk=1
z-domain partial fraction
z −1
1− zk z
z −2
−1
sk
1
z k − 1 sT − s k
(1 − z k z −1 ) 2
( − sk + 1 −
1
) sT − sk 2
zk
( zk − 1)
1
2
1
( sT − sk ) 2
0.5
sT
1
sT
( sT )
sk
1
z k − z k 0.5 sT − sk
[(0.5 z k −0.5 − 1) s k + 1 − z k −0.5 )]sT + (0.5 z k −0.5 − 1) s k 2
1
( z k − z k 0.5 ) 2
( sT − s k ) 2
2
sT
sk
1
zk 0.5 − 1 sT − sk
2
sT
2
−
−1.5
2
+
sT
( sT ) 2
( −0.5 zk −0.5 sk + zk −0.5 − zk −1 ) sT − 0.5 zk −0.5 sk 2
( zk
0.5
− 1)
2
1
( sT − sk ) 2
2
− 0 .5
+
sT
( sT ) 2
Let us take a classical second-order Δ-Σ A/D modulator as an example to
illustrate the validation of the impulse invariant transformation. The second order
quantization noise transfer function is:
NTF ( z ) = (1 − z −1 ) 2
The corresponding z-domain loop filter transfer function is:
(3.6)
20
2 z −1 − z −2
H ( z ) = 1 / NTF ( z ) − 1 =
(1 − z −1 ) 2
(3.7)
here zk=1. By looking up Table (3.1) and doing some simple mathematical
manipulation, we can get s-domain loop transfer functions for the three different
DAC pulse shapes as the following:
⎧ 1 + 1.5sT
NRZ
⎪ s 2T 2
⎪⎪ 2 + 2.5sT
H C (s) = ⎨
RZ
2 2
⎪ s T
⎪ 2 + 3.5sT HRZ
⎪⎩ s 2T 2
(3.8)
Second-order DT and CT modulators with the above H (z ) and H C (s ) have
been simulated in MATLAB/SIMULINK. Figure 3.4 shows the SNDR versus input
amplitude plot. The curves for the three different DAC shapes in CT modulators
are exactly on top of each other and they are slightly different from the DT curve.
This little difference is probably due to two reasons: the different simulation
algorithm/solver that SIMULINK uses for CT models and DT models and the
signal transfer functions of CT modulators and their equivalent DT modulators are
different. Basically the impulse invariant transformation preserves the noise
transfer function but not the signal transfer function. Unlike DT Δ-Σ modulators,
CT Δ-Σ modulators exhibit an inherent anti-aliasing function, an important merit
which we will discuss in Section 3.2.
21
80
70
SNDR (dB)
60
50
40
30
DT
CT-NRZ
CT-RZ
CT-HRZ
20
10
0
-70
-60
-50
-40
-30
-20
Input Amplitude (dB)
-10
0
Figure 3.4 SNDR of 2nd-order modulators with DT and CT loop filters.
Besides rectangular shapes, some other shapes have also been tried in CT
Δ-Σ A/D modulators, although they all inevitably add much complexity to the DAC
design. Perhaps the only reason to use non-rectangular DAC shapes is to reduce
sensitivity to clock jitter which is one of the major challenges for CT Δ-Σ
modulators. We will come back to this issue with more details in Chapter 4.
3.2 Inherent anti-aliasing filtering
It was shown that a low-pass CT Δ-Σ A/D modulator provides an inherent
anti-aliasing filtering on the input signal path [Can85]. In fact, the signal transfer
function contains a “sinc” term and the zeros of the “sinc” term are located at
multiples of the sampling frequency. Hence clock-image signals are attenuated
significantly which otherwise would be aliased into the desired frequency band. In
this section we will analyze the CT Δ-Σ modulators to explain the origination of the
inherent anti-aliasing and validate the observation by showing some simulation
results for a second-order CT modulator.
22
First we redraw the general CT modulator block diagram in Figure 3.5. It is
the CT version of a general Δ -Σ A/D modulator, similar to the DT version in
Figure 2.4. Here, the loop filter H C (s ) is obtained through the impulse invariant
transformation of H (z ), the loop filter of the equivalent DT modulator. In most
conventional CT modulator designs, GC ( s) = H C ( s ) .
e
X(t)
GC(s)
T
u1(k)
y(k)
HC(s)
HDAC(s)
Figure 3.5 A general CT Δ -Σ A/D modulator block diagram.
Unlike a DT modulator, where the signal transfer function (STF) can be
defined completely in z-domain since both the input and output signals are discretetime quantities, in a CT modulator the input is a CT signal which can only be
expressed in s-domain while the output is a discrete-time signal which should be
expressed in z-domain. Therefore it is impossible to derive a straight z- or s-domain
STF for a CT modulator. However, the CT modulator STF can still be written in a
“mixed” form as:
Y (e jωT )
STFC (ω ) =
X ( jω )
(3.9)
Shifting the internal sampler in Figure 3.5 to the left side of the input
subtraction, the Figure 3.5 can be redrawn as in Figure 3.6.
23
e
X(t)
GC(s)
T u (k)
1
y(k)
H(z)
T
HC(s)
HDAC(s)
Figure 3.6 Another block diagram of CT Δ -Σ A/D modulators.
Note that now the modulator loop in Figure 3.6 consisting of the DAC, loop
filter H C (s ) and the sampler is equivalent to its corresponding DT loop filter H (z ) .
Therefore we can derive the transfer function from u1 ( k ) to y (k ) as:
L( z ) =
Y ( z)
1
=
= NTF ( z )
U1 ( z) 1 + H ( z)
(3.10)
Then STFC (ω ) can be rewritten as:
G C ( jω )
Y (e jωT ) U 1 (e jωT )
STFC (ω ) =
⋅
=
= GC ( jω ) ⋅ NTF (e jωT ) (3.11)
jωT
jωT
U 1 ( e ) X ( jω ) 1 + H ( e )
Based on Eq. (3.11), we can obtain the new representation of the CT
modulator in Figure 3.7.
Faa(jω )
X(t)
T
GC(s)
G-1(z)
G(z)
1+H(z)
y(k)
Figure 3.7 A new representation of the CT Δ -Σ A/D modulator.
24
The inherent anti-aliasing filtering function can be expressed as:
Faa (ω ) =
G C ( jω )
G (e jωT )
(3.12)
For most conventional DT modulators, G ( z ) = H ( z ) and for most
conventional CT modulators, GC ( s) = H C ( s ) , For these modulators,
Faa (ω ) =
STFC (ω ) =
H C ( jω )
H ( e jωT )
H C ( jω )
1 + H (e jωT )
(3.13)
(3.14)
Since the DT loop filter H (e jωT ) has poles at multiples of the sampling
clock frequency FS , it can be expected that both Faa (ω ) and STFC (ω ) have zeros at
these frequencies.
The frequency responses of the anti-aliasing function Faa (ω ) and signal
transfer function STFC (ω ) of a 2nd-order double-integration CT modulator
employing NRZ, RZ and HRZ DAC feedback shapes are shown in Figure 3.8 and
Figure 3.9. As expected, the inherent anti-aliasing filtering has a sinc-like response
in that all nulls are at nFS , for n ≠ 0 . For an input signal band 0 ~ f B , the aliasing
frequencies are within [nFS − f B , nFS + f B ] , therefore signals falling within these
bands are attenuated by the inherent anti-aliasing filter. It is interesting to note that
STFC (ω ) for all cases have high-pass characteristics, which may cause instability
if there are some out-band interference along with the in-band signals.
25
1.4
CT-NRZ
CT-RZ
CT-HRZ
1.2
Amplitude
1
0.8
0.6
0.4
0.2
0
0
0.5
1
1.5
2
2.5
Frequency (Fs)
3
3.5
4
Figure 3.8 Frequency response of inherent anti-aliasing function of a 2nd-order CT
modulator.
3
CT-NRZ
CT-RZ
CT-HRZ
2.5
Amplitude
2
1.5
1
0.5
0
0
0.5
1
1.5
2
2.5
Frequency (Fs)
3
3.5
4
Figure 3.9 Frequency response of signal transfer function (STF) of a 2nd-order CT
modulator.
26
4. NON-IDEALITIES IN OVERSAMPLING Δ-Σ A/D MODULATORS
Various non-idealities, including finite OpAmp (Operational Amplifier)
gain/bandwidth/slew rate, quantizer delay/offset/hysteresis/metastability, multi-bit
feedback DAC element mismatch, loop filter coefficients variation and clock jitter,
adversely affect the performance of Δ-Σ A/D modulators. However, due to their
different mechanisms and different occurring locations inside a modulator, their
effects are different and moreover, they may manifest themselves with varying
degrees in DT and CT Δ-Σ A/D modulators. To guarantee a successful design, a
thorough understanding of these non-ideal phenomena is required. In this chapter,
we present the details of these “un-wanted” effects, derive mathematical models
which can be included in system level simulations, and describe commonly used
solutions to overcome them.
4.1 OpAmp non-idealities
The OpAmp is the most commonly used active analog block in Δ-Σ A/D
modulators. When it appears in the first stage of the loop filter, its non-idealities
undergo no attenuation, hence impact the modulator performance to a large extent.
4.1.1 OpAmp in DT integrators
Fig (4.1) shows a typical single-ended delaying switched-capacitor
integrator. CS and CFB are sampling and integration capacitors respectively. Φ1 and
Φ2 are non-overlapped two phase clocks. The integrator samples the input during
Φ1 while it does integration during Φ2. Although only a single-ended integrator is
shown here for analysis, fully differential circuits are normally adopted for better
common-mode noise rejection. The results shown below can be applied to
differential circuits as well.
27
CFB
Φ1
Φ2
Cs
Vin
A(s)
Φ2
Φ1
Vo
CL
Figure 4.1 Typical switched-capacitor integrator.
Assume an OpAmp has single-pole roll-off and, A(s) can be expressed as:
A( s ) =
ADC
1+ s / ω0
(4.1)
where ADC is the OpAmp DC gain while ω0 is -3dB radian frequency. The unity
gain bandwidth of the OpAmp can be expressed as:
UGBW = ADC ⋅ ω 0
(4.2)
The ideal transfer function of the DT integrator is:
H ( z) =
C S z −1
C FB 1 − z −1
(4.3)
The impact of finite OpAmp gain is to shift the pole of H (z ) slightly off the
unit circle, which can be demonstrated by deriving the integrator transfer function
given the finite gain of the OpAmp, as shown in Eq. (4.4).
H ( z) =
CS
C FB
z −1
1
z −1
1−
CS
1+
ADC ⋅ C FB
(4.4)
28
The pole shift is recognized as “integrator leakage” in that only a fraction of
previous output of the integrator is added to the new input sample value. The error
will increase the in-band quantization noise floor.
Finite bandwidth and slew-rate limit the speed at which the integrator can
reach its desired value, in other words, the output of integrator cannot settle
instantaneously. Although the exact details of the settling behavior will vary
depending on the integrator implementation, a good first-order settling model of
both DT and CT integrators can be defined by [Wil93]:
vout [n + 1] = vout [n] + g (vin [n])
(4.5)
⎧ x(1 − e −TS / τ ),
x ≤ τξ
⎪
x TS
( − −1)
⎪
g ( x) = ⎨ x − sgn( x)τξe τξ τ , τξ < x ≤ (τ + TS )ξ
⎪sgn( x)ξT ,
(τ + TS )ξ < x
S
⎪
⎩
(4.6)
where
Ts is the clock period, τ is the settling time constant, which is determined
by 1 / UGBW , and ζ is the maximum slew-rate of the OpAmp. In this model, the
integrator is assumed to approach its final value with a single exponential time
constant τ but the slope of this exponential is limited to ζ.
4.1.2 OpAmp in CT integrators
Figure 4.2 shows the typical R-C integrator widely used in CT Δ-Σ A/D
modulators. The clocked current source(s) is used to provide feedback from singlebit or multi-bit quantizers. The current injection period is a full sampling period for
NRZ or half period for RZ and HRZ.
29
CFB
RIN
Vin
A(s)
Vo
CL
Figure 4.2 Typical R-C integrator used in CT Δ-Σ A/D modulators.
Ideal RC integrators have transfer functions:
Vo ( s )
k ⋅ fs
−1
=
=
Vin ( s ) sRIN C FB
s
(4.7)
where RIN is the value of input resistor while CFB is the value of the integration
capacitor, k is the gain factor of the integrator, and f s is the clock frequency.
When the finite OpAmp gain and bandwidth are taken into account, the
transfer function is modified as:
Vo ( s)
−1
=
1 + ADC
1
1
Vin ( s )
2 RIN C FB
)+
s
RIN C FB +
+ s(
ADC ω0
ADC
ADC ω0
ADC
(4.8)
where ADC is the OpAmp DC gain while ω0 is -3dB radian frequency.
Assume ADC >> 1, (4.8) can be simplifies as [Ort03]:
k ⋅ f s 1 − GE
Vo ( s )
−1
=
=
s
R
C
1
s
Vin ( s )
+1
)
s 2 IN FB + s ( RIN C FB +
ω2
ADC ω0
ADC ω0
where,
(4.9)
30
k ⋅ fs
UGBW + k ⋅ f s
(4.10)
ω 2 = UGBW + k ⋅ f s
(4.11)
GE =
GE is the gain error factor with respect to an ideal integrator gain.
Eq. (4.9) shows that a practical R-C integrator with finite OpAmp gain and
bandwidth can be modeled as an ideal integrator followed by a single-pole roll off
filter.
If we apply Eq. (4.9) to a CT Δ-Σ A/D modulator employing an R-C
integrator as its first stage, we will see a non-ideal first stage shown in Figure 4.3 .
k
X
S / ω2 + 1
f s (1 − GE )
S
+
k
S / ω2 + 1
DAC
Quantizer Output
Figure 4.3 The non-ideal first stage integrator of a CT modulator.
The gain error can be reduced by increasing k. The added second pole ω2
has no effect on the input signal path as long as it is much larger than the maximum
signal frequency, which is easy to satisfy. However, it will generate an extra loop
delay in the feedback path. As will be discussed later, excess loop delay can lead to
modulator instability so that it must be well controlled. Because we have used some
approximations in the above theoretical analysis, it is a good practice to use timedomain simulations to find the minimum required OpAmp gain/bandwidth at
system level.
31
Eq. (4.5) and Eq. (4.6) are not applicable for CT R-C integrators because it
is not possible to use the clock period as a fixed step size to simulate CT
modulators in the time-domain. A practical solution is to apply an output current
amplitude limitation to the OpAmp model, then the required slew-rate can be found
by time-domain simulation.
4.2 Quantizer non-idealities
Delay, offset, hysteresis and metastability are well known non-idealities of
quantizers. Unlike Nyquist-rate A/D converters where comparator errors do not
experience high-pass shaping, comparator non-idealities in Δ-Σ A/D modulators
can be shaped by the loop filter so that they can be, for the most part, tolerated.
However, it should be noted that for high resolution Δ-Σ modulators with multi-bit
quantizers and low oversampling ratios, caution is still needed to prevent
performance loss due to comparator non-idealities.
4.2.1 Quantizer delay
Practical comparators (quantizers) have non-zero time to generate the
correct outputs. This delay, mainly determined by comparator design and IC
process, together with the finite time for the feedback DAC to respond, comprise
the delay between the quantizer clock edge and valid DAC output. The total delay
is called excess loop delay. It should be noticed that in some modulators employing
multi-bit feedback DACs, dynamic element matching (DEM) or calibration
circuitry might be included in the feedback path to suppress DAC element
mismatch errors. These extra signal processing blocks add more delays.
For DT modulators, the excess loop delay can be nearly as high as one
clock period without compromising modulator performance and stability. However,
this is not the case for CT modulators. This problem is illustrated in Figures
4.4Figure 4.4 , 4.5 and Figure 4.6 for three different DAC shapes.
32
Recall that a correct impulse invariant transformation relies on proper shape
of the DAC pulse. Due to the delay of τ d , the whole DAC output is shifted in the
time domain by τ d to the right side. As a consequence the DAC transfer function
will deviate from its ideal expression in Eq. (3.4) and becomes:
H DAC ( s ) =
exp(−τ d s ) − exp(−(T + τ d ) s )
s
DNRZ(t)
0
(4.12)
DNRZ(t)
T/2
(a)
T
t
0τ
d
T
T/2
t
(b)
Figure 4.4 Excess loop delay on NRZ DACs (a) ideal DAC (b) DAC with delay.
DRZ(t)
0
DRZ(t)
T/2
(a)
T
t
0τ
d
T
T/2
t
(b)
Figure 4.5 Excess loop delay on RZ DACs (a) ideal DAC (b) DAC with delay.
33
DHRZ(t)
DHRZ(t)
τd
0
T/2
(a)
T
t
0
t
T
T/2
(b)
Figure 4.6 Excess loop delay on HRZ DACs (a) ideal DAC (b) DAC with delay.
The result of this non-ideal DAC shape is that the equivalence between Hc(s)
and H(z) in Eq. (3.2) is no longer true.
Taking a second-order CT modulator with NRZ DACs as an example, the
ideal CT loop filter transfer function is shown in Eq. (3.8).
If there is an excess loop delay τ d , the z-domain loop transfer function can
be derived as [Che00]:
(2 − 2.5τ d + 0.5τ d ) z −1 − (1 − 4τ d + τ d ) z −2 − (1.5τ d − 0.5τ d ) z −3
(4.13)
H ( z ,τ d ) =
(1 − z −1 ) 2
2
2
2
If τ d =0, H ( z ,τ d ) turns into Eq. (3.7), while for non-zero τ d , H ( z ,τ d ) is no
longer equal to Eq. (3.7) and is 3rd-order now. In fact, as long as the DAC pulse
falling edge passes T due to excess loop delay, the order of the equivalent DT
modulator is one higher than the order of the CT modulator. Performance
degradation and even instability may occur [Che00].
Obviously when HRZ DAC shapes are used, there is no problem as long as
the delay is less than half a clock period. This is a major advantage of using the
HRZ DAC shape. HRZ DACs have been used together with RZ DACs in [Gao97];
34
However, HRZ DACs are more sensitive to clock jitter, a problem which will be
discussed later.
Recall that the excess loop delay originates from three sources: 1. Quantizer
delay, 2. Extra delay due to added signal processing in the feedback loop, 3. Finite
switching time of DAC cells. Thus modulators with different DAC shapes will be
affected by excess loop delay differently.
If NRZ DAC is used, any delay shifts the DAC pulse and causes the falling
edge to pass T, increasing the equivalent DT modulator order by one.
If a RZ DAC is used, any delay shifts the DAC pulse. But as long as the
summed delay is less than half a clock period, the falling edge will not pass T, thus
the equivalent DT modulator still has the same order as the CT modulator.
If a HRZ DAC is used, the DAC pulse will remain unchanged as long as the
sum of the quantizer delay and extra signal processing delay is less than half a
clock period. But the unavoidable finite switching time in the DAC will still push
the falling edge of the DAC pulse to be greater than T, thus increasing the order of
the equivalent DT modulator by one.
From the above discussion, we conclude that when only excess loop delay
is considered, NRZ DAC is the worst choice while RZ and HRZ DACs both have
advantages and disadvantages. They shall be chosen based on intensive simulation,
taking into account all sources of loop delay.
4.2.2 Comparator offset
Comparator offset is shaped by the loop filter in Δ-Σ modulators. However,
for high resolution modulators with multi-bit quantizers, offset can cause an
increase in the noise-floor and the harmonic distortion, thus degrade the SNDR.
Therefore, system level simulations are needed to determine the allowable offset
that will not degrade the modulator performance.
In circuit level design, several measures can be taken to reduce the offset
errors of the comparator, including input offset storage (IOS) and output offset
35
storage (OOS) [Raz95]. The input offset storage is used more frequently in multibit Δ-Σ modulators because of its wide input common mode range.
Figure 4.7 shows a single-ended comparator with input offset storage. The
comparator is comprised of a preamplifier stage and a latch stage.
The input referred offset is [Raz95]:
VOS ( tot ) =
VOSA
Δq VOSL
+
+
1 + A0 C S
A0
(4.14)
where VOSA is the input offset of the preamplifier, VOSL is the offset of the latch, A0
is the preamplifier gain and Δq is the error due to charge injection. As indicated in
Eq. (4.14), the comparator offset can be reduced by the gain of the preamplifier
(normally between 10 and 20), which is adequate for most Δ-Σ modulators.
Φ offset _ cancel
Φ1
Vin
Cs
c
A0
Latch
Vo
Φ2
Voffset
Figure 4.7 Input offset cancellation of a comparator.
4.2.3 Comparator hysteresis
The comparator hysteresis leads to a “memory” effect which causes the
output to resist change even when the input level may have surpassed a threshold.
Like dc offsets, Hysteresis may also increase noise floor and in-band distortion. In
order to reduce hysteresis, one can reset comparators before entering the latch
36
mode. For example, shorting differential internal nodes in the latch to one of the
power supplies or connecting together using switches in the reset phase can be used
[Joh97].
4.2.4 Comparator metastability
Metastability is the result of longer times to resolve the output in the
comparator when very small inputs are applied. The large delay can be problematic
particularly for CT modulators with NRZ or RZ DAC pulses, as mentioned above.
Cherry [Che00] proposed several methods to mitigate metastability performance
loss, such as scaling the quantizer input to have as large as possible span;
decreasing regeneration time by inserting a preamplifier stage and increasing the
gain-bandwidth product of the regenerative circuits; adding additional latching
stages and using improved modulator architectures. An example of the last method
is to have a digital delay in the feedback path for a band-pass modulator.
An efficient technique to overcome metastability proposed in [Raz95]
employs Gray coding between thermometer and binary codes. However, the added
decoding stage may not be preferred for some high speed designs.
4.3 Clock Jitter
4.3.1 Clock jitter in DT modulators
For DT Δ-Σ A/D modulators, the effect of clock jitter can be completely
described by computing the sampling error of the input signals, Clock jitter
occurring internally does not affect modulator performance as long as signal
settling error is low enough. A sinusoidal input signal can be expressed as:
Vin (t ) = A sin(2πf in t + ω t )
(4.15)
where A is signal amplitude, f in is the signal frequency and ω t is the initial phase.
Assuming the clock jitter at a sampling instant t is Δt , the sampling error
ΔVin (t ) is given by [Bri99]:
37
ΔVin (t ) =
dVin (t )
Δt = 2πf in AΔt cos( 2πf in t + ωt )
dt
(4.16)
Assuming the clock jitter is white noise with a Gaussian distribution, and its
standard deviation is σ Δt , the resultant error has uniform power spectral density
from dc to f s / 2 , with a total power of:
P jitter = E[Δ2Vin (t )] = (2πf in Aσ Δt ) 2 / 2
(4.17)
Thus the signal-to-jitter noise ratio can be calculated as:
SNR jitter =
PS
P jitter
=
A2 / 2
2π 2 f in 2 A 2σ 2 Δt / OSR
=
OSR
4π 2 f in 2σ 2 Δt
(4.18)
where OSR is the oversampling ratio.
Eq. (4.18) shows that SNR jitter is not dependent on the input signal
amplitude. This is because the sampling error due to jitter is proportionally to the
signal power, as shown in Eq. (4.17).
Eq. (4.18) expresses the maximum signal-to-noise ratio of a DT Δ-Σ A/D
modulator when the input sampling jitter error dominates.
4.3.2 Clock jitter in CT modulators with rectangular DAC shapes
In CT Δ-Σ A/D modulators, both the quantizer and the feedback DAC are
clocked. The sampling error due to clock jitter at the quantizer is noise shaped by
the same order as the quantization error so that it adds little noise to the modulator
output. However, clock jitter in the feedback DAC generates noise which is not
shaped and affects the modulator performance significantly.
Figure 4.8 shows a simplified typical CT Δ-Σ A/D modulator [Che00]. The
feedback is realized by transferring charge at a constant rate over the whole or part
of a clock period. Thus the clock rising and falling edge variations, in other words,
clock jitter, generates more significant charge errors compared with feedback in DT
modulator where the DAC waveform has a decaying characteristics.
38
X
Gm
+
Y
Gm
IFB
Ts
Figure 4.8 Simplified typical CT Δ-Σ A/D modulator.
Taking a CT modulator with an NRZ DAC feedback waveform as an
example, the effect of clock jitter can be illustrated in Figure 4.9.
Figure 4.9 NRZ DAC output with and without clock jitter.
The error sequence can be expressed by [Ris94]
39
e NRZ (n) = [ y (n) − y (n − 1)]
Δt (n)
(4.19)
Ts
where y (n) is the nth output bit, Δt s is the clock edge timing error and Ts is the
clock period.
For wideband uncorrelated clock jitter, this jitter error energy can be written
as:
σ 2e NRZ = σ 2 Δy , NRZ
σ 2 Δt
(4.20)
Ts 2
Where σ Δy, NRZ is the standard deviation of the adjacent output difference,
and σ Δt is the standard deviation of the clock jitter.
Since the in-band jitter error is reduced by a factor of the OSR over the total
jitter error above, we can calculate the signal-to-jitter noise ratio as:
SNR jitter =
Ps
P jitter
=
A2 / 2
σ 2 e NRZ / OSR
OSR ⋅ A 2
=
2σ 2 ΔY , NRZ (
σ Δt
Ts
)2
(4.21)
where OSR is the oversampling ratio.
To compare the jitter requirements for DT and CT modulators, Eq. (4.18)
and (4.21) are set to be equal, we obtain
σ 2 Δt CT
σ 2 Δt DT
Since normally OSR ≥ 4 , σ
2
=
π 2 ⋅ A2
2OSR 2 ⋅ σ 2 Δ y, NRZ
Δy ≥ 1 ,
(4.22)
A ≤ 1,
σ 2 Δt CT
< 0.31
σ 2 Δt DT
(4.23)
which means to obtain the same signal-to-jitter noise ratio, the jitter noise in CT
modulators must be at least a few times smaller than in DT modulators. In fact,
40
since most modulators’ oversampling ratios are larger than 8, CT modulators are
normally much more sensitive to jitter noise than Eq. (4.23) suggests.
To verify equations Eq. (4.18) and Eq. (4.21), simulations are performed for
second-order, double-integration DT and CT modulators. Several parameters are:
osr = 64, Fs = 80MHz, fin = 156.25KHz, σ Δt ( DT ) = 4.58ns, σ Δt (CT ) = 20 ps.
The clock jitter in both modulators is chosen to make jitter noise dominant.
Parameter σ 2 Δ y, NRZ is found from simulation. Table 4.1 summarizes the simulation
and calculation results.
Table 4.1 Simulated and calculated second-order low-pass DT and CT modulator
SNR.
DT Modulator SNR
Amplitude
(dB)
(dB)
Simulated (4.17)
CT Modulator SNR (dB)
Simulated (4.20)
σ 2Δ y
-6
64.0237
65.0045
64.8270
64.2380 2.3611
-5
63.9120
65.0045
65.1537
64.8690 2.2909
-4
63.8388
65.0045
65.7049
65.6704 2.1373
-3
63.9008
65.0045
65.8488
66.4922 1.9847
From the data in the above table, we see that simulated results fit with
theoretical values very well. Thus, Eq. (4.18) and Eq. (4.21) can be used to estimate
jitter requirements in DT and CT modulators, respectively.
Jitter sensitivity is still the bottleneck to hinder CT modulator from being
widely used in high speed applications where low enough clock jitter is not easy to
obtain.
DAC shape affects the jitter sensitivity of CT modulators. This can be
illustrated by Figure 4.10, where single-bit NRZ, RZ and HRZ DAC shapes are
41
shown. The solid lines indicate that the clock edges are affected by jitter. Intuitively,
NRZ DACs are less affected by clock jitter because clock jitter only causes errors
when the output changes. However, for RZ and HRZ DACs, both rising and falling
edges of the pulse occur every clock cycle so that they are affected by clock jitter
more frequently. Cherry proved that RZ second-order LP modulators are 4.6dB
worse than its NRZ counterpart [Che00]. A good rule of thumb is that CT
modulators employing RZ or HRZ DACs experience jitter noise about 6 dB worse
in the signal band than if NRZ DACs are used.
1
-1
-1
1
-1
NRZ
RZ
HRZ
Figure 4.10 Single-bit NRZ, RZ and HRZ DAC feedback pulse with jitter noise.
Eq. (4.20) and Eq. (4.21) indicate that the jitter noise power can be lowered
by reducing the standard deviation of the adjacent modulator output difference. In
other words, if the step size of the quantizer is reduced, the jitter noise is lowered.
This implies that using multi-bit DACs can reduce the sensitivity to clock jitter.
42
Figure 4.11 shows multi-bit NRZ, RZ and HRZ DAC feedback pulses with
jitter noise. Intuitively NRZ multi-bit DACs should provide best jitter noise
immunity than the other two in that its outputs do not need to reset to zero for every
clock cycle and hence the average adjacent output difference is smaller. This
conclusion can be proved by the following derivation.
NRZ
RZ
HRZ
Figure 4.11 Multi-bit NRZ, RZ and HRZ DAC feedback pulses with jitter noise.
Assuming the standard deviation of the adjacent output difference in the
NRZ mulit-bit DAC is σ Δy and the standard deviation of clock jitter is σ Δt , the
DAC output error due to jitter can be express again by Eq. (4.20).
However, for RZ and HRZ DAC, the output error due to jitter is
proportional to the output value, not the difference.
2
2
σ eRZZ = 2σ y , RZ
σ 2eHRZ = 2σ 2 y, HRZ
σ 2 Δt
Ts 2
σ 2 Δt
Ts 2
(4.24)
(4.25)
43
The coefficient “2” in the above two equations takes into account the fact
that both RZ and HRZ DACs are affected by jitter twice in one cycle, at both their
rising and falling edges.
Comparing the induced jitter error, we obtain
σ 2e
σ 2e
NRZ
σ 2e
σ 2e
=
σ 2 Δy , NRZ
2σ 2 y , RZ
(4.26)
=
σ 2 Δy , NRZ
2σ 2 y , HRZ
(4.27)
RZ
NRZ
HRZ
If the three types of multi-bit DACs have the same full scale, both Eq. (4.26)
and (4.27) are less than 1, meaning that NRZ multi-bit DACs are less sensitive to
clock jitter than RZ and HRZ multi-bit DACs do.
Let’s take a second-order, double-integration CT modulator as an example.
Assume OSR=16, the quantizer has 8 levels and the input signal is -4 dBFS,
simulations in SIMULINK show that σ Δy , NRZ = 0.38 , σ y , RZ = σ y , HRZ = 0.49 , thus
σ 2e
σ 2e
NRZ
RZ
σ 2e
= 2
σ e
= 0 .3
NRZ
(4.28)
HRZ
which means the second-order CT modulator can achieve 5.2dB more resolution if
a NRZ DAC is used instead of RZ or HRZ DACs, assuming the jitter noise is the
dominating factor.
Eq. (4.20) also implies that the more levels the quantizer has, the smaller
jitter induced error will be. However, this is only true for NRZ multi-bit DACs, not
for RZ and HRZ DACs. For NRZ DACs, doubling the number of quantizer levels
will roughly reduce σ Δy, NRZ by half while σ y, RZ and σ y, HRZ have almost no change.
This observation has also been verified by simulations. If we increase the quantizer
levels
of
the
above
modulator
to
16,
simulations
show
that σ Δy , NRZ = 0.17 , σ y , RZ = σ y , HRZ = 0.46 , thus
σ 2e
σ 2e
NRZ
RZ
=
σ 2e
σ 2e
NRZ
HRZ
= 0.07
(4.29)
44
Now the NRZ multi-bit DAC have 11.6dB more resolution than the RZ and
HRZ DACs.
We conclude that for DACs with rectangular shapes, multiple bits in the
DAC can significantly reduce jitter sensitivity only if NRZ shapes are used.
4.3.3 Clock jitter in CT modulators with non-rectangular DAC shapes
Several papers present alternative DAC shapes which can reduce jitter
sensitivity in CT modulators. The fundamental idea is to reduce the feedback signal
amplitude near the edge of the clock signals so that clock variations in time have
less effect compared with constant feedback amplitude shapes, like NRZ, RZ or
HRZ.
One example is to use exponentially decaying DACs, also called SCR
DACs, as shown in Figure 4.12 [Ort01, Ger01]. This type of DAC works like
DACs in DT modulators. Figure 4.13 shows the simplified circuit diagram of an RC integrator with SCR DAC feedback. The charge is transferred through charging
and discharging a capacitor. A resistor can be added in series with the capacitor and
MOS switch to adjust the time constant. Since the DAC output is much lower at the
end of integration phase compared with the beginning of the phase, clock jitter has
less impact on the amount of transferred charge than rectangular DACs where the
DAC output is constant in every cycle.
Iout(t)
0
T/2
T
Figure 4.12 Pulse shape of SCR DAC.
45
CFB
RIN
Vin
A(s)
R
D
Vo
CL
CDAC
Figure 4.13 R-C integrator with SCR DAC feedback.
Although this type of DAC reduces the clock jitter sensitivity, it places
more stringent slew rate requirements on the integrator, and hence larger power
will be consumed. In addition, when a multi-bit quantizer is used for high
resolution, the DAC also needs to be multi-bit. In such cases, the mismatch of the
DAC should be suppressed so that it doesn’t limit the modulator performance.
However, as we will show in the next section, dynamic element matching (DEM)
cannot boost the DAC linearity to be more than14-bit. Therefore, this DAC is not
suitable for wideband high resolution CT modulators.
Another example is to use sine-shaped DAC pulses which can alleviate slew
rate issues induced by using SCR DACs [Luc04]. This type of DAC, however,
needs additional synchronization circuitry and introduces extra phase noise into the
system [Luc02]. The DAC mismatch is also a problem as noted above.
So far, there is no CT Δ-Σ A/D modulator with multi-bit non-rectangular
DAC reported in the literature. However, as the component matching is improved
in silicon process, the non-rectangular DAC may be an attractive choice since they
nearly eliminate the most prominent bottleneck for CT Δ-Σ A/D modulators: clock
jitter.
46
4.4 Multi-bit DAC element mismatch
A Δ-Σ A/D modulator employing a single-bit quantizer uses a single-bit
DAC which are inherently linear. This attractive advantage has driven the wide-use
of single-bit quantizers in Δ-Σ A/D modulators, especially for low-speed, high
resolution modulators with high oversampling ratios. However, for high-speed
modulator digitizing MHz range signal, low oversampling ratios (<32) are a must
for a reasonably high clock frequency. In such cases, a multi-bit quantizer is a good
choice since it has several significant advantages over a single-bit quantizer,
including lowering quantization noise, improving loop stability and reducing clock
jitter sensitivity for CT modulators.
Despite all the gains, the use of a multi-bit quantizer means a multi-bit DAC
in the feedback path. The unavoidable element mismatch may become a limiting
factor of the modulator performance. This can be illustrated by Figure 4.12.
Loop Filter
x
+
e Quantizer
u
H(z)
y
d
DAC
Figure 4.14 Δ-Σ A/D modulator model including DAC mismatch error.
In Figure 4.14, d represents the DAC mismatch error. If we rewrite Eq. (2.1)
including the DAC mismatch error, we obtain
1
H ( z)
H ( z)
X ( z) +
E ( z) −
D( z )
1 + H ( z)
1 + H ( z)
1 + H ( z)
= STF ( z ) ⋅ X ( z ) + NTF ( z ) ⋅ E ( z ) − MTF ( z ) ⋅ D ( z )
Y ( z) =
(4.30)
47
where MTF ( z ) represents the mismatch error transfer function.
Eq. (4.30) indicates that the DAC mismatch error appears in the modulator
output as if it goes through a mismatch transfer function MTF ( z ) and MTF ( z ) is
the same as the signal transfer function STF ( z ) . Since H ( z ) has large in-band gain.
The DAC mismatch experiences no attenuation in the signal band when it appears
in the modulator output. Current CMOS processes can only provide 0.1% matching
accuracy (10-bit) for capacitors, and matching accuracy for transistors is even
poorer than that of capacitors [Shy84]. To obtain more than 10-bit resolution, DAC
mismatch errors must be suppressed below the modulator overall linearity
requirement.
Figure 4.15 and Figure 4.16 show typical DT and CT integrators with multibit DACs in the feedback paths, respectively. DT modulators usually adopt
capacitors as DAC elements while CT modulators usually use current sources.
Vref+ VrefS
~S
1
2
...
...
Vin+
C1
1
2
C2
...
...
1
2
C16
CFB
1
2
+ -
Vout-
- +
Vout+
1
...
2
C1'
1
C2'
2
1
...
C16
1
2
1
2
CFB
...
...
Vin~S
S
Vref+ Vref-
Figure 4.15 Switched-capacitor integrator with 4-bit DAC feedback.
48
0.5IDAC
0.5IDAC
RZ CFB
RIN
Vin+
VoutVout+
VinRIN
...
RZ CFB
.....
D1p
D1n D2p
D2n
D16p
D16n
Figure 4.16 Continuous-time integrator with 4-bit DAC feedback.
Dynamic element matching (DEM) and digital calibration have been used
widely for DT modulators. DEM whitens the DAC errors by randomizing the
selection of DAC elements [Car89], first-order shaped [Bar95] or second-order
shaped [Sch95]. It has been found that DEM is not very effective when
oversampling ratio is low, say, 16 or lower. Digital calibration can suppress DAC
errors more efficiently, but it needs much more complicated analog and digital
circuitry to implement, consuming more power and silicon area.
Figure 4.17 takes data-weighted-averaging (DWA), a widely used firstorder DEM algorithm, and a 4-bit DAC, as an example to illustrate the principle of
the DEM.
The selection of the DAC elements is based on the input data and currently
used elements. Assume the input sequence is “2, 5, 4, 7, 5, 2…” in Figure 4.17, the
gray grids represent currently used DAC elements while white grids indicate those
not used. The elements are selected in a circularly way such that every element has
49
the same probability of uses. Hence, the mismatch error can quickly average out
and the DAC mismatch error is effectively first-order shaped.
DAC Elements
DATA 1 2 3 4 5 6 7 8
2
5
4
7
5
2
Figure 4.17 Illustration of DWA.
The other technique to tackle DAC mismatch errors, which has been used in
monolithic high-resolution current steering D/A converters, is self-calibration
[Gro89]. The basic ideal of this technique is to use a reference current as a standard
to trim each current source. The calibration is done circularly so that the calibration
is continuous.
The circuit of a single current source with calibration is shown in Figure
4.18. During the calibration phase, switch S2 is on and switch S1 connects the
reference current source to transistor M1. Thus M1 takes a current of Iref. Since it
is diode-connected, the voltage Vgs on the intrinsic gate capacitor Cgs is
determined by the transistor V-I characteristics. During the operation phase, switch
S2 is off and switch S1 connects to the output node of M1. Since Vgs is preserved
by Cgs, provided that the drain voltage of M1 is not changed either, the output
current from M1 will still be Iref.
50
OUT
OUT
Iref
Iref
Iref
S1
S1
S2
S2
Cgs
+
M1
Cgs
Vgs
(a)
M1
+
Vgs
(b)
Figure 4.18 Current calibration principle during (a) Calibration (b) Operation.
To be suitable for a multi-bit current steering DAC, the calibration idea
must be extended to an array of current sources. This is realized by the continuous
current calibration circuit which is shown in Figure 4.19.
CLK
IOUT,1
N+1 BITS
SHIFT
IOUT,2
IOUT,N
Iref
SWITCHING NETWORK
M1
M2
MN
M’
Figure 4.19 Block diagram for a N-bit current steering DAC with calibration.
Because a current source cannot generate valid output when it is in the
calibration phase, a spare current source is added to ensure the continuity of the
DAC output. The N+1 bits digital shifter generates a 1-of-n code to select the
current cell for calibration. The rotation feature of the shifter enables each cell to be
calibrated again after the other cells have been sequentially calibrated. The current
switches are incorporated in the switching network, conducting N normally
51
operating current cells to their corresponding output terminals and the only one
calibrating cell to the reference current source.
Some non-idealities, such as charge injection, clock feedthrough and switch
mismatch will lead to nonlinear errors. Proper design technique can be taken to
achieve 16-bit linearity [Gro89].
4.5 Loop filter coefficient variation
The DT integrator shown in Figure 4.1 has a nominal gain factor
determined by the ratio between two capacitors, thus its accuracy is the same as the
matching between on-chip capacitors which is on the order of 0.1% or even better.
However, the gain factor in a CT integrator shown in Figure 4.2 is determined by
the product of an on-chip resistor and capacitor. Since the on-chip resistor and
capacitor vary independently and each of their absolute values can vary from
nominal values by nearly +/-20%, it is not uncommon that the gain of a CT
integrator departs from its desired value by +/-30%. Therefore, the gain errors of
integrators in DT modulators are normally not an issue while it is the opposite case
in the CT modulators. A large variation in loop filter coefficients in CT modulators
can significantly degrade the modulator performance by shifting the locations of
poles and zeros. Even worse, the modulators can be driven into instability. That is
why tuning is often needed for CT circuits, including CT modulators.
4.6 Comparison between DT and CT Δ-Σ A/D modulators
4.6.1 Implementation
DT Δ-Σ A/D modulators can only be fabricated with CMOS processes
because their operation largely depends on high quality front-end sampling
switches which can only be realized by MOS transistors. On the contrary, front-end
sampling switches are not needed in CT Δ-Σ A/D modulators so that CT Δ-Σ A/D
modulators can be fabricated with CMOS, BICMOS and bipolar processes. In fact,
bipolar CT Δ-Σ A/D modulators [Jen95] have achieved a 3.2GHz clock rate.
52
4.6.2 Low voltage operation
As the supply voltage becomes lower and lower, it is harder to realize MOS
switches with high linearity and low on-resistance. In such case, DT Δ-Σ A/D
modulators, which are normally implemented with switched-capacitor techniques,
have to find ways to overcome this problem. Although switch-bootstrapping
[Rab97, Abo99] or switched-OpAmp [Bas97] circuit techniques have been used in
low supply circuits, they do have their own drawbacks and limitations. The former
method requires extra complicated circuits for switches and the switches may break
down during long-term operation. The latter method may reduce the available
speed of the modulator because the OpAmps are normally turned off completely
during one phase of the clock [Bas97]. Thanks to the continuous-time operation,
CT Δ-Σ A/D modulators are not impacted by the low supply voltage.
4.6.3 Operation speed
In DT Δ-Σ A/D modulators, to reduce sampling errors, the clock speed can
not be too high if the input and intermediate analog signals are to be sampled
accurately. In addition, the finite bandwidth of OpAmps, given reasonable power
consumption, put another limit on clock frequency. On the other hand, in CT
modulators the sampling occurs just at the quantizer, therefore the sampling errors
are shaped by the loop filter gain. Moreover, if CT loop filters are designed with
bipolar transistors, much higher OpAmp bandwidths can be acquired. These two
merits enable the CT modulators to work at very high clock speeds. In other words,
the signal bandwidth of CT modulators can be much larger than that of their DT
counterparts.
4.6.4 Power consumption
In DT modulators, the unit-gain frequency of the OpAmps must be at least
five times the clock rate [Gre86], resulting in high power consumption. On the
other hand, OpAmps in CT modulators do not have settling problems, so their
53
bandwidth can be as low as the clock rate. Therefore, for the same signal bandwidth
and resolution requirements, CT modulators need much less power than do DT
modulators.
4.6.5 Anti-aliasing filter requirement
For a DT modulator, to prevent signal aliasing due to front-end sampling
operation, there must be an anti-aliasing filter in front of the modulator to
sufficiently attenuate the frequency components in the aliasing band. For a wideband, high speed modulator, the anti-aliasing filter design is not trivial and the filter
might consume a significant amount of power which is undesirable in low-power
systems. In some applications, the on-chip implementation of the anti-aliasing filter
is even not feasible. Thus an off-chip filter has to be used and the cost of the system
will increase significantly. However, for CT modulators, the loop filters provide an
inherent anti-aliasing function so that anti-aliasing filters at the front-ends are
normally not needed. Even if they are needed in some cases, the requirements
become very relaxed and it is easy to implement the filters on-chip.
4.6.6 Clock jitter sensitivity
As analyzed in section (4.3), CT modulators are much more sensitive to
clock jitter than DT modulators.
4.6.7 Sensitivity to process variation
The loop filter coefficients of the DT modulators are determined by the onchip components matching properties, not their absolutely values, thus they are
only slightly affected by process variations and it is normally not a problem. On the
contrary, the loop filter coefficients of the CT modulators are determined by
products of resistors and capacitors whose values do not track with each other.
Therefore, the time constant variations of the CT modulators should be considered
carefully in the system level and circuit level designs to prevent them from
degrading modulator performance.
54
4.6.8 Loop filter scalability with clock frequency
The loop filter coefficients of DT modulators do not depend on clock
frequencies. Hence the loop filters are scalable and the modulators can be easily
reused for different applications with different signal bandwidth and sampling rates.
In comparison, the loop filter coefficients of the CT modulators depend on clock
frequency, therefore the modulators can only be used for specific applications
having pre-determined signal bandwidth and sampling rate.
Table 4.2 lists the advantages and disadvantages of the DT and CT Δ-Σ
modulators.
Table 4.2 Comparison between DT and CT Δ-Σ modulators
Design Requirements or
DT Δ-Σ Modulators
Performance
Process
CMOS
Low Voltage Operation
Not suitable
Speed of Operation
Power Consumption
Anti-aliasing Filter
CT Δ-Σ Modulators
CMOS, BICMOS, Bipolar
Suitable
Clock frequency normally
Clock frequency up to a
less than 100 MHz
few GHz
More power needed for
Not limited by settling
sufficient settling
Less power consumption
Required, on-chip feasibility
questionable
Not normally necessary,
relaxed requirements if
needed
Clock jitter sensitivity
Low
High
Process variation impact
Low
High
Scalable
Not scalable
Loop filter scalability
with clock
55
5.
SYSTEM LEVEL DESIGN
This chapter describes the system level design issues and simulation results
of a 14-bit CT Δ-Σ A/D converter with 2.5MHz signal bandwidth. Various nonidealities were taken into account based on methods and equations presented in
Chapter 4.
5.1 Modulator topology
5.1.1 Modulator order and number of quantizer levels
Because of the large loop coefficients variation in CT modulators, it is
difficult to achieve sufficient matching between analog loop and digital
cancellation logic, thus a multi-stage topology is not preferred for a 14-bit
modulator. Rather, a single-stage topology is chosen for this project.
If a multi-bit quantizer is used in a single-stage modulator, it introduces
several benefits: 1. Reduces the in-band quantization noise by implementing more
aggressive noise transfer function. As the consequence, if a N-bit quantizer is used,
more than 20log10 (2N-1) dB DR improvement can be expected compared with a
single-stage single-bit modulator [Jia01]; 2. Improves loop stability because of the
significantly reduced quantization noise power; 3. Lowers the clock jitter
sensitivity if a NRZ multi-bit DAC is accordingly used.
The choice of the NTF is a trade off among several factors:
•
Loop order
•
Clock speed
•
Maximum stable input amplitude
•
Number of quantizer levels
Based on extensive simulations in MATLAB, a fifth-order, 5-bit (17 levels)
topology is chosen with 12X OSR. The clock frequency is 60MHz. Figure 5.1
shows the simulated peak SNDR versus maximum out-of-band NTF gain using
56
Schreier’s toolbox [Sch00]. Balancing between the ideally achievable peak SNDR
and maximum stable input amplitude, the maximum out-of-band NTF gain of 4
was finally chosen.
115
110
Peak SNDR (dB)
105
100
95
90
85
80
2
3
4
5
6
Maximum out-of-band NTF Gain
7
8
Figure 5.1 Peak SNDR versus maximum out-of-band NTF gain.
Figure 5.2 shows the simulated SNDR versus input amplitude. The peak
SNDR is 102.5dB. The maximum stable input amplitude is nearly -2dBFS.
However, this simulation does not include any non-ideal effects. When various
non-ideal effects are added, the achievable SNDR will decrease. Thus sufficient
margin should be given in the system level design.
57
100
SNDR (dB)
80
60
40
20
0
-20
-100
-80
-60
-40
Input amplitude (dBFS)
-20
0
Figure 5.2 SNDR versus input amplitude for a fifth-order CT Δ-Σ A/D modulator.
5.1.2 Choice of DAC pulse shape
Jitter sensitivity of a CT Δ-Σ A/D modulator is determined by the DAC
choice and the DAC pulse shape has to be determined before designing the loop
filter. Hence, we need to find the proper DAC shape based on the jitter sensitivity
requirement before we derive the loop transfer function.
Since we already decided to use multi-bit quantizer to achieve low enough
quantization noise, and analysis in Section (4.3.2) shows that among three
rectangular DAC shapes, jitter sensitivity is lowest when a multi-bit NRZ DAC is
adopted, we first assume that a NRZ DAC will be used for this design.
Figure 5.3 shows the simulated and calculated SNDR for -3dBFS input for
different clock jitter rms values. It should be noted that the calculation is based on
Eq. (4.20) which takes into account only jitter noise while the simulations include
both quantization noise and jitter noise. It is shown that when the clock jitter rms
58
value is more than 4ps, the jitter noise begins to dominate at the modulator output
and the simulation result fit with the calculation result very well.
To achieve the total power of quantization noise and jitter noise of 87dB
lower than the input signal power, the clock jitter rms value must be less than 6ps.
105
SNDR for -3dBFS input (dB)
simulated SNDR
calculated SNDR
100
95
90
85
80
0
0.2
0.4
0.6
0.8
Clock jitter standard deviation (s)
1
-11
x 10
Figure 5.3 SNDR sensitivity to clock jitter.
We can use Eq. (4.26) and (4.27) to estimate achievable signal-to-jitter
noise ratio for this fifth-order modulator if RZ or HRZ DACs are used. Simulations
in MATLAB/SIMULINK show that σ Δy, NRZ =0.2, σ y , RZ = σ y , HRZ = 0.51,
substituting these values into Eq. (4.26) and (4.27), we can find that jitter noise
power will be 11.1dB more than the case when a NRZ DAC is used. This implies
that the signal-to-(quantization noise + jitter noise) ratio will be about 85dB even if
the clock jitter rms value is only 2ps. Therefore, we can conclude that RZ or HRZ
DACs are not appropriate choices for this design.
59
5.1.3 Loop filter architecture
After determining the modulator order, quantizer levels and maximum outof-band NTF gain, the equivalent DT loop transfer function H ( z ) can be found.
Then together with the determined DAC shape, we can use impulse invariant
transformations to find the loop transfer function H C ( s ) of the CT modulator. The
next step is to determine the loop filter architecture. As we have discussed in
Chapter 1, there are two commonly used loop filter architectures for single-stage
modulators: CIFF and CIFB. Since CIFB requires several DACs feeding back to
each integrator’ output, it is not an economical solution when multi-bit DACs are
used. Thus we choose to use the CIFF architecture for this work.
However, if we directly implement the CIFF architecture for this CT
modulator as shown in Figure 5.4, a problem arises immediately: How about the
impact of the extra loop delay? Since the quantizer and the DAC are clocked by the
same phase, any delay in the quantizer may degrade the performance and may even
lead to instability, therefore this issue should be carefully examined through system
level simulations to see how much delay the modulator can actually tolerate.
g1
g2
g3
k1
ST
u
k2
ST
k4
ST
gz 2
gz1
d1
DAC
k3
ST
g4
k5
ST
y
g5
PHI1
NRZ DAC
Q
SET
D
PHI1
Q
CLR
DFF
Figure 5.4 A fifth-order CT Δ-Σ A/D modulator with a single-stage, single-loop
architecture.
60
Figure 5.5 shows the SNDR at -4 dBFS input for the architecture in Figure
5.4 when the quantizer delay is taken into account. It indicates that if the quantizer
delay is 9% of the clock period (1.5ns in this design), the modulator becomes
unstable. To ensure that the quantizer has delay well below 1.5ns, the quantizer has
to dissipate a significant amount of power which is not preferred for this work.
Thus, a different architecture needs to be found that can alleviate the excess loop
delay problem.
110
100
90
SNDR (dB)
80
70
60
50
40
30
20
10
0
0
0.2
0.4
0.6
0.8
Quantizer_delay (Ts)
1
1.2
Figure 5.5 SNDR versus quantizer delay of the modulator in Figure 5.3.
Fortunately, this excess loop delay issue can be easily tackled by adding a
second feedback path to the input of the quantizer [Yan04, Moy03], as shown in
Figure 5.6.
In this single-stage dual-loop modulator architecture, the clock driving Dlatch array has opposite phase to the clocks driving the quantizer and the DFF array
61
synchronizing DAC1. The D-latch array effectively adds a half-clock delay in front
of DAC1 and DAC2, thus there is now one digital delay between the quantizer
output and the DAC1 input, giving the quantizer a full clock period to settle
without adding any extra loop delay. It should be noted that there is one digital
delay too around the second feedback loop starting from the quantizer output to the
quantizer input.
g1
g2
g3
k1
ST
u
k2
ST
k4
ST
k5
ST
y
g5
PHI1
gz 2
gz 1
d1
DAC1
k3
ST
g4
d2
NRZ DAC
DAC2
Q
SET
D
Q
SET
PHI1
Q
Q
CLR
D
PHI2
CLR
D-LATCH
DFF
Figure 5.6 Improved fifth-order CT Δ-Σ A/D modulator alleviating quantizer delay
requirement.
The reason for adding a second DAC can be explained by the following
derivation.
The loop transfer function of the equivalent DT modulator can be generally
written as:
n
H ( z) =
∑a z
−i
i
i =1
n
b0 + ∑ bi z
i =1
(5.1)
−i
62
H ( z ) can be further decomposed into two parts as:
~
a1 −1
z + z −1 H ( z )
b0
(5.2)
Where
n −1
~
∑ (a
i +1 −
H ( z ) = i =1
a1
a
bi ) z −i − 1 bn z − n
b0
b0
n
b0 +
∑b z
i
−i
(5.3)
i =1
Since H (z ) is equivalent to the loop transfer function in the CT modulator
from the quantizer output to the quantizer input, we can see that the first item in Eq.
(5.2) represents DAC2.
a1
is the gain of DAC2. The second item in Eq. (5.2)
b0
represents the loop transfer function composed of DAC1 and the fifth-order loop
filter. The z −1 in the first item represents the one digital delay around the internal
loop composed of the quantizer, the D-latch array and DAC2. The z −1 in the
second item represents the one digital delay between the quantizer output and
DAC1 input.
Having decided the DAC1 shape, we can perform the impulse invariant
~
transform on H ( z ) to obtain the corresponding CT loop filter H C (s) . After this all
coefficients in the CT loop filter can be derived. The mathematical process is
included in Appendix A.
Figure 5.7 shows the SNDR at -4 dBFS input for the architecture in Figure
5.6 when the quantizer delay is taken into account. As expected the quantizer can
have up to one clock delay without impacting modulator performance. For the sake
of comparison, the curve in Figure 5.5 is also shown in the plot. Also, the SNDR
versus quantizer delay characteristic of single-loop architecture with RZ DAC is
63
simulated and plotted in Figure 5.7. It is shown that even with a RZ DAC, the
quantizer delay should be less than 14% of the clock period (2.33ns in this design)
otherwise the modulator becomes unstable.
110
100
90
SNDR (dB)
80
70
60
50
40
30
CT-NRZ-dual-loop
CT-NRZ-single-loop
CT-RZ
20
10
0
0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9
Quantizer_delay (Ts)
1
Figure 5.7 SNDR versus quantizer delay of the modulator in Figure 5.6.
A drawback of the feedforward architecture is the unavoidable out-of-band
peaking in the signal transfer function. Figure 5.8 shows the frequency response of
the signal transfer function (STF) of this fifth-order modulator with CIFF
architecture. Although the STF has unit gain within the signal band (Fs/24), it has a
13 dB peaking at about Fs/6. If the modulator is used in a wireless devices, the
desired in-band signal may be accompanies by some strong out-band interference.
If the interference signal is unfortunately close to the peaking frequency, Fs/6 in
this example, they will be folded back into the signal band due to the non-linearity
64
of the modulator, hence increase the in-band noise floor and may generate in-band
tones as well.
50
Out-of-band peak
0
-50
Gain (dB)
-100
-150
-200
-250
-300
-350
0
0.5
1
1.5
2
2.5
3
3.5
4
Frequency (Fs)
Figure 5.8 Frequency response of the STF of the fifth-order modulator with CIFF
architecture.
There has been some previous work on solving this peaking problem by adding
low-pass filtering inside the modulator [Phi04]. Since the peaking frequency in this
design is about 4.3 times the maximum in-band frequency, it can be largely
attenuated by some filtering before the A/D modulator, for instance, image
rejection filter. Moreover, the out-of-band peak has no harmful effect when the
modulator is used in wireline communications, such as ADSL2+, one of the major
applications of this work. Hence, we do not take any special care for this out-ofband peaking in the signal transfer function.
65
5.2 Time constant variation
As discussed in Chapter 4, the large time constant variation is one of the
major disadvantages of CT modulators compared to DT modulators and it needs to
be carefully examined in the system level.
The process we are using to fabricate the chip is a TMSC 0.25μm 5-metal
mixed/RF CMOS. The documents that the foundry provides do not include enough
information on how good capacitors/resisters match given certain component sizes
and mutual distances. Thus we have to use available limited matching information
and common sense to simulate the effects of time constant variations.
In simulation we assume that all resistors in the five integrators vary by the
same percentage and so do the capacitors. Thus the time constants in the five
integrators vary by the same percentage. This is actually a worst-case assumption
because if they vary differently, the effects of the time constant variation can be
somehow averaged out.
When the time constants, in other words, the products of resistors and
capacitors, become smaller then their nominal values, the integrators’ gains
increase, hence more SNR can be obtained. However, when the time constants are
as small as 94% of their nominal values, the modulator become unstable due to
excessive loop gain; On the other hand, if the time constants are larger than their
nominal values, the loop gain decreases so that the noise shaping is less efficient, as
a result, SNDR drops gradually. Figure 5.9 shows the simulation result.
66
100
SNDR (dB) for -3 dBFS input
90
80
70
60
50
40
30
20
10
0
0.9
0.95
1
1.05
1.1
Normalized time constant
1.15
Figure 5.9 SNDR for -3dBFS input versus normalized time constant.
From Figure 5.9 we see that within 94% and 114% of nominal time
constant, the modulator can achieve more than 90dB SNDR for -3 dBFS input. To
extend the tolerable time constant variation, we can relocate the loop filter
coefficients to the center point of this range, in other words, 104% of the nominal
time constant. By doing this, the time constant can vary by +/-10% without
significantly degrading SNDR.
Since in extreme cases the RC time constant can vary by +/-30%, some onchip tuning method still needs to be implemented.
5.3 Multi-bit DAC mismatch
The mismatch of the DAC1 can limit the modulator dynamic range to less
than 10 bits if no calibration is provided. Due to the low oversampling ratio and
67
large transistor threshold voltage and current factor mismatch, dynamic element
matching is not sufficient to suppress the DAC mismatch to the required level. On
the contrary, a DAC with current calibration can achieve more than 14 bits of
linearity with less hardware consumption and less excess loop delay.
Figure 5.10 shows the simulation results for three different cases: using
self-calibration for DAC1; using DWA for DAC1 and no suppression of mismatch
for DAC1. All simulations assume there is 0.5% element mismatch in DAC1 and
DAC2 and there is no measure to suppress mismatch for DAC2. It is also assumed
that self-calibration can improve the element matching in DAC1 to 14bits which
can be readily achieved with proper DAC and calibration logic circuit design.
The simulation results show that the modulator can only achieve 69dB
SNDR when DWA is used while using self-calibration can suppress the DAC1
mismatch low enough not to adversely impact the modulator performance. Hence,
self-calibration is adopted in this design.
The second DAC, which sums with other signals at the front of the
quantizer, does not need any calibration because its mismatch is fifth order noise
shaped. Simulations show that the mismatch in DAC2 can be as high as 4% without
degrading the modulator performance. Therefore the transistors in DAC2 can be
relatively small due to relaxed matching requirements.
68
0
-20
Output Spectrum (dB)
-40
-60
-80
-100
-120
-140
With calibration, 95dB
With DWA, 69dB
No mismatch reduction, 55dB
-160
-180 3
10
4
10
5
10
6
10
10
7
10
Frequency (Hz)
Figure 5.10 Output spectrum of the CT modulator for -3dBFS input.
8
69
6. CIRCUIT AND LAYOUT LEVEL DESIGN
In this chapter, the circuit and layout level design of the CT Δ-Σ A/D
modulator will be discussed. In fact the design of the modulator is an iterative
process, making the system level, circuit level and layout level design closely
correlated.
6.1 Loop filter design
The fifth-order loop filter of this design is implemented with a dual-loop
single-stage CIFF architecture, as shown in Figure 6.1. The first stage is an R-C
integrator and the following two resonators are both realized by Gm-C integrators.
The role of the resonators is to shift the poles of the loop filter to optimum non-zero
frequencies in order to reduce in-band quantization noise. The five gain stages are
also transconductors which convert the integrators’ outputs from voltages to
currents and then convert back to voltages through two resistors. The voltages on
the resistors are sampled by the multi-bit quantizer to generate the modulator
digital outputs. The thermometer-coded outputs control the two current steering
DACs to generate feedback currents, feeding to the modulator input and quantizer
input, respectively.
There are three types of commonly used continuous-time integrators: R-C
integrators, Gm-C integrators and MOSFET-C integrators. In this design, the first
stage uses an RC integrator rather than Gm-C and MOSFET-C integrators for its
superior linearity. Gm-C integrators are chosen for the two resonators to save
power. If they were R-C or MOSFET-C integrators, resistive loading would
increase the power consumption considerably because two stage OpAmps are
needed to increase the drive capabilities.
70
Gm
Gm
Gm
Gm
Gm
Gm
Gm
Gm
Gm
Gm
Gm
Figure 6.1 Simplified block diagram of the fifth-order CT Δ-Σ A/D modulator.
6.2 First stage R-C integrator
As shown in Figure 6.2, a multi-bit current steering DAC feedbacks current
to the virtual grounds of the RC integrators, therefore good DAC linearity can be
achieved. This is another advantage compared with using a Gm-C integrator for the
first stage besides better integrator linearity. If a Gm-C integrator were used, the
DAC would have to connect to the high-swing integrator outputs, and hence DAC
linearity would be poor.
Two I BIAS current sources inject common mode currents to prevent a
common-mode offset from appearing at the amplifier virtual grounds [Kap03]. Two
small value resistors, RZ , are inserted in the amplifier feedback path to cancel the
right-half-plane zero in the RC integrator transfer function and alleviate the gainbandwidth requirement of the amplifier for loop stability.
71
The lower part of Figure 6.2 is the simplified representation of the current
steering DAC. Each cell contains a cascode current source and a pair of current
switches controlled by feedback thermometer digital codes.
0.5IDAC
0.5IDAC
RZ CFB
RIN
Vout-
Vin+
Vout+
VinRIN
...
RZ CFB
D1p
M4 M5
.....
D1n D2p
D2n
D16p
D16n
M3
M2 M1
DAC1
Figure 6.2 First stage R-C integrator with current steering DAC.
6.2.1 The OpAmp in the R-C integrator
The OpAmp in the R-C integrator uses a telescopic topology. Compared
with the two-stage OpAmps and folded-cascode OpAmps, telescopic OpAmps
achieve the highest speed with the lowest power consumption and they generate
low noise. Figure 6.3 shows the schematic of the telescopic OpAmp used in this
design.
72
NMOS transistors are used for the input pair to provide a high speed path
for the input. In addition, given the same biasing current and size, a NMOS
transistor has larger transconductance than a PMOS transistor. Therefore, input
referred thermal noise is lower when NMOS transistors are used for the input pair
than if PMOS transistors are used.
The major drawback of telescopic OpAmps is the limited output voltage
swing compared to folded-cascode OpAmps or two-stage OpAmps. In this design,
voltage scaling has been performed in the system level to make sure the output
swing of the first stage is not too large to impact linearity.
VDD
M9
M10 M7
M5
BIAS_P1
BIAS_PC
M8
M6
VCOM_CTR
VOUT_N
VOUT_P
M3
VIN_P
M11
M1
M4
M13 M2
VIN_N
M12
Figure 6.3 Telescopic OpAmp in the R-C integrator.
Figure 6.4 shows the common-mode feedback (CMFB) circuit for the
telescopic OpAmp along with the transconductor gain stage that connects to the
output. The integrator’s differential outputs become differential inputs to the
73
transconductor. The two local feedbacks force the voltage at node A to be equal to
VOUT_P and the voltage at node B to be equal to VOUT_N, hence the voltage at
node C is equal to (VOUT_P+VOUT_N)/2 [Cha97]. In this way we obtain the
common-mode voltage of the differential outputs of the telescopic OpAmp.
The same method is used for the following four Gm-C integrators to obtain
output common-mode voltages since each integrator is followed by a
transconductor gain stage with the same architecture as shown in Figure 6.4.
VDD
VCOM_CTR
VDD
M4
M3
VCOM_REF
Transconductor
(gain g1)
C
A R R B
-
VOUT_P +
M1 M2
+
VOUT_N
Figure 6.4 CMFB circuit in the telescopic OpAmp.
6.2.2 Modulator front-end noise analysis
The device noise at the modulator front-end is not attenuated and thus it is a
limiting factor in the total input referred noise of the modulator. There are three
sources for the noise of the front-end:
1. Noise of the two input resistors,
2. Noise of the telescopic OpAmp, and
74
3. Noise of the current steering DAC1 feedback to the virtual grounds of the
OpAmp.
The equations from here on in this section use k to represent Boltzmann
constant; T to represent absolute temperature; g mn to represent the transconductance
of the nth transistor; k P and k N to represent the flicker noise coefficients of the
PMOS and NMOS transistors, respectively.
The input referred noise, including thermal noise and flicker noise, of the
telescopic OpAmp shown in Figure 6.3 can be expressed as:
V n = 8kT γ (
1
2
g m1, 2
+
g m 7 ,8 + g m 9 ,10
g m1, 2
2
)+
2
2
(6.1)
g m 7 ,8
g m 9 ,10
KN
KP
KP
+2
+2
+2
2
(WL ) 1, 2 C OX f
(WL ) 7 ,8 C OX f g m1, 2
(WL ) 9 ,10 C OX f g m1, 2 2
The total in-band thermal noise equals:
Vin,th = 8kTγ (
1
2
g m1, 2
+
g m 7 ,8 + g m9,10
g m1, 2
2
)Δf
(6.2)
and the total in-band flick noise equals:
2
Vin ,1 / f
2
g m 7 ,8
KN
KP
Δf = ( 2
+2
+
(WL)1, 2 C OX f
(WL) 7 ,8 C OX f g m1, 2 2
2
(6.3)
g m 9,10
KP
+2
) ln( f max / f min )
(WL) 9,10 C OX f g m1, 2 2
In this design, the biasing current of the telescopic OpAmp is set to be
1.7mA for low thermal noise and the NMOS input pair is big with
W / L = 508.8μ / 0.6u . The large device size reduces the flicker noise and offset,
and, it reduces the overdrive voltage of the input transistors, hence increases the
linear output swing range.
The total in-band noise power of the two input resistors is:
2
V Rin = 8kTRin Δf
(6.4)
75
In this design, the value of the input resistors are chosen to be 833Ω,
generating thermal noise power 96.7dB lower than the full scale input signal.
The noise from DAC1 can be derived as the following.
Assume the DAC full scale current is IDAC. Looking at one single current
cell in the DAC shown in Figure 6.2, the major thermal noise is from transistors
M1 and M2. Thermal noise from M3, M4 and M5 are greatly attenuated because of
source generation. In the following DAC noise analysis, we will ignore noise from
M3-M5, focusing on noise from M1 and M2 only. The total in-band thermal noise
current from M1 and M2 can be expressed as:
n I = 4kTγ ( g m 1 + g m 2 )Δf = 4kTγ (
2 I1
2I 2
+
)Δf
VGS1 − VT 1 VGS 2 − VT 2
(6.5)
Here g m1 and g m 2 are the transconductances of M1 and M2, respectively,
VGS 1 − VT 1 and VGS 2 − VT 2 are the over-drive voltages of M1 and M2, respectively. In
our design, they are both close to 450mV. For simplicity, we assume that they are
equal to each other, and notice that
I1 + I 2 = I cell = I DAC / N
(6.6)
I cell is the DC current in each cell. Thus we obtain
nI =
8kTγI cell
Δf
VGS − VT
(6.7)
The total in-band thermal noise power from M1 and M2 can thus be
expressed as:
8kTγI DAC Rin
Δf
VGS − VT
2
n DAC =
(6.8)
The full-scale input signal amplitude is Rin I DAC , so the full-scale input
signal power is:
Psignal =
( Rin I DAC ) 2
2
(6.9)
76
The constant current biasing generated by the PMOS cascode current
mirrors also contributes noise. In our design, the over-drive voltages of the PMOS
transistors are close to those of the NMOS transistors M1 and M2, so the thermal
noise from the PMOS current biasing can also be expressed by Eq. (6.8).
From Eq. (6.8) and (6.9), we obtain the signal-to-noise due to the DAC
noise
SNR DAC =
Psignal
2n DAC
=
I DAC (VGS −VT )
32kTγΔf
(6.10)
Given a specified SNRD AC , the required DAC current is:
I DAC =
32kTγ ⋅ SNRDAC ⋅ Δf
VGS − VT
(6.11)
Given T = 300°K, γ = 2 / 3 , VGS − VT = 0.45V , SNR DAC = 90dB and
Δf = 2.5MHz , we obtain the required I DAC = 0.49mA .
In our design, we choose I DAC = 0.96mA , leaving about 3dB margin.
In this design, I DAC = 0.96mA , VOV = 0.45V , substituting these quantities
into Eq. (6.10), we get
SNR DAC1 = 92.9dB
(6.12)
Simulation in Spectre shows that the input referred in-band noise due to the
first stage integrator (including Rin and the OpAmp) and the DAC1 is about
386 pV 2 , about 89dB lower than full scale input power. The total input referred inband noise of the loop filter plus the two DACs is 556 pV 2 .
6.3 Gm-C transconductor design
With the exception of the first stage integrator, all the following four
integrators are implemented with Gm-C integrators to save power.
Figure 6.5 shows the attenuation of non-idealities at different stages in the
modulator. Due to the low oversampling ratio (12X), the first Gm-C integrator
77
requires more than 70dB linearity at the signal band edge. A folded-cascode
architecture is used that includes input driving amplifiers, source degeneration
resistors and gain boosting amplifiers as shown in Figure 6.6. It achieves the
required linearity and it has independent input-output common mode voltages as
well. The drawback of this topology is that the power consumption is higher than a
single-stage Gm-C integrator.
The two gain boosting OpAmps in Figure 6.6 are shown in Figure 6.7 and
Figure 6.8, respectively. They both have folded cascode topologies to
accommodate proper input and output common-mode voltages. Since they each
drive only the gate capacitance of the cascode transistors in the transconductor,
which are pretty small, they consume very little power, approximately 0.3mW.
Attenuation of non-idealities (dB)
0
-20
-40
Stage2
-60
-80
-100
Stage3
-120
-140
-160
Stage4
2.5MHz
Stage5
-180
-200 4
10
5
6
10
10
7
10
Frequency (Hz)
Figure 6.5 Attenuations of non-idealities for different stages in the loop filter.
78
VDD
M5 BIAS_P1
M4
M3
M6
R
VIN_P
+
M1
M2
+
M7
VOUT_N
VIN_N
C
V_CMFB
M8
VOUT_P
M9
M10
C
BIAS_N1
M13 M11
M12 M14
V_CMFB
Figure 6.6 Second stage Gm-C integrator architecture.
VDD
M5
M7
VIN_P
M1
M2
VIN_N
M9
VOUT_N
M3
M4
GND
M6
BIAS_P1
BIAS_PC
BIAS_NC
M11
BIAS_N1
M13
M8
M10
VOUT_P
M12
M14
Figure 6.7 Gain boosting OpAmp for the PMOS current mirror.
79
VDD
M3
M4
M5
BIAS_P1
M6
M7
BIAS_PC
M8
VOUT_N
VIN_P
M1 M2
VIN_N
VOUT_P
M9
M11
BIAS_NC
BIAS_N1
M13
M10
M12
M14
GND
Figure 6.8 Gain boosting OpAmp for the NMOS current mirror.
The latter three GM-C integrators share the same architecture for the same
reason, except that the two gain boosting amplifiers can be eliminated due to larger
suppression of their non-idealities by the high loop gain.
6.4 DAC with current calibration
Figure 6.9 shows the current cell in DAC1 employing calibration [Gro89,
Fal99]. The fundamental working principle is the following: M1 is the main
transistor which takes about 95% of the nominal current. M2, in parallel with M1,
is to compensate for the error current between standard current Iref and the current
in M1. M3 is a cascode transistor to increase the output impedance of the current
source and at the same time prevents dynamic glitches at node A from impacting
current in M1 and M2. When the calibration signal “CAL” is high, NMOS switches
M6 and M7 are both turned on. M6 conducts the standard current Iref into M1 and
M2 while M7 connects the gate of M2 to the standard current generation circuit.
Since the total current in M1 and M2 are forced to be equal to Iref, the difference
80
between Iref and the M1 current should flow through M2. This will create a proper
gate voltage for M2 and will be saved on the gate-source capacitance of M2. When
the calibration mode is over for this cell, the signal “CAL” goes low and the cell
enters operation mode. In this mode, one of the two current conducting switches
M4 or M5 will be turned on depending on the logic level of the input data D and D .
Since the gate-source capacitance M2 preserves the gate voltage acquired during
the calibration mode, the total current in M1 and M2, or the current in M3 will be
maintained at Iref. Hence either M4 or M5 will conduct current with a value of Iref.
The calibration is run for each cell in DAC1 in a circular way such that
every cell will be in either calibration mode or operation mode. Since the quantizer
generates 16-bit thermometer digital code, DAC1 should have 16 identical cells
that feed back currents to the modulator input terminal. Hence, in order not to
interrupt the calibration, there is an extra cell added into DAC1. Therefore there is
always one cell in calibration mode and the other 16 cells in operation mode,
assuring DAC1 operates continuously.
To Opamp virtual grounds
Iref+Ibias
Iref
V1
M11
M6
CAL
M4 M5
D
D
A
Iref
M3
V2
Ibias
M9
Biasing circuit
Shared by all cells
M7
M8
M2 M1
Current cell
M10
Biasing circuit
Shared by all cells
Figure 6.9 A current cell in DAC1.
81
There are several design issues involved in this block and all of them need
to be carefully studied and addressed in order not to adversely affect the DAC
performance.
6.4.1 Charge injection
NMOS-only switch M7 connects the error-compensation transistor M2 to
the biasing circuit and it is turned on when the current cell is in the calibration
mode. When M7 is turned off, the resultant charge injection can change the current
stored in M2, hence the total current of this cell. Due to the size mismatch of M7
and M2 in all cells, this charge injection error will increase the nonlinearity of
DAC1.
The solution is to add two NMOS transistors M8 and M9 in series with M7
whose size are both half of that of M7 and their drains and sources are shorted, as
shown in Figure 6.9. With such a technique, the injected charge from M7 when it is
turned on will be absorbed by M8, therefore the charge injection error can be
greatly reduced. Simulation in Spectre verified the significant improvement using
this technique.
6.4.2 Clock feedthrough
The clock feedthrough introduced when switching input data D and D can
lead to voltage excursions at current switch M4 and M5’s drain and source nodes.
As a result, the output current needs more time to settle. This problem can be
alleviated by using low-swing D and D .
6.4.3 Glitch at source node of M4 and M5
If for period of time both M4 and M5 are turned off, their source node, A in
Figure 6.9, will drop significantly and then rise back to its normal value when one
of the switches is turned on. This glitch can cause long settling times of the output
current. The delay and the shape deviation from its idealities in the output current
82
will change the transfer function of the DAC. As a consequence, the modulator
performance may be degraded.
A low-swing, high-crossing generator is used in this modulator to convert
full-swing and middle-crossing D and D to low-swing, high-crossing digital
signals, as shown in Figure 6.10. Low-swing can reduce clock feedthrough and
high-crossing can prevent the two current switches from turning off simultaneously
to minimize glitch energy.
2.5V
Low swing, High crossing
signal generator
VA
0.7V
VA
Figure 6.10 Low-swing, high-crossing signal generation in current steering DAC.
To generate high crossing, low swing digital signals for both calibration
control signals and digital input codes to the current cells, a full-PMOS driver
[Fal99] is used, as shown in Figure 6.11. The relative sizes of the transistors in the
stacks determine the crossing point and rising and falling time of the outputs. The
cascode transistors are added to reduce the coupling between the full swing input
signals and the low swing output signals.
83
1.8V
IN
8μ / 0.24μ
IN
8μ / 0.24μ
8μ / 0.24μ
OUT
OUT
2 μ / 0.24 μ
IN
2 μ / 0.24 μ
8μ / 0.24μ
2 μ / 0.24 μ
IN
2 μ / 0.24 μ
1.1V
Figure 6.11 High crossing, low swing complementary digital signals generator.
The high level and low level of the output signals, 1.8V and 1.1V,
respectively, are carefully chosen to make sure that the switches can be fully turned
on/off with sufficiently low unwanted clock feedthrough and charge injection.
Figure 6.12 shows the complete control logic for each DAC current cell
except the spare cell (the control logic for the spare cell is more complicated).
DATA is the input digital code and CAL_ENA is the calibration control signal.
They are both synchronized by CLK which is a low jitter clock signal. CAL_HX
corresponds to CAL in Figure 6.9 DATA_HX and DATA_B_HX correspond to D
and D in Figure 6.9, respectively. When CAL_ENA is high, DATA_HX and
DATA_B_HX are both low, meaning the cell is in calibration mode. When
CAL_ENA goes low, either DATA_HX or DATA_B_HX is high depending on the
logic level of DATA.
84
D
CAL_ENA
SET
CLR
DATA
CAL_ENA
D
SET
CLR
DATA
CAL_ENA
D
SET
CLR
Q
Low swing,
High crossing
signal generator
CAL_HX
Low swing,
High crossing
signal generator
DATA_HX
Low swing,
High crossing
signal generator
DATA_B_HX
Q
Q
Q
Q
Q
CLK
Figure 6.12 Synchronizing circuit for each cell in DAC1.
DAC2 uses PMOS current cells because its output is connected to a low
potential which is only about 400mV more than the negative supply (ground in this
design). Hence for DAC2, a pair of low-swing, low-crossing digital signals are
needed. A similar, but fully NMOS version of the circuit in Figure 6.11, is designed
to generate low-swing, low-crossing complementary signals.
6.4.4 Low jitter clock generation
All the current cells in DAC1 are synchronized by a clock as shown in
Figure 6.12 . This clock needs to have sufficiently low jitter in order not to increase
the modulator output noise floor due to non-shaped jitter noise. In this design,
system level simulations show that less than 6ps clock jitter is required. Some
85
design strategies are adopted to minimize clock jitter due to device and supply
noise. Figure 6.13 shows the simplified circuit to generate the low jitter clock.
VDDD
CLK_DAC_SYNC_SLAVE
Sinusoidal
differential input
To generate other clocks
Differential-to-single end converter
Figure 6.13 Low-jitter on-chip clock generation.
To reduce common mode noise probably coupled to the testing board and to
obtain the least amount of clock jitter from the external clock source, sinusoidal
differential clock inputs are generated on board and fed to the modulator. It is
critical to use as few clock driver stages as possible to generate the low jitter clock
with sufficient driving capability because any extra stages generate extra device
noise, hence larger clock jitter. The D flip flops in DAC1 have a master-slave
topology so that the low jitter clock only needs to drive their slave stages [Fal99],
therefore its capacitive loading can be decreased and fewer driving stages are
needed. To reduce the supply noise, a dedicated and clean supply is used solely for
the low jitter clock generation circuit. Simulation in Spectre shows that the clock
jitter due to on-chip device noise is less than 0.7ps.
6.5 Summing block
The summing block is shown in Figure 6.14 together with a feedforward
gain stage and a simplified DAC2 current cell. The five transconductor gain stages
86
convert the five integrator outputs from voltages into currents and inject the
currents to two folding nodes A and B in the summing block. The current cells in
DAC2 also inject currents into nodes A and B. The summed differential currents
are converted back to differential voltages through two pull up resistors. A gain
boosting OpAmp is used to increase the output impendence of the NMOS cascode
current mirror as well as the linearity of the summing block.
Figure 6.14 Summing block.
6.6 Sample and hold
In Figure 5.6, since the output from the summing block is directly sampled
by the quantizer, two problems arise. First, the pull up resistors and the large
sampling capacitors from the 16 comparators make the settling of these nodes
problematic. In fact, this extra R-C filter changes the loop transfer function.
87
Additionally, the outputs of summing block contain high frequency signals, as a
result, slew-dependent errors may occur [Raz95].
A solution for the above two problems is to add a sample and hold (S&H)
stage after the summing block and before the quantizer. It not only provides a flat
input signal for the quantizer but also acts as a buffer between the pull-up resistors
in the summing block and the large input capacitors in the quantizer [Yan04].
Figure 6.15 shows the sample and hold stage. During phase2, the
differential outputs of the summing blocks are sampled onto the capacitors. During
phase1, the sampling capacitors flip across the OpAmp differential inputs and
outputs, holding the sampled differential voltages.
Φ1
Φ2
Vin+
C
Φ 2e
VoutVCM
Vin-
Vout+
C
Φ1
Figure 6.15 Sampling and hold stage.
To better illustrate the timing for the S&H stage and the quantizer, Figure
6.16 shows the circuits of the summing block, S&H and a comparator. The
comparator has one pre-amplifier stage and one latch stage. It uses the offset
cancellation technique illustrated in Figure 4.7.
88
During phase-2, the S&H stage samples the outputs of the summing block
and the quantizer enters offset cancellation mode during which all comparator
inputs are connected to corresponding reference voltages. During phase-1, the S&H
stage enters the holding mode. Phase-3 is a slightly delayed version of phase-1.
During this phase, the quantizer samples the outputs of the S&H block. Phase-4 is
the regeneration clock, during which the regenerative latch generates valid digital
output.
Φ1
Φ2
Φ3
Φ4
Φ1
RPULL-UP Φ 2
RPULL-UP
C
Vrefp
Φ 2e
M8
Φ3
Φ3
M9
Vrefn
C
BIAS_N1
M10
M11
Summing block
Φ2
Φ2
Φ 2e
+
+
Φ4
Regenerative
latch
Φ 2e
Φ1
Sample and Hold
Comparator
Figure 6.16 Summing block, S&H block and comparator.
There is a trade-off in choosing the value of the pull-up resistors. A large
value can reduce the DC biasing currents in all feedforward stages. This is because
the feedforward gain is determined by the ratio between the pull-up resistors and
the source degeneration resistors in the feedforward transconductors. The larger the
pull resistors, the larger the source degeneration resistors are, hence the smaller DC
biasing currents that are needed for those transconductor stages. However, the time
89
constant due to the pull-up resistors and the sampling capacitors in the S&H block
should not be too large so that sufficient settling is achieved. Careful simulations,
taking into account possible process variations, shall be performed to find the
proper value for the pull-up resistors.
By adding a S&H stage in front of the quantizer and arranging the timing as
just described, the loop architecture shown in Figure 5.6 can be modified as in
Figure 6.17. The major difference is that the D-latch array after the quantizer is
omitted because there is still one digital delay between the quantizer output and
input due to the existence of the S&H block.
In Figure 6.17, Φ1 corresponds to “ Φ1 ” in Figure 6.16 and Φ1D
corresponds to “ Φ 4 ” in Figure 6.16. Φ1 _ low _ jitter is the low jitter clock driving
DAC1. Nominally it is in phase with Φ1 in S&H stage.
g1
g2
g3
k1
ST
u
k2
ST
d1
k3
ST
k4
ST
k5
ST
g5
gz2
g z1
DAC1
g4
d2
NRZ DAC
NRZ DAC
Q
Q
SET
D
S/H
Φ1
y
Φ1D
DAC2
Φ1 _ low _ jitter
CLR
DFF
Figure 6.17 Modified loop topology of the modulator.
6.7 Quantizer
Figure 6.18 shows the 17-level flash ADC used for the quantizer in this
design. Figure 6.19 shows the comparator circuit. The comparator has a pre-
90
amplifier stage to reduce kick-back noise [Joh97]. In addition, a switched capacitor
input offset cancellation technique is adopted to suppress offset from both the preamplifier and latch stages.
Vin+ VinΦ 2e
R/2
Vref16 Vref16
R
Vref1
Φ1
Φ2
Strobe
+
Φ1
LATCH
OUT16
+
Φ2
...
Φ 2e
Φ 2e
R
Vref9
Vref9
R
Vref8
R
Vref8
Φ1
Φ2
Strobe
+
LATCH
Φ1
Φ2
OUT9
+
...
Φ 2e
Φ 2e
Vref1
R/2
Vref1
Vref16
Vref-
Φ1
Φ2
Φ1
Φ2
Strobe
+
LATCH
+
Φ 2e
Figure 6.18 17-level quantizer.
OUT1
Thermometer-to-Binary Encoder
Vref+
D5
D4
D3
D2
D1
91
VDD
M3 M5
Limiter
MID_N
M15
M6 M4
MID_P
M13
M16
M14
OUT_P
M11
VIN_P
M1
M12
M2
Reset
Reset
VIN_N
M7 M9
Pre_amplifier
M10M8
Regenerative Latch
OUT_N
SR Latch
Figure 6.19 Comparator.
The pre-amplifier is a low gain single-stage amplifier with gain of 10. The
limiter can constrain the swing of the pre-amplifier for faster speed. The
regenerative latch outputs are pulled down to “0” when the “Reset” signal is “1” to
eliminate “memory”. When “Reset” goes low, the regenerative latch amplifies the
difference at its inputs to full scale. The inverter immediately after the regenerative
circuit is sized so that unwanted turn over won’t happen because of the temporary
voltage jump when “Reset” changes from low to high [Gee00].
The 17-bit thermometer-code outputs from the 5-bit quantizer are converted
to 5-bit binary codes with a Wallace-tree thermometer-to-binary encoder as shown
in Figure 6.20.
This encoder counts the number of “1s” in the 17-bit input signal. This
encoder is not the fastest solution for thermometer-to-binary conversion but it is the
most hardware economic one. As long as the worst case conversion time is less
than a clock period, this encoder is good enough. Simulation shows that the worst
case conversion time is about 4.5ns, which is much less then clock period, 16.67ns.
92
It should be mentioned that the Wallace tree can effectively “kill” bubbles
which may occur at the output of the flash ADC [Raz95, Joh97]. For example, if at
some instant the thermometer-code is “000•••1011111” with one bubble. The
Wallace tree will generate a binary code as “00110” as if the output is
“000•••0111111”. Hence a dedicated bubble-killer circuit after the quantizer as in
[Jia01] is not needed in this design.
DAT[15]
DAT[14]
DAT[13]
DAT[12]
OUT[0}
(LSB)
DAT[11]
DAT[10]
OUT[1}
DAT[9]
DAT[8]
DAT[7]
DAT[6]
DAT[5]
OUT[2}
DAT[4]
DAT[3]
DAT[2]
DAT[1]
DAT[0]
OUT[3}
OUT[4}
(MSB)
Full adder
Half adder
Figure 6.20 Wallace tree decoder.
93
6.8 Output driver
To drive the 5-bit binary codes off chip for testing without introducing extra
digital switching noise, a differential pairs, as shown in Figure 6.21, is used to
convert each bit from full swing digital signals to current signals which are taken
off chip and converted back to low-swing voltages (about 400mV) by off-chip pull
up resisters. Then high speed comparators on the testing board amplifies these low
swing signals to full swing signals.
Figure 6.21 Output driver of the CT modulator.
6.9 Clock generator
Figure 6.22 shows the simplified circuit diagram to generate clocks in
Figure 6.16Figure 6.16 . Extreme process variations (slow model and fast model)
have been taken into account in the design and simulations to make sure the timing
is always correct.
94
Φ3
Φ4
Variable delay cell
Delay cell
CLK_IN
Φ1
Φ2
Φ 2e
Figure 6.22 Clock generator.
Ideally, as shown in Figure 6.17, the synchronizing clock in DAC1 and the
holding phase clock in the S&H stage should have the same phase. However, when
taking the finite response time of the DAC1 current cells into account, the former
clock should be an earlier version of the latter one. The proper timing relationship
between these two phase clocks can be obtained by running extracted view
simulations including parasitic resistors and capacitors. In this test chip, for the
sake of flexibility and debugging easiness, a variable delaying cell, as shown in
Figure 6.22, is added in the path.
Figure 6.23 shows the variable delay cell circuit. By adjusting the biasing
current offered from the testing board, variable delaying time can be acquired. The
sizing of the transistors in this circuit depends on how much delay tuning range is
needed.
95
VOUT
VIN
Figure 6.23 Variable delay cell.
6.10 Time constant tuning
The large time constant shift due to process variations in practical
continuous time circuits can degrade system performance to an unacceptable level.
For CT Δ-Σ A/D modulators, +/-20% variation is more than enough to drive the
modulator into unstable operation. To tackle this issue, we apply a capacitor array
tuning method to adjust the time constants.
Figure 6.24 shows the two types of integrators, the R-C integrator and the
Gm-C integrator, in this design. Both of their integration capacitors are realized by
an adjustable capacitor array as shown in Figure 6.25 [Yan04].
To ease the capacitor tuning, it has been designed at the system level so that
the integration capacitors in all integrators have the same value except the first
stage whose capacitor values are doubled to reduce the input resister values for
noise consideration. Hence, only two different types of capacitor arrays are needed
in this design.
The capacitors in the arrays are binary-sized except the “always-in-use”
capacitors. This sizing method is to provide constant tuning step with the least
96
number of capacitors and to ease layout. The 3-bit digital control codes are fed
externally to choose which capacitors to use.
C
+
C
Rin
Vo
+
Vi
-
+
vi
-
+
+
-
-
Gm
+
vo
C
Rin
C
(a)
(b)
Figure 6.24 Two types of integrators used in this design (a) R-C integrator (b) GmC integrator.
Figure 6.25 Tunable capacitor array.
97
The total in-use capacitor value is:
C in −use = C + k ⋅ C '
( k = 0 ~ 7)
(6.13)
Where C ' is the minimum capacitor in the array and it equals the tuning step
size.
The maximum available capacitance in the array is:
C max = C + 7C '
(6.14)
The minimum available capacitance in the array is:
C min = C
(6.15)
The tuning range of the integration capacitor arrays is:
m=
C max
7C '
= 1+
C min
C
(6.16)
C'
C + 3C '
(6.17)
The tuning accuracy is:
p=
The value of C and C ' are chosen such that C + 3C ' equals the nominal
value of the integration capacitor.
It is apparent that there is a trade-off here between the tuning range and
tuning accuracy. To obtain wide tuning range, the tuning accuracy is sacrificed, and
vice versa. Based on the system level simulation results in MATLAB, the ratio
between C ' and C is chosen to be 0.1, thus, the tuning range and tuning accuracy
are 1.7 and 7.7%, respectively, which suffice for the requirements for this
modulator according to simulation results shown in Figure 5.9 .
6.11 Layout design considerations
The continuous-time delta-sigma modulator is essentially a mixed signal
system. It contains continuous-time blocks such as the fifth-order loop filter. It
includes sampled data blocks such as the S&H stage and the multi-bit quantizer. It
also has purely digital blocks such as the control logic in current calibration and
98
thermometer-to-binary code converter. To achieve high resolution and linearity, a
great deal of caution should be taken in the layout design to reduce the effects of
mismatch, parasitics and digital noise coupling to analog blocks.
Figure 6.26 shows the chip die photo of the CT modulator which labels
some major blocks. The main considerations for the floor-plan are to minimize the
coupling from digital blocks to analog blocks, offset and parasitics. Several
commonly used layout techniques were employed, such as common-centroid layout
for capacitors, inter-digitation for transistors, guard ring and shielding. In DAC1, a
deep n-well was inserted between the array of digital control logic and current cells
to further reduce the noise coupling.
Output driver
Quantizer
DAC-2
Clock
generator
S&H
Adder
Resonator-2 &
two gain stages
Resonator-1 &
two gain stages
DAC-1
First Integrator &
one gain stage
Figure 6.26 Chip die photo.
99
In the circuit level, current calibration was utilized to suppress mismatch
among all cells in the DAC1. In the layout level, a technique, called symmetrical
sequence [Con02], can be used to further reduce linear gradient errors. The basic
idea of this technique can be illustrated by Figure 6.27. In the DAC layout, all
even-numbered current cells are placed on one side of the array center while all
odd-numbered current cells are placed on the order side. In this way, linear errors
are cancelled by every two cells located symmetrically about the center.
We used this technique for both DACs. This technique is “free’ because it
doesn’t add any complexity to the digital control logic.
Error
0
15 13 11 9
7
5 3
1
0
2
4
6
8 10 12 14 16
Figure 6.27 Current steering DAC layout with symmetrical sequence.
Unlike most DT data converters, the layout of clock generator in this circuit
has been physically divided in two parts. The reason is that the clock to drive
DAC1 should have low jitter (<6ps), therefore a dedicated power supply is used for
generating this clock phase to prevent noise coupling from other digital circuitry.
Since there is no stringent jitter requirement for other clocks and digital control
signals, they are grouped together in the other clock generator.
100
7.
TEST SETUP AND EXPERIMENTAL RESULTS
7.1 Test board design
Two four layer printed circuit boards (PCBs), one daughter board and one
mother board have been designed to test the prototype chip. The two boards are
connected as shown in Fig 6.1.
DUT
Daughter Board
Connector
Mother Board
Figure 7.1 Two PCB boards for testing the prototype chips
On the daughter board is the prototype chip, the circuits to generate a low
noise input signal and the low jitter clock signal. Plenty of decoupling capacitors
are placed as close as possible to the DUT to reduce supply and ground noises. The
mother board has analog and digital supply generation circuitry, DC biasing
circuitry, digital control circuitry and an output data processing block.
The advantages of using two, rather than one, boards to test the chip are
twofold. First, the coupling between digital and analog sections on the boards can
be reduced. Second, since the packages of the prototype chips are 64-pin QFN
which are very hard to solder, to facilitate testing multiple chips, each daughter
board has one prototype chip. In this way, we can easily change chips just by
unplugging one daughter board and replacing it with the other one.
Figure 7.2 shows the layouts of both boards.
101
(a)
(b)
Figure 7.2 The testing boards (a) daughter board (b) mother board.
Figure 7.3 shows the photo of the assembled daughter board and mother
board.
Figure 7.3 Assembled testing boards.
102
7.2 Test environment setup
Figure 7.4 depicts the configuration of the instruments used to evaluate the
performance of the prototype chips. The differential sinusoidal input signals are
produced by the audio precision (System Two•2322). The synthesizer/function
generator HP 3325B is used to generate low speed calibration signal. The
synthesized signal generator HP 8665A is used to provide low jitter clock signal for
the DAC1 in the modulator. It also triggers the Tektronix HFS 9030 precision pulse
generator which generates all other clock and digital control signals. The modulator
digital outputs are captured by the logic analyzer TLA720. The FFT analysis of the
output data are performed in MATLAB using a PC connected to the logic analyzer.
RF
generator
Pulse
generator
Low jitter clock
For other clocks
Vin+
Audio
precision
Vin-
DC sources
DC sources
+/- 5V
Test Board
Logic
analyzer
3.3V
Calibration signal
Signal
synthesizer
Figure 7.4 Experimental test setup.
103
7.3 Measurement results
The prototype chips have been tested with a clock frequency of 60MHz and
an input signal 100KHz. Since the signal bandwidth is 2.5MHz, up to the 24th
harmonics of the input signals can be seen in the output spectrum if there are any.
The achieved peak SNDR is 80.5dB, peak SNR is 81dB and peak SFDR is 98.4dB.
Dynamic range (DR) is 85dB.
Figure 7.5 plots the measured SNDR, SNR and SFDR versus input
amplitude.
100
SNDR
SNR
SFDR
SNR, SNDR and SFDR (dB)
90
80
70
60
50
40
30
20
10
0
-90
-80
-70
-60
-50
-40
-30
-20
-10
0
Input amplitude (dB)
Figure 7.5 SNDR, SNR and SFDR versus input amplitude with a clock frequency
of 60 MHz and an input frequency of 100 KHz.
Figure 7.6 and Figure 7.7 show the output spectrum for -2.5dBFS 200KHz
input signal with and without DAC calibration. With calibration, SNDR is 80.2dB
and SFDR is 97.1dB. However, without calibration, we can see an increase in the
noise floor and the input signal harmonics. SNDR drops to 69dB and SFDR drops
104
to 70.4dB. These results validate the functionality and effectiveness of the DAC
calibration implementation in this work.
Power Spectral Density (dB/bin)
0
-50
-100
-150
10
4
5
10
10
6
10
7
Frequency (Hz)
Figure 7.6 Output spectrum with calibration for -2.5dBFS 200KHz input.
Power Spectral Density (dB/bin)
0
-50
-100
-150
10
4
10
5
10
6
10
7
Frequency (Hz)
Figure 7.7 Output spectrum without calibration for -2.5dBFS 200KHz input.
105
As Figure 5.9 implies, varying tuning code will change the modulator
performance, Figure 7.8 shows the measured SNDR versus tuning code for a 2.5dBFS 200KHz input signal. The MSB and LSB of the tuning code represent the
digital code to control the MSB capacitor 4C’ and LSB capacitor C’, respectively,
as shown in Figure 6.25 . The modulator is stable for tuning code “101”, “110” and
“111” but unstable for tuning code less than “100”. This result indicates that the onchip time constants are smaller than the ideal numbers. The SNDR drop with
increasing tuning code is very small (about 0.4dB for each step from “101” to
“111”). It is because the final modulator SNDR is not limited by the quantization
noise, but more likely limited by device noise, DAC mismatch errors and jitter
noise.
85
80
75
70
SNDR (dB)
65
60
55
50
45
40
35
30
100
101
110
111
Tuning code
Figure 7.8 SNDR versus tuning code for -2.5dBFS 200KHz input signal
A two-tone test has been performed. The input frequencies were 190KHz
and 210KHz, respectively. Both of them have -9dBFS amplitude. Figure 7.9 shows
the output spectrum of the testing. The measured IM3 (third-order intermodulation)
is 80.3dB. If the input amplitudes of the two signals drop to -12dBFS, the measured
106
IM3 is 84.4dB, as shown in Figure 7.10. Figure 7.10Linearity degradation with
increasing signal amplitude has been observed.
Power Spectral Density (dB/bin)
0
-50
IM3=80.3dB
-100
-150 4
10
5
10
10
6
Frequency (Hz)
Figure 7.9 Output spectrum of two-tone test for -9dBFS inputs
Power Spectral Density (dB/bin)
0
-50
IM3=84.4dB
-100
-150 4
10
5
10
10
6
Frequency (Hz)
Figure 7.10 Output spectrum of two-tone test for -12dBFS inputs
107
Table 7.1 lists the measured peak SNDR for different input frequencies. The
choice of the input signal frequencies are based on the availability of band-pass
filters in our testing lab.
Table 7.1 Peak SNDR with different input frequencies
Input frequency (Hz)
Peak SNDR (dB)
100K
80.5
200K
80.4
500K
80
1M
77
2M
73
When the input frequency becomes higher, the modulator’s peak SNDR is
lower. There are two possible reasons for this performance degradation: 1. The
parasitic capacitances on the PCB and the chip manifest themselves more
significantly when the input signal frequency is high, therefore the linearity in the
signal processing path is lower. 2. When the input frequency is larger than 1MHz,
most of the harmonics are out of band and some of them are close to the peaking
frequency of the signal transfer function, hence they can be amplified and aliased
back into the signal band, increasing the noise floor or even worse, causing the
modulator to become unstable.
Table 7.2 summarizes the measured characteristics of the prototype chip.
108
Table 7.2 Summary of the measured chip results.
Specifications
Values
Peak SNDR
80.5dB
Peak SNR
81dB
Peak SFDR
98.4dB
Dynamic range
85dB
Input signal bandwidth
2.5MHz
Clock frequency
60MHz
Oversampling ratio (OSR)
12
Power supply
2.5V
Power consumption
50mW
Die area w/o pads
2.1mm × 1.3mm
Die area w/ pads
2.5mm × 1.7 mm
Fabrication Process
0.25μm 5-matel mixed/RF CMOS
7.4 Comparison between this work and reported designs
Table 7.3 lists previously reported CT Δ-Σ A/D modulators that digitize
MHz signals. Compared with them, this modulator is the first one that achieves 14bit dynamic range with more than 2MHz signal bandwidth.
109
Table 7.3 Performance summary of reported design and this work.
Refs
Performance
Loop
Quantizer
(dB)
order
levels
Signal
Clock
bandwidth
frequency
(MHz)
(MHz)
Process
Power
[Vel02]
70 (DR)
4
3
2
153.6
0.18µ, 1.8V
11.5
[Yan04]
88 (DR)
3
31
1.1
35.2
0.5µ, 3.3V
62
[Put04]
77 (DR)
3
2
1.1
281.6
0.18µ, 1.8V
6
[Uen04]
53.2 (SNR)
2
5
1.92
61.44
0.13µ,0.9V
1.5
[Pat04]
64 (DR)
4
16
15
300
0.13µ, 1.5V
70
{Nag05}
70 (DR)
4
2
1.3
132
0.11µ, 1.2V
3.4
[Dör05]
74 (SNR)
3
16
2
104
0.13µ, 1.5V
3
85 (DR)
5
17
2.5
60
0.25µ, 2.5V
50
This
work
[Vel02] uses a 3-level, rather than a 2-level quantizer and DAC to reduce
quantization noise and jitter error without introducing DAC non-linearity. Since the
design targeted only 12-b dynamic range, 3-levels is enough. To achieve better than
12-b dynamic range, more quantization and DAC levels have to be used.
[Yan04] uses a single-stage, dual-loop architecture to relax the quantizer
delay. It has a 31-level quantizer with 16X oversampling ratio. It uses a revised
current-calibration scheme [Raz95] to suppress the DAC mismatch in the loop.
Automatic capacitor tuning is implemented to overcome time-constant variation.
[Uen04] features low supply voltage operation. It has a second-order loop
with a 5-level quantizer. Since the required resolution is relatively low, no DAC
mismatch suppression is included in the design.
[Put04] has a high oversampling ratio (128) so that a one-bit quantizer is
sufficient to achieve the required resolution. Instead of a one-bit DAC, a finiteresponse DAC (FIRDAC) is used to generate a multi-level signal thus reducing
clock jitter sensitivity. This “multi-bit” DAC is linear so that no DEM or
calibration is needed to address mismatch error.
110
[Nag05] uses passive current summing networks to save power. The first
stage is a R-C integrator while the other stages are Gm-C integrators to reduce
power consumption. It uses a single bit quantizer thus no DEM or calibration is
needed for the DAC. A SC-DAC is used for low jitter sensitivity.
[Dör05] uses a tracking-ADC to realize a 4-bit quantizer with only three
comparators, thus reducing the power consumption of the quantizer to 20%. In
addition, it uses passive feedforward gain stages, instead of transconductors, to
save power and omit the need for a summing block. It uses a revised DWA to
suppress DAC mismatch error. The DEM block is outside the critical feedback path
so that it doesn’t add excess loop delay. The integrators in this design are all R-C
integrators, hence the power consumption could be further reduced by replacing
them, except the first stage, by Gm-C integrators, without losing performance.
Generally speaking, to acquire 14-b or better dynamic range for MHz range
CT Δ-Σ A/D modulators, high order loop is needed for steep noise shaping; multibit quantizer and DAC are needed to suppress both quantization noise and jitter
error; DEM or calibration has to be utilized to reduce the multi-level DAC
mismatch error; Time-constant tuning should be included to adjust the
unpredictable RC products. All these measures will increase chip area and power
consumption.
111
8. CONCLUSION
8.1 Summary
In this work, the following techniques have been utilized to achieve low
power consumption and high resolution for a wide-band CT Δ-Σ A/D modulator.
1.
A high-order loop filter is implemented to provide sufficient noise
shaping for the quantization noise and internal sampling error.
2.
A Multi-bit quantizer is used to greatly reduce the quantization
noise and enhance loop stability.
3.
A large but appropriate noise transfer function out-of-band gain
(gain equals 4) is chosen to reduce in-band quantization noise
power while maintaining loop stability for large input signals.
4.
Optimally spread noise transfer function notches in the signal band
to offer extra quantization noise attenuation.
5.
A dual-loop architecture is chosen to relax the quantizer delay
requirement, addressing the issue of excess loop delay.
6.
Non-return-to-zero (NRZ) multi-bit DACs to reduce clock jitter
sensitivity.
7.
Integration of capacitor tuning to overcome the time constant shift
due to process variations.
8.
On-chip self-calibration is realized for the multi-bit DAC to
suppress mismatch error.
9.
Except for the first stage, all stages are Gm-C integrators to reduce
power consumption.
Combining all the above techniques, the modulator achieves 80.5 dB peak
SNDR, 81 peak SNR, 85 dB DR and 98.4 peak SFDR. Clocked at 60 MHz, the
modulator consumes only 50mW power.
112
This modulator is the first reported CT Δ-Σ A/D modulator obtaining 14-bit
DR for more than 2MHz signal bandwidth.
8.2 Future work
To design CT Δ-Σ A/D modulators for even wider bandwidths with high
resolution, several design issues existing in this work can be further explored in the
future.
1.
A drawback of the dual-loop topology is that it needs a second
multi-bit DAC which consumes more area and power. Some
different methods of addressing excess loop delay may be found
to achieve the same goal without introducing one more DAC.
2.
For applications such as VDSL, the signal bandwidth is more
than 10MHz. In such cases, the clock frequencies will be as large
as a few hundreds MHz. Hence the clock jitter issue becomes
more critical. Some non-rectangular DAC shapes, for instance, an
exponentially decaying DAC, might be worth exploring to reduce
further reduce clock jitter sensitivity.
3.
Some other loop filter topologies may have less coefficient
sensitivity so that they are more resistant to time constant
variations.
4.
As the number of quantizer bits increases, the in-band
quantization noise is lowered and the jitter sensitivity is reduced.
However, the area and power consumption of the quantizer and
the DAC will be increased. There are definitely some trade-offs
that exist here. More theoretical analysis can be performed to find
the best balancing point given the required bandwidth, resolution
and fabrication process.
5.
Various design strategies can be adopted in the future to lower the
power consumption. For example, more aggressive power scaling
113
can be done based on circuit level simulation to further reduce the
power consumptions of the latter stages in the forward loop; the
multi-bit quantizer doesn’t necessarily need 2N comparators (N is
the number of bits of the quantizer). It can use only threecomparators to realize multi-bit functions [Dor05]; Of course,
process with lower power supply and shorter channel length will
also help to reduce the power consumption, especially the power
dissipated in digital blocks.
6.
Some
Automatic
implemented.
on-chip
tuning
can
be
designed
and
114
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APPENDICES
121
Appendix A: Map loop filter HC(s) to single-stage dual-loop coefficients
The fifth-order loop filter H C ( s ) has the following format:
H C ( s) =
a 4 ⋅ ( sT ) 4 + a3 ⋅ ( sT ) 3 + a 2 ⋅ ( sT ) 2 + a1 ⋅ ( sT ) + a 0
(A.0.1)
b5 ⋅ ( sT ) 5 + b4 ⋅ ( sT ) 4 + b3 ⋅ ( sT ) 3 + b2 ⋅ ( sT ) 2 + b1 ⋅ ( sT ) + b0
~
The s-domain loop filter corresponding to H ( z ) in Eq. (5.6) is:
~
H C (s) =
3.821 ⋅ ( sT ) 4 + 2.908 ⋅ ( sT )3 + 1.783 ⋅ ( sT ) 2 + 0.641 ⋅ ( sT ) + 0.115
( sT )5 + 0.076 ⋅ ( sT )3 + 0.0011 ⋅ ( sT )
(A.2)
Derive the H ' C ( s ) based on Figure 6.17 and then equalize it to Eq. (A.2),
we obtain
k1 ⋅ g1 = 3.821
(A.3)
k1 ⋅ k 2 ⋅ g 2 = 2.908
(A.4)
k1 ⋅ k 2 ⋅ k 3 ⋅ ( g1 ⋅ g z1 + g 3 ) + k1 ⋅ k 4 ⋅ k 5 ⋅ g1 ⋅ g z 2 = 1.783
(A.5)
k1 ⋅ k 2 ⋅ k 4 ⋅ (k 5 ⋅ g 2 ⋅ g z 2 + k 3 ⋅ g 4 ) = 0.641
(A.6)
k1 ⋅ k 2 ⋅ k 3 ⋅ k 4 ⋅ k 5 ⋅ ( g 5 + g1 ⋅ g z1 ⋅ g z 2 + g 3 ⋅ g z 2 ) = 0.115
(A.7)
k 2 ⋅ k 3 ⋅ g z1 + k 4⋅ ⋅ k 5 ⋅ g z 2 = 0.076
(A.8)
k 2 ⋅ k 3 ⋅ k 4 ⋅ k 5⋅ ⋅ g z1 ⋅ g z 2 = 0.0011
(A.9)
MATLAB Symbolic toolbox can be used to solve the above 7 equations.
Since we have 12 variables but only 7 equations, we have to assign some initial
values to five of them and then solve the others. Dynamic scaling is needed to
make sure every stage’s output has reasonable swing.
The following is the MATLAB code to obtain CT loop filter transfer
function from Eq. (5.5) and solve for all coefficients in Figure 6.17.
%MATLAB code to calcualte the loop coefficients in the fifth-order
%CT %modulator
clear all;
close all;
122
digits 8;
Fs = 60e6; % Sampling Frequency
N = 5;
% Order
osr=12;
% Oversampling ratio
H_inf=4; % Maximum out-of-band gain of NTF
NTF=synthesizeNTF(N,osr,1,H_inf,0); % acquire H(z)
Hz=1/NTF-1;
[num_dt,den_dt]=zp2tf(Hz.z{:},Hz.p{:},Hz.k); % DT forward loop
[num1,den1]=zp2tf(Hz.z{:},Hz.p{:},Hz.k);
Hz_tmp1=Hz/tf([0,1],[1],'Variable','z^-1');
% Hz_tmp1=H'(z)+a1/b0 in Eq. (5.5)
[num2,den2]=zp2tf(Hz_tmp1.z{:},Hz_tmp1.p{:},Hz_tmp1.k);
Hz_tmp2=tf(num2,den2,'Variable','z^-1');
Hz_new=Hz_tmp2-num1(2)/den1(1);
% Hz_new=H'(z)in Eq.(5.5) and Eq.(5.6)
k_DAC2=num1(2)/den1(1);
% k_DAC2=a1/b0, gain of DAC2
[num3,den3]=tfdata(Hz_new,'v');
[num_ct_nrz_tmp,den_ct_nrz_tmp]=d2cm(num3,den3,1)
% define variables as symbols to be sovled
k1=sym('k1','positive');
k2=sym('k2','positive');
k3=sym('k3','positive');
k4=sym('k4','positive');
k5=sym('k5','positive');
g1=sym('g1','positive');
g2=sym('g2','positive');
g3=sym('g3','positive');
g4=sym('g4','positive');
g5=sym('g5','positive');
gz1=sym('gz1','positive');
gz2=sym('gz2','positive');
[k1 k2 k3 k4 k5 g1 g2 g3 g4 g5 gz1
gz2]=solve('k2=2','k4=1','gz1=1','gz2=0.1','g5=1',...
'k1*g1=num_ct_nrz_tmp(2)','k1*k2*g2=num_ct_nrz_tmp(3)',...
'k1*k2*k3*g1*gz1+k1*k4*k5*g1*gz2+k1*k2*k3*g3=num_ct_nrz_tmp(4)',...
'k1*k2*k4*k5*g2*gz2+k1*k2*k3*k4*g4=num_ct_nrz_tmp(5)',...
'k1*k2*k3*k4*k5*g5+k1*k2*k3*k4*k5*g1*gz1*gz2+k1*k2*k3*k4*k5*g3*gz2=
num_ct_nrz_tmp(6)',...
'k2*k3*gz1+k4*k5*gz2=den_ct_nrz_tmp(3)','k2*k3*k4*k5*gz1*gz2=den_ct
_nrz_tmp(5)',...
'k1','k2','k3','k4','k5','g1','g2','g3','g4','g5','gz1','gz2');
k_coeff=[eval(k1),eval(k2),eval(k3),eval(k4),eval(k5),eval(g1),eval
(g2),eval(g3),eval(g4),eval(g5),eval(gz1),eval(gz2)];