50 MHz to 2200 MHz Quadrature Modulator
with Integrated Detector and VVA
ADL5386
In addition, the ADL5386 incorporates a standalone
logarithmic power detector, as well as a voltage variable
attenuator (VVA). The attenuator has its own separate input and
output pins for easy cascading with filters and buffer amplifiers.
The wide dynamic range of the power detector and VVA provides
flexibility in the choice of the signal monitoring point in the
transmitter system.
FEATURES
Output frequency range: 50 MHz to 2200 MHz
1 dB output compression: 11 dBm @ 350 MHz
Noise floor: −160 dBm/Hz @ 350 MHz
Sideband suppression: −46 dBc @ 350 MHz
Carrier feedthrough: −38 dBm @ 350 MHz
30 dB of linear AGC dynamic range @ 350 MHz
Single supply: 4.75 V to 5.5 V
40-lead, Pb-free LFCSP_VQ with exposed paddle
The wide baseband input bandwidth of 700 MHz allows for
either baseband drive or a drive from a complex IF signal.
Typical applications are in IF or direct-to-RF radio-link
transmitters, cable modem termination systems, broadband
wireless access systems, and cellular infrastructure equipment.
APPLICATIONS
Radio-link infrastructures
Cable modem termination systems
Wireless/cellular infrastructure systems
Wireless local loops
WiMAX/broadband wireless access systems
The ADL5386 takes signals from two differential baseband inputs
and modulates them onto two carriers in quadrature with each
other. The two internal carriers are derived from a single-ended,
external local oscillator (LO) input signal at twice the frequency
as the desired output. The output amplifier is designed to drive
a 50 Ω load.
GENERAL DESCRIPTION
The ADL5386 consists of two die, one fabricated using the
Analog Devices, Inc., advanced SiGe bipolar process, and the other
using an external GaAs process. The ADL5386 is packaged in a
40-lead, Pb-free LFCSP_VQ with an exposed paddle. Performance
is specified over the −40°C to +85°C range. A Pb-free evaluation
board is also available.
The ADL5386 is a quadrature modulator with unmatched
integration levels for low intermediate frequency (IF) and radio
frequency (RF) transmitters within broadband wireless access
systems, microwave radio links, cable modem termination
systems, and cellular infrastructure equipment. The ADL5386
operates over a frequency range of 50 MHz to 2200 MHz. Its
excellent phase accuracy and amplitude balance supports high data
rate, complex modulation for next-generation communication
infrastructure equipment.
FUNCTIONAL BLOCK DIAGRAM
VPOS
38 37 36 35
IBBP
25
IBBN
26
LOIP
LOIN
33
34
23 22
NC
MODOUT ATTI
ENBL
21
24
10
12
9
IQ MOD
BIAS
15dB
QUADRATURE
PHASE
SPLITTER
ADL5386
QBBN
29
QBBP
30
I
LOG
DETECTOR
TEMPERATURE
SENSOR
8
TEMP
V
I
1
2
INLO INHI
39
5
V
11 13 15 16 18 19 27 28 31 32 40
TADJ
COMM
17
ATTCM
14
ATTCM
20
ATTO
6
VREF
7
VDET/VCTL
4
CLPF
3
VSET
07664-001
VPOS
Figure 1.
Rev. 0
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.461.3113
©2009 Analog Devices, Inc. All rights reserved.
ADL5386
TABLE OF CONTENTS
Features .............................................................................................. 1 Open-Loop Power Control Mode ............................................ 21 Applications ....................................................................................... 1 Power Supply and Grounding .................................................. 22 General Description ......................................................................... 1 Device Enable and Disable ........................................................ 22 Functional Block Diagram .............................................................. 1 Baseband Inputs ......................................................................... 22 Revision History ............................................................................... 2 LO Input ...................................................................................... 22 Specifications..................................................................................... 3 AGC Mode .................................................................................. 22 Typical Input and Output Impedances ...................................... 8 Setting the TADJ Resistor.......................................................... 24 Absolute Maximum Ratings............................................................ 9 Using the Detector in Standalone Measurement Mode ........ 25 ESD Caution .................................................................................. 9 DAC Modulator Interfacing ..................................................... 25 Pin Configuration and Function Descriptions ........................... 10 Spectral Products from Harmonic Mixing ............................. 27 Typical Performance Characteristics ........................................... 12 LO Generation Using PLLs ....................................................... 27 Modulator .................................................................................... 12 Transmit DAC Options ............................................................. 28 Voltage Variable Attentuator ..................................................... 16 Modulator/Demodulator Options ........................................... 28 Detector ....................................................................................... 17 Evaluation Board ............................................................................ 29 Closed-Loop AGC Mode........................................................... 18 Characterization Setup .................................................................. 31 Circuit Description ......................................................................... 19 SSB Setup ..................................................................................... 31 Overview...................................................................................... 19 Detector Setup ............................................................................ 31 Quadrature Modulator Section ................................................ 19 VVA S-Paramters Setup............................................................. 32 Logarithmic Detector................................................................. 20 VVA Intermodulation Test Setup ............................................. 32 Voltage Variable Attenuator (VVA) ......................................... 20 Outline Dimensions ....................................................................... 33 Basic Connections .......................................................................... 21 Ordering Guide .......................................................................... 33 REVISION HISTORY
1/09—Revision 0: Initial Version
Rev. 0 | Page 2 of 36
ADL5386
SPECIFICATIONS
Unless otherwise noted, VS = 5 V, TA = 25°C, LO = −7 dBm, I/Q inputs = 1.4 V p-p differential sine waves in quadrature on a 500 mV dc
bias, baseband frequency = 1 MHz, LO source and RF output load impedances are 50 Ω.
Table 1.
Parameter
MODULATOR DYNAMIC CHARACTERISTICS
Operating Frequency Range
External LO Frequency Range
Output Frequency = 50 MHz
Output Power
Modulator Voltage Gain
Output P1dB
Output Return Loss
Carrier Leakage
Sideband Suppression
Quadrature Error
I/Q Amplitude Balance
Second Harmonic
Third Harmonic
Output IP2
Output IP3
Noise Floor
Output Frequency = 140 MHz
Output Power
Modulator Voltage Gain
Output P1dB
Output Return Loss
Carrier Leakage
Sideband Suppression
Quadrature Error
I/Q Amplitude Balance
Second Harmonic
Third Harmonic
Output IP2
Output IP3
Noise Floor
Output Frequency = 350 MHz
Output Power
Modulator Voltage Gain
Output P1dB
Output Return Loss
Carrier Leakage
Conditions
Min
External LO frequency is twice output frequency
50
100
Single (lower) sideband output
Unadjusted (nominal drive level)
At 85°C after optimization at 25°C
At −40°C after optimization at +25°C
Unadjusted (nominal drive level)
At 85°C after optimization at 25°C
At −40°C after optimization at +25°C
(fLO − (2 × fBB)), POUT = 5 dBm
(fLO + (3 × fBB)), POUT = 5 dBm
F1 = 3.5 MHz, F2 = 4.5 MHz, POUT = −3 dBm per tone
F1 = 3.5 MHz, F2 = 4.5 MHz, POUT = −3 dBm per tone
20 MHz offset from LO, all BB inputs at a bias of 500 mV
Single (lower) sideband output
Unadjusted (nominal drive level)
At 85°C after optimization at 25°C
At −40°C after optimization at +25°C
Unadjusted (nominal drive level)
At 85°C after optimization at 25°C
At −40°C after optimization at +25°C
(fLO − (2 × fBB)), POUT = 5 dBm
(fLO + (3 × fBB)), POUT = 5 dBm
F1 = 3.5 MHz, F2 = 4.5 MHz, POUT = −3 dBm per tone
F1 = 3.5 MHz, F2 = 4.5 MHz, POUT = −3 dBm per tone
20 MHz offset from LO, all BB inputs at a bias of 500 mV
Single (lower) sideband output
Unadjusted (nominal drive level)
At 85°C after optimization at 25°C
At −40°C after optimization at +25°C
Rev. 0 | Page 3 of 36
4
Typ
Max
Unit
2200
4400
MHz
MHz
5.6
−1.3
10.8
−21
−43
−63
−63
−48
−60
−60
−0.2
0.05
−80
−58
76
26
−159
dBm
dB
dBm
dB
dBm
dBm
dBm
dBc
dBc
dBc
Degrees
dB
dBc
dBc
dBm
dBm
dBm/Hz
5.7
−1.2
11.1
−21
−42
−62
−62
−57
−60
−60
−0.2
0.05
−79
−56
75
25
−160
dBm
dB
dBm
dB
dBm
dBm
dBm
dBc
dBc
dBc
Degrees
dB
dBc
dBc
dBm
dBm
dBm/Hz
5.5
−1.4
11.1
−19
−38
−58
−58
7
dBm
dB
dBm
dB
dBm
dBm
dBm
ADL5386
Parameter
Sideband Suppression
Quadrature Error
I/Q Amplitude Balance
Second Harmonic
Third Harmonic
Output IP2
Output IP3
Noise Floor
Output Frequency = 860 MHz
Output Power
Modulator Voltage Gain
Output P1dB
Output Return Loss
Carrier Leakage
Sideband Suppression
Quadrature Error
I/Q Amplitude Balance
Second Harmonic
Third Harmonic
Output IP2
Output IP3
Noise Floor
Output Frequency = 1450 MHz
Output Power
Modulator Voltage Gain
Output P1dB
Output Return Loss
Carrier Leakage
Sideband Suppression
Quadrature Error
I/Q Amplitude Balance
Second Harmonic
Third Harmonic
Output IP2
Output IP3
Noise Floor
Conditions
Unadjusted (nominal drive level)
At 85°C after optimization at 25°C
At −40°C after optimization at +25°C
Min
Typ
−46
−57
−57
−0.5
0.05
−76
−53
74
25
−160
−156
Max
Unit
dBc
dBc
dBc
Degrees
dB
dBc
dBc
dBm
dBm
dBm/Hz
dBm/Hz
3.8
5.3
−1.6
11.4
−15
−37
−56
−56
−39
−55
−55
−0.9
0.05
−72
−49
73
25
−160
−157
6.8
dBm
dB
dBm
dB
dBm
dBm
dBm
dBc
dBc
dBc
Degrees
dB
dBc
dBc
dBm
dBm
dBm/Hz
dBm/Hz
(fLO − (2 × fBB)), POUT = 5 dBm
(fLO + (3 × fBB)), POUT = 5 dBm
F1 = 3.5 MHz, F2 = 4.5 MHz, POUT = −3 dBm per tone
F1 = 3.5 MHz, F2 = 4.5 MHz, POUT = −3 dBm per tone
20 MHz offset from LO, all BB inputs at a bias of 500 mV
20 MHz offset from LO, output power = −5 dBm
Single (lower) sideband output
Unadjusted (nominal drive level)
At 85°C after optimization at 25°C
At −40°C after optimization at +25°C
Unadjusted (nominal drive level)
At 85°C after optimization at 25°C
At −40°C after optimization at +25°C
(fLO − (2 × fBB)), POUT = 5 dBm
(fLO + (3 × fBB)), POUT = 5 dBm
F1 = 3.5 MHz, F2 = 4.5 MHz, POUT = −3 dBm per tone
F1 = 3.5 MHz, F2 = 4.5 MHz, POUT = −3 dBm per tone
20 MHz offset from LO, all BB inputs at a bias of 500 mV
20 MHz offset from LO, output power = −5 dBm
Single (lower) sideband output
Unadjusted (nominal drive level)
At 85°C after optimization at 25°C
At −40°C after optimization at +25°C
Unadjusted (nominal drive level)
At 85°C after optimization at 25°C
At −40°C after optimization at +25°C
(fLO − (2 × fBB)), POUT = 5 dBm
(fLO + (3 × fBB)), POUT = 5 dBm
F1 = 3.5 MHz, F2 = 4.5 MHz, POUT = −3 dBm per tone
F1 = 3.5 MHz, F2 = 4.5 MHz, POUT = −3 dBm per tone
20 MHz offset from LO, all BB inputs at a bias of 500 mV
Rev. 0 | Page 4 of 36
4.3
−2.6
10.6
−15
−35
−50
−50
−43
−45
−45
−0.2
0.03
−67
−45
63
25
−160
dBm
dB
dBm
dB
dBm
dBm
dBm
dBc
dBc
dBc
Degrees
dB
dBc
dBc
dBm
dBm
dBm/Hz
ADL5386
Parameter
Output Frequency = 1900 MHz
Output Power
Modulator Voltage Gain
Output P1dB
Output Return Loss
Carrier Leakage
Sideband Suppression
Quadrature Error
I/Q Amplitude Balance
Second Harmonic
Third Harmonic
Output IP2
Output IP3
Noise Floor
Output Frequency = 2150 MHz
Output Power
Modulator Voltage Gain
Output P1dB
Output Return Loss
Carrier Leakage
Sideband Suppression
Quadrature Error
I/Q Amplitude Balance
Second Harmonic
Third Harmonic
Output IP2
Output IP3
Noise Floor
LO Inputs
LO Drive Level
Input Impedance
Input Return Loss
Baseband Inputs
I and Q Input Bias Level
Input Bias Current
Bandwidth (0.1 dB)
Bandwidth (3 dB)
Conditions
Min
Single (lower) sideband output
Unadjusted (nominal drive level)
At 85°C after optimization at 25°C
At −40°C after optimization at +25°C
Unadjusted (nominal drive level)
At 85°C after optimization at 25°C
At −40°C after optimization at +25°C
(fLO − (2 × fBB)), POUT = 5 dBm
(fLO + (3 × fBB)), POUT = 5 dBm
F1 = 3.5 MHz, F2 = 4.5 MHz, POUT = −3 dBm per tone
F1 = 3.5 MHz, F2 = 4.5 MHz, POUT = −3 dBm per tone
20 MHz offset from LO, all BB inputs at a bias of 500 mV
20 MHz offset from LO, output power = −5 dBm
Single (lower) sideband output
Unadjusted (nominal drive level)
At 85°C after optimization at 25°C
At −40°C after optimization at +25°C
Unadjusted (nominal drive level)
At 85°C after optimization at 25°C
At −40°C after optimization at +25°C
(fLO − (2 × fBB)), POUT = 5 dBm
(fLO + (3 × fBB)), POUT = 5 dBm
F1 = 3.5 MHz, F2 = 4.5 MHz, POUT = −3 dBm per tone
F1 = 3.5 MHz, F2 = 4.5 MHz, POUT = −3 dBm per tone
20 MHz offset from LO, all BB inputs at a bias of 500 mV
20 MHz offset from LO, output power = −5 dBm
Pin LOIP and Pin LOIN
Characterization performed at typical level
Characterization performed at typical level (<140 MHz)
350 MHz, LOIN ac-coupled to ground
Pin IBBP, Pin IBBN, Pin QBBP, Pin QBBN
fLO = 2 × 900 MHz, POUT ≈ −4 dBm
fLO = 2 × 900 MHz, POUT ≈ −4 dBm
Rev. 0 | Page 5 of 36
−13
−7
Typ
Max
Unit
3.2
−3.7
9.2
−13
−35
−53
−53
−30
−45
−45
−3
0.02
−59
−45
55
23
−160
−156
dBm
dB
dBm
dBm
dBm
dBm
dBm
dBc
dBc
dBc
Degrees
dB
dBc
dBc
dBm
dBm
dBm/Hz
dBm/Hz
2.5
−4.4
8.4
−11
−35
−48
−46
−34
−45
−45
−1.2
0.03
−56
−48
53
21
−160
−155
dBm
dB
dBm
dB
dBm
dBm
dBm
dBc
dBc
dBc
Degrees
dB
dBc
dBc
dBm
dBm
dBm/Hz
dBm/Hz
−7
−7
50
−7
500
−60
50
700
+2
+2
dBm
dBm
Ω
dB
mV
μA
MHz
MHz
ADL5386
Parameter
VOLTAGE VARIABLE ATTENUATOR
Output Frequency = 50 MHz
Insertion Loss
Attenuation Range
Return Loss
Input IP3
Output Frequency = 140 MHz
Insertion Loss
Attenuation Range
Return Loss
Input IP3
Output Frequency = 350 MHz
Insertion Loss
Attenuation Range
Return Loss
Input IP3
Output Frequency = 860 MHz
Insertion Loss
Attenuation Range
Return Loss
Input IP3
Output Frequency = 1900 MHz
Insertion Loss
Attenuation Range
Return Loss
Input IP3
Output Frequency = 2150 MHz
Insertion Loss
Attenuation Range
Return Loss
Input IP3
SWITCHING CHARACTERISTICS
VCTL Response Time
LOG DETECTOR
f = 50 MHz
±1 dB Dynamic Range
Slope 1
Intercept1
VDET or VSET Voltage
Conditions
Pin VCTL, Pin ATTI, and Pin ATTO, open-loop mode,
attenuation control applied to VCTL
Minimum attenuation, VVCTL = 2 V
Attenuation at VVCTL = 2 V − Attenuation at VVCTL = 0 V
Minimum attenuation, VVCTL = 2 V, Δf = 1 MHz,
input power = −3 dBm per tone
Minimum attenuation, VVCTL = 2 V
Attenuation at VVCTL = 2 V − Attenuation at VVCTL = 0 V
Minimum attenuation, VVCTL = 2 V, Δf = 1 MHz,
input power = −3 dBm per tone
Minimum attenuation, VVCTL = 2 V
Attenuation at VVCTL = 2 V − Attenuation at VVCTL = 0 V
Minimum attenuation, VVCTL = 2 V, Δf = 1 MHz,
input power = −3 dBm per tone
Minimum attenuation, VVCTL = 2 V
Attenuation at VVCTL = 2 V − Attenuation at VVCTL = 0 V
Minimum attenuation, VVCTL = 2 V, Δf = 1 MHz,
input power = −3 dBm per tone
Minimum attenuation, VVCTL = 2 V
Attenuation at VVCTL = 2 V − Attenuation at VVCTL = 0 V
Minimum attenuation, VVCTL = 2 V, Δf = 1 MHz,
input power = −3 dBm per tone
Minimum attenuation, VVCTL = 2 V
Attenuation at VVCTL = 2 V − Attenuation at VVCTL = 0 V
Minimum attenuation, VVCTL = 2 V, Δf = 1 MHz,
input power = −3 dBm per tone
ATTCM (Pin 14 and Pin 17) = 1000 pF
Frequency = 350 MHz, VVCTL = 2 V to 0 V; measured from
50 % of VVCTL to10% of RF envelope
Frequency = 350 MHz, VVCTL = 0 V to 2 V; measured from
50 % of VVCTL to 90% of RF envelope
In measurement mode, VDET/VCTL is shorted to VSET;
in controller mode, the setpoint voltage is applied to VSET;
the CW input signal is applied at INHI
RTADJ = 22.1 kΩ
TA = 25°C
PIN = −10 dBm
PIN = −30 dBm
Rev. 0 | Page 6 of 36
Min
Typ
Max
Unit
1.7
37.8
17
36
dB
dB
dB
dBm
1.9
37
17
36
dB
dB
dB
dBm
2.2
26.2
17
35
dB
dB
dB
dBm
2.5
21
14
35
dB
dB
dB
dBm
3
19
13
36
dB
dB
dB
dBm
3.3
17
13
35
dB
dB
dB
dBm
125
ns
15
ns
28
−21
18.2
0.59
1.01
dB
mV/dB
dBm
V
V
ADL5386
Parameter
f = 140 GHz
±1 dB Dynamic Range
Slope1
Intercept1
VDET or VSET Voltage
f = 350 MHz
±1 dB Dynamic Range
Slope1
Intercept1
VDET or VSET Voltage
f = 860 MHz
±1 dB Dynamic Range
Slope1
Intercept1
VDET or VSET Voltage
f = 1900 MHz
±1 dB Dynamic Range
Slope1
Intercept1
VDET or VSET Voltage
f = 2150 MHz
±1 dB Dynamic Range
Slope1
Intercept1
VDET or VSET Voltage
LOG DETECTOR OUTPUT INTERFACE
VDET Voltage Swing
Small Signal Bandwidth
Output Noise
Fall Time
Rise Time
Video Bandwidth
VSET Incremental Input Resistance
VSET Input Bias Current
TADJ INTERFACE
Input Resistance
Disable Threshold Voltage
TEMPERATURE SENSOR OUTPUT
Output Voltage
Temperature Slope
Output Impedance
Conditions
RTADJ = 22.1 kΩ
TA = 25°C
Min
PIN = −10 dBm
PIN = −30 dBm
RTADJ = 22.1 kΩ
TA = 25°C
PIN = −10 dBm
PIN = −30 dBm
RTADJ = 22.1 kΩ
TA = 25°C
PIN = −10 dBm
PIN = −30 dBm
RTADJ = 22.1 kΩ
TA = 25°C
PIN = −10 dBm
PIN = −30 dBm
RTADJ = 22.1 kΩ
TA = 25°C
PIN = −10 dBm
PIN = −30 dBm
VDET
VVSET = 0 V, INHI = open, controller mode
VVSET = 2 V, INHI = open, controller mode
Simulated, INHI = −10 dBm, from CLPF to VOUT
INHI = 2.2 GHz, –10 dBm, fNOISE = 100 kHz, CCLPF = open
Input level = no signal to −10 dBm, 90% to 10%, CCLPF = 8 pF
Input level = no signal to −10 dBm, 90% to 10%, CCLPF = 0.1 μF
Input level = −10 dBm to no signal, 10% to 90%, CCLPF = 8 pF
Input level = −10 dBm to no signal, 10% to 90%, CCLPF = 0.1 μF
POUT = 0 dBm, AGC mode, VVSET = 0.9 V to 1 V
POUT = 0 dBm, AGC mode, VVSET = 1 V
TADJ
TADJ = 0.9 V, sourcing 50 μA
TADJ = open
TEMP
TA = 27.15°C, 300K, RL = 1 MΩ (after full warmup)
−40°C ≤ TA ≤ +85°C, RL = 1 MΩ
Rev. 0 | Page 7 of 36
Typ
Max
Unit
28
−21.1
17.8
0.59
1.01
dB
mV/dB
dBm
V
V
26
−21.3
17.1
0.58
1.0
dB
mV/dB
dBm
V
V
25
−21.6
16.2
0.57
1.00
dB
mV/dB
dBm
V
V
26
−22.7
13.5
0.54
0.99
dB
mV/dB
dBm
V
V
24
−23.2
12.6
0.53
0.99
dB
mV/dB
dBm
V
V
2
10
>100
73
42
178
29
174
15
33,000
25
V
mV
MHz
nV/√Hz
ns
μs
ns
μs
MHz
dV/dI
μA
13
VVPOS − 0.4
kΩ
V
1.45
4.6
1
V
mV/°C
kΩ
ADL5386
Parameter
ENABLE INPUT
Input Bias Current
Conditions
ENBL
ENBL = 5 V
ENBL = 0 V
ENBL High Level (Logic 1)
ENBL Low Level (Logic 0)
POWER SUPPLIES
Voltage
Supply Current
1
Min
Typ
Max
Unit
0.4
μA
μA
V
V
0.5
−0.7
1.5
Pin VPOS
4.75
ENBL = high
In sleep mode, ENBL = low and TADJ = high
In detector disabled mode, ENBL = high and TADJ = high
230
2.2
215
5.5
245
V
mA
mA
mA
Slope and intercept are determined by calculating the best-fit line between the power levels of −33 dBm and −10 dBm at the specified input frequency.
TYPICAL INPUT AND OUTPUT IMPEDANCES
Unless otherwise noted, VS = 5 V, TA = 25°C. All impedances are normalized to 50 Ω. The effects of the test fixture are de-embedded up to
the pins of the device.
Table 2.
Frequency (MHz)
50
140
350
860
1450
1900
2150
LO Input Impedance at 2× Frequency
1.393 − j0.027
1.406 + j0.013
1.441 + j0.039
1.66 + j0.077
2.261 − j0.304
1.436 − j1.898
0.517 − j1.446
Modulator Output Impedance
0.847 − j0.016
0.839 + j0.019
0.82 + j0.065
0.764 + j0.166
0.799 + j0.231
0.856 + j0.371
0.862 + j0.51
Rev. 0 | Page 8 of 36
Detector Input Impedance
28.463 − j11.386
15.159 − j15.234
4.661 − j10.6
1.158 − j4.58
0.567 − j2.545
0.375 − j1.866
0.308 − j1.652
ADL5386
ABSOLUTE MAXIMUM RATINGS
Table 3.
Parameter
Supply Voltage, VPOS
IBBP, IBBN, QBBP, QBBN Range
LOIP and LOIN
Internal Power Dissipation
θJA (Exposed Paddle Soldered Down)
Maximum Junction Temperature
Operating Temperature Range
Storage Temperature Range
Rating
5.5 V
0 V to 2.0 V
13 dBm
1.4 W
38°C/W
150°C
−40°C to +85°C
−65°C to +150°C
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
ESD CAUTION
Rev. 0 | Page 9 of 36
ADL5386
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
VPOS
VPOS
23 22
38 37 36 35
21
ENBL
MODOUT ATTI
24
10
NC
12
9
IBBP 25
IBBN 26
IQ MOD
BIAS
LOIP 33
17 ATTCM
LOIN 34
14 ATTCM
15dB
QUADRATURE
PHASE
SPLITTER
20 ATTO
ADL5386
6 VREF
QBBN 29
I
QBBP 30
4 CLPF
I
1
2
INLO INHI
39
5
V
3 VSET
11 13 15 16 18 19 27 28 31 32 40
TADJ
COMM
NOTES
1. NC = NO CONNECT.
2. CONNECT THE EXPOSED PAD TO GROUND VIA A LOW IMPEDANCE PATH.
07664-002
8
7 VDET/VCTL
LOG
DETECTOR
TEMPERATURE
SENSOR
TEMP
V
Figure 2. Pin Configuration
Table 4. Pin Function Descriptions
Pin No.
1
2
Mnemonic
INLO
INHI
3
4
VSET
CLPF
5, 11, 13, 15,
16, 18, 19, 27,
28, 31, 32, 40
6
COMM
7
VDET/VCTL
8
TEMP
9
10
NC
MODOUT
12, 20
ATTI, ATTO
14, 17
21 to 23,
35 to 38
ATTCM
VPOS
VREF
Description
Detector Common. This pin should be ac-coupled to ground.
Detector Input. When operating in AGC mode, a portion of the signal at the output of the VVA (or at the
output of a subsequent stage) is coupled back to this input. The signal should be ac-coupled into INHI. To provide
a 50 Ω match at INHI, a 50 Ω resistor should be connected between INHI and ground (with the ac-coupling
capacitor placed between the resistor and the INHI pin).
Setpoint Input. Setpoint input for controller mode or feedback input for measurement mode.
AGC Loop Filter Capacitor. The ground-referenced capacitor that is connected to this pin sets the loop bandwidth
of the AGC circuit.
Device Common. Connect these pins to the same low impedance ground plane.
Attenuator Control Voltage Reference. In AGC mode, this pin should be left open. In open-loop mode, when
the VVA is being controlled externally, a 2 V reference voltage should be applied to this pin.
Detector Output/VVA Control Voltage Input. When the VVA is being controlled externally (open-loop mode),
the attenuation is controlled by the external voltage applied to this pin. The VVA control range is from 0 V
(maximum attenuation) to 2 V (minimum attenuation). In this mode, VREF (Pin 6) should be tied to approximately
2 V. When the VVA is being operated in AGC mode, this pin is left open with the voltage on the pin representing the
AGC drive voltage to the VVA. If the VVA is not being used, the AGC log amp can be used as a standalone detector
by connecting this pin to VSET. In this mode, the log amp output voltage is available at this pin.
Temperature Sensor Output. This pin provides a standalone temperature sensor output voltage. At room
temperature, the nominal output voltage is equal to 1.45 V. The slope of the output voltage is equal to 4.6 mV/°C.
No Connect. Do not connect this pin.
RF Output of IQ Modulator. Single-ended, 50 Ω internally biased RF output. MODOUT is generally
ac-coupled to the input of the VVA (either ATTI or ATTO).
VVA RF Input/Output. ATTI is normally ac-coupled to MODOUT. However, because the VVA is completely reversible,
MODOUT can also drive ATTO with ATTI operating as the VVA output.
VVA Input/Output Common. These pins should be ac-coupled to ground.
Power Supply. Positive supply voltage pins. All pins should be connected to the same supply (VS). To ensure
adequate external bypassing, connect a 0.1 μF capacitor between each pin and ground.
Rev. 0 | Page 10 of 36
ADL5386
Pin No.
24
Mnemonic
ENBL
25, 26, 29, 30
IBBP, IBBN,
QBBN, QBBP
33
LOIP
34
39
LOIN
TADJ
41 (EPAD)
Exposed
Pad (EPAD)
Description
IQ Modulator Enable. The IQ modulator is enabled by connecting this pin to VPOS and is disabled by connecting
ENBL to ground.
Differential In-Phase and Quadrature Baseband Inputs. These high impedance inputs should be dc-biased to 0.5 V.
Nominal characterized ac signal swing is 700 mV p-p on each pin, resulting in a differential drive of
1.4 V p-p on each input pair. These inputs are not self-biased and have to be externally biased.
Local Oscillator Input. The local oscillator signal, at two times the output frequency, should be ac-coupled into
this pin.
Local Oscillator Common. This pin should be ac-coupled to ground.
Temperature Compensation Adjustment Pin and Detector Enable/Disable. This pin is primarily used to
provide temperature compensation to the on-chip log amp based AGC circuit. The correct compensation
current is set by connecting a ground-referenced resistor to this pin. A value of 22.1 kΩ is recommended
for the frequencies over which the ADL5386 is specified. The TADJ pin can also be used to power down the
detector section of the ADL5386 by connecting it to VPOS. The detector must be disabled when the
modulator/VVA is operating in open loop mode.
Connect the exposed pad to ground via a low impedance path.
Rev. 0 | Page 11 of 36
ADL5386
TYPICAL PERFORMANCE CHARACTERISTICS
MODULATOR
12
11
10
9
8
SSB OUTPUT POWER
6
5
4
3
2
1
50
550
1050
1550
2050
OUTPUT FREQUENCY (MHz)
OUTPUT IP2 AND IP3 (dBm)
11
10
9
SSB OUTPUT POWER
7
6
5
4
3
2
1
50
550
–40
–50
0
–60
–5
–70
–80
0.1
1050
1550
50
40
OIP3
30
20
0
50
550
1050
1550
2050
OUTPUT FREQUENCY (MHz)
Figure 7. Output IP2 and IP3 vs. Output Frequency and Temperature
2
THIRD-ORDER
DISTORTION
5
SIDEBAND SUPPRESSION
–50
0
–60
–5
–70
–10
SECOND-ORDER
DISTORTION
1.0
DIFFERENTIAL BASEBAND VOLTAGE (V p-p)
–15
10
SSB OUTPUT POWER (dBm)
10
SSB OUTPUT POWER
Figure 5. Second- and Third-Order Distortion, Carrier Feedthrough, Sideband
Suppression, and SSB Output Power vs. Differential Baseband Voltage,
Output Frequency = 350 MHz
1
0
–1
–2
–3
–4
–5
–6
–7
–8
07664-008
BASEBAND FREQUENCY RESPONSE (dB)
15
–20
–40 CARRIER FEEDTHROUGH
+85°C
+25°C
–40°C
OIP2
60
2050
07664-005
SECOND-ORDER DISTORTION (dBc),
THIRD-ORDER DISTORTION (dBc), CARRIER
FEEDTHROUGH (dBm), SIDEBAND SUPPRESSION (dBc)
–15
10
1.0
DIFFERENTIAL BASEBAND VOLTAGE (V p-p)
10
Figure 4. Single Sideband (SSB) Output Power (POUT), Output P 1 dB vs.
Output Frequency and Temperature
–80
0.1
–10
SECOND-ORDER
DISTORTION
70
OUTPUT FREQUENCY (MHz)
–30
5
THIRD-ORDER
DISTORTION
SIDEBAND SUPPRESSION
80
07664-004
SSB OUTPUT POWER, OUTPUT P1dB (dBm)
+85°C
+25°C
–40°C
12
8
10
CARRIER FEEDTHROUGH
90
OUTPUT P1dB
13
–30
Figure 6. Second- and Third-Order Distortion, Carrier Feedthrough, Sideband
Suppression, and SSB Output Power vs. Differential Baseband Voltage,
Output Frequency = 860 MHz
Figure 3. Single Sideband (SSB) Output Power (POUT), Output P1dB vs.
Output Frequency and Power Supply
14
15
SSB OUTPUT POWER
07664-007
7
–20
SSB OUTPUT POWER (dBm)
VS = 5.5V
VS = 5.0V
VS = 4.75V
07664-006
OUTPUT P1dB
13
07664-003
SSB OUTPUT POWER, OUTPUT P1dB (dBm)
14
SECOND-ORDER DISTORTION (dBc),
THIRD-ORDER DISTORTION (dBc), CARRIER
FEEDTHROUGH (dBm), SIDEBAND SUPPRESSION (dBc)
Unless otherwise noted, VS = 5 V, TA = 25°C, LO = −7 dBm, I/Q inputs = 1.4 V p-p differential sine waves in quadrature on a 500 mV dc bias, baseband
frequency = 1 MHz, LO source and RF output load impedances are 50 Ω.
–9
–10
1
10
100
BB FREQUENCY (MHz)
1000
Figure 8. Baseband Frequency Response Normalized to Response for 1 MHz
BB Signal, Carrier Frequency = 500 MHz
Rev. 0 | Page 12 of 36
ADL5386
0
+85°C
+25°C
–40°C
SIDEBAND SUPPRESSION (dBc)
–40
–50
–60
–70
550
1050
1550
–30
–40
–50
–60
–70
–80
–90
50
2050
550
Figure 9. Carrier Feedthrough Distribution vs. Output Frequency and
Temperature
–20
–30
–40
–50
–60
–70
1050
1550
–30
–40
–50
–60
–70
07664-013
–90
50
2050
550
1050
1550
2050
OUTPUT FREQUENCY (MHz)
OUTPUT FREQUENCY (MHz)
Figure 10. Carrier Feedthrough Distribution at Temperature Extremes,
After Nulling to < −65 dBm at TA = 25°C vs. Output Frequency
Figure 13. Sideband Suppression Distribution at Temperature Extremes,
After Sideband Suppression Nulled to < −50 dBc at TA = 25°C vs.
Output Frequency
0.010
0.20
I OFFSET
Q OFFSET
0.008
0.15
IQ AMPLITUDE OFFSET (dB)
0.006
0.004
0.002
0
–0.002
–0.004
–0.006
–0.010
550
1050
1550
OUTPUT FREQUENCY (MHz)
2050
07664-011
–0.008
50
94
PEAK IQ AMPLITUDE OFFSET
IQ PHASE
Figure 11. Distribution of I Offset and Q Offset Required to Null Carrier
Feedthrough vs. Output Frequency
93
0.10
92
0.05
91
0
90
–0.05
89
–0.10
88
–0.15
87
–0.20
50
550
1050
1550
OUTPUT FREQUENCY (MHz)
2050
86
IQ PHASE (Degrees)
550
–20
–80
07664-010
–80
+85°C
+25°C
–40°C
–10
SIDEBAND SUPPRESSION (dBc)
CARFRIER FEEDTHROUGH (dBm)
2050
0
+85°C
+25°C
–40°C
–10
OFFSET (V)
1550
Figure 12. Sideband Suppression vs. Output Frequency and Temperature
0
–90
50
1050
OUTPUT FREQUENCY (MHz)
OUTPUT FREQUENCY (MHz)
07664-014
–80
50
–20
07664-012
–30
+85°C
+25°C
–40°C
–10
07664-009
CARRIER FEEDTHROUGH (dBm)
–20
Figure 14. Distribution of Peak Q Amplitude to Null Undesired Sideband
(Peak I Amplitude Held Constant at 0.7 V) and Distribution of IQ Phase to
Null Undesired Sideband vs. Output Frequency
Rev. 0 | Page 13 of 36
ADL5386
j1
j2
j0.5
–20
2250MHz
–40
–50
50MHz 100MHz
50MHz
350MHz
–60
–70
–7
–6
–5
–4
–3
–2
–1
0
1
4500MHz
2250MHz
–j0.5
2
–j1
LO AMPLITUDE (dBm)
Figure 15. Carrier Feedthrough Distribution vs. LO Amplitude
at 50 MHz and 350 MHz
Figure 18. Modulator Output Impedance, LO Input Impedance and Detector
Input Impedance (Unterminated) vs. Frequency
–20
0
50MHz
350MHz
–30
–5
–40
RETURN LOSS (dB)
–50
–60
–70
–10
07664-016
–4
–3
–2
–1
0
1
–20
2
0
LO AMPLITUDE (dBm)
Figure 16. Sideband Suppression Distribution vs. LO Amplitude
at 50 MHz and 350 MHz
1.0
1.5
2.0
2.5
3.0
LOIP FREQUENCY (GHz)
3.5
4.0
4.5
Figure 19. LO Port Input Return Loss vs. LOIP Frequency
–20
30
25
NUMBER OF PARTS
–30
–40
–50
–60
20
15
10
–156.0
–156.2
–156.4
–156.6
–156.8
0
100
–157.0
10
BASEBAND FREQUENCY (MHz)
07664-020
5
07664-017
–70
1
0.5
–157.4
–5
–157.6
–6
–157.8
–7
–158.0
–90
07664-019
–15
–80
–158.2
SIDEBAND SUPPRESSION (dBc)
–j2
07664-018
–90
07664-015
–80
SIDEBAND SUPPRESSION (dBc)
50MHz
S11 OF LOIP
S22 OF MOD OUTPUT
S11 OF DETECTOR INPUT
–157.2
CARRIER FEEDTHROUGH (dBm)
–30
OFFSET FROM OUTPUT FREQUENCY (dBm/Hz at 20MHz)
Figure 17. Sideband Suppression vs. Baseband Frequency,
Output Frequency = 350 MHz
Figure 20. 20 MHz Offset Noise Floor Distribution, Output Frequency = 360 MHz,
POUT = −5 dBm, QPSK Carrier, Symbol Rate = 3.84 MSPS
Rev. 0 | Page 14 of 36
ADL5386
35
250
20
15
10
–154.0
–154.2
–154.4
–154.6
–154.8
–155.0
–155.2
–155.4
–155.6
–155.8
–156.0
0
07664-021
5
225
200
POWER SUPPLY CURRENT
WITH MODULATOR ENABLED
AND DETECTOR DISABLED
175
POWER SUPPLY CURRENT
WITH MODULATOR DISABLED
AND DETECTOR ENABLED
150
22
20
18
125
16
100
14
75
OFFSET FROM OUTPUT FREQUENCY (dBm/Hz at 20MHz)
24
–40
25
85
DETECTOR SUPPLY CURRENT (mA)
25
26
VS = 5.5V
VS = 5.0V
VS = 4.75V
12
TEMPERATURE (°C)
Figure 21. 20 MHz Offset Noise Floor Distribution, Output Frequency =
860 MHz, POUT = −5 dBm, 64 QAM Carrier, Symbol Rate = 5 MSPS
Figure 22. Power Supply Current vs. Temperature and Supply Voltage
Rev. 0 | Page 15 of 36
07664-022
MODULATOR SUPPLY CURRENT (mA)
NUMBER OF PARTS
30
ADL5386
VOLTAGE VARIABLE ATTENTUATOR
Unless otherwise noted, VS = 5 V, TA = 25°C.
70
10
INPUT IP3
5
30
0
20
–5
10
–10
RETURN LOSS
–15
–10
–20
–20
–25
–30
–30
–40
–35
–50
–40
–60
–45
0.4
0.6
0.8
1.0
1.2
1.4
1.6
1.8
2.0
VVCTL (V)
10
INPUT IP3
40
0
30
–5
20
ATTENUATION
10
–15
RETURN LOSS
–10
–25
–30
–30
–40
–35
–50
–40
–60
25
80
20
70
0
10
50
INPUT IP3
40
5
30
0
20
–5
10
–10
ATTENUATION
0
–15
RETURN LOSS
–20
–10
–20
–25
–30
–30
–40
–35
–50
–40
–60
0
0.2
0.4
0.6
0.8
1.0
1.2
1.4
1.6
1.8
2.0
–45
VVCTL (V)
0
20
–5
ATTENUATION
–10
RETURN LOSS
–15
–10
–20
–20
–25
–30
–30
–40
–35
–50
–40
–60
–45
0.8
1.0
1.2
1.4
1.6
1.8
VVCTL (V)
–45
20
10
5
0
ATTENUATION
–5
–10
10
RETURN LOSS
0
–15
–20
–10
–25
–20
+85°C
+25°C
–40°C
–30
–60
–30
–35
–40
0
0.2
0.4
0.6
0.8
1.0
1.2
VVCTL (V)
1.4
1.6
1.8
2.0
–45
2.0
25
INPUT IP2
20
15
60
INPUT IP3 AND INPUT IP2 (dBm)
INPUT IP3
30
0.6
2.0
INPUT IP3
20
70
5
0.4
1.8
30
80
40
0.2
1.6
15
40
20
10
0
1.4
50
25
15
0
1.0
1.2
VVCTL (V)
–50
ATTENUATION AND RETURN LOSS (dB)
INPUT IP2
50
10
0.8
25
–40
10
50
INPUT IP3
40
5
0
30
20
–5
ATTENUATION
–10
10
RETURN LOSS
0
–15
–10
–20
–20
–25
–30
–30
+85°C
+25°C
–40°C
–40
–50
07664-025
INPUT IP3 AND INPUT IP2 (dBm)
60
0.6
Figure 27. IIP3, IIP2, Attenuation, and Return Loss vs.
VVCTL Voltage and Temperature at 1900 MHz
80
+85°C
+25°C
–40°C
0.4
INPUT IP2
Figure 24. IIP3, IIP2, Attenuation, and Return Loss vs.
VVCTL Voltage and Temperature at 350 MHz
70
0.2
60
INPUT IP3 AND INPUT IP2 (dBm)
15
ATTENUATION AND RETURN LOSS (dB)
INPUT IP2
07664-024
INPUT IP3 AND INPUT IP2 (dBm)
60
–20
–20
Figure 26. IIP3, IIP2, Attenuation, and Return Loss vs.
VVCTL Voltage and Temperature at 1450 MHz
80
+85°C
+25°C
–40°C
–10
0
Figure 23. IIP3, IIP2, Attenuation, and Return Loss vs.
VVCTL Voltage and Temperature at 140 MHz
70
5
ATTENUATION AND RETURN LOSS (dB)
0.2
15
50
07664-027
0
20
–60
0
0.2
–35
–40
0.4
0.6
0.8
1.0
1.2
1.4
1.6
1.8
2.0
VVCTL (V)
Figure 28. IIP3, IIP2, Attenuation, and Return Loss vs.
VVCTL Voltage and Temperature at 2150 MHz
Figure 25. IIP3, IIP2, Attenuation, and Return Loss vs.
VVCTL Voltage and Temperature at 860 MHz
Rev. 0 | Page 16 of 36
ATTENUATION AND RETURN LOSS (dB)
ATTENUATION
0
INPUT IP2
–45
07664-028
40
60
INPUT IP3 AND INPUT IP2 (dBm)
INPUT IP3 AND INPUT IP2 (dBm)
50
15
INPUT IP2
07664-023
+85°C
+25°C
–40°C
60
25
+85°C
+25°C
–40°C
ATTENUATION AND RETURN LOSS (dB)
80
20
07664-026
25
70
ATTENUATION AND RETURN LOSS (dB)
80
ADL5386
DETECTOR
Unless otherwise noted, VS = 5 V, TA = 25°C.
1.00
1
0.75
0
0.50
–1
0.25
–2
–25
–15
–5
5
1.00
1
0.75
0
0.50
–1
0.25
–2
–3
0
–45
–35
–25
Figure 29. VVDET/VVSET Voltage and Log Conformance vs. Input Amplitude at
350 MHz, RTADJ = 22.1 kΩ
+85°C
+25°C
–40°C
0.50
–1
0.25
–2
–25
–15
–5
5
–3
VVDET /VVSET (V)
0
POWER ERROR (dB)
0.75
3
+85°C
+25°C
–40°C
1.25
2
1.00
1
0.75
0
0.50
–1
0.25
–2
07664-030
VVDET /VVSET (V)
1
–35
–3
1.50
2
1.00
0
–45
5
Figure 31. VVDET/VVSET Voltage and Log Conformance vs. Input
Amplitude at 1450 MHz, RTADJ = 22.1 kΩ
3
1.25
–5
PIN (dBm)
PIN (dBm)
1.50
–15
0
–45
–35
–25
–15
–5
5
–3
PIN (dBm)
PIN (dBm)
Figure 30. VVDET/VVSET Voltage and Log Conformance vs. Input Amplitude at
860 MHz, RTADJ = 22.1 kΩ
Rev. 0 | Page 17 of 36
Figure 32. VVDET/VVSET Voltage and Log Conformance vs. Input
Amplitude at 2150 MHz, RTADJ = 22.1 kΩ
POWER ERROR (dB)
–35
2
07664-032
0
–45
+85°C
+25°C
–40°C
POWER ERROR (dB)
1.25
3
07664-031
2
VVDET /VVSET (V)
VVDET /VVSET (V)
1.50
POWER ERROR (dB)
+85°C
+25°C
–40°C
1.25
3
07664-029
1.50
ADL5386
CLOSED-LOOP AGC MODE
Unless otherwise noted, VS = 5 V, TA = 25°C, LO = −7 dBm, I/Q inputs = 1.4 V p-p differential sine waves in quadrature on a 500 mV dc bias,
baseband frequency = 1 MHz, LO source and RF output load impedances are 50 Ω. For AGC mode characterization setup, refer to Figure 42.
4
+85°C
+25°C
–40°C
0
2
–5
2
–10
1
–10
1
–15
0
–15
0
–20
–1
–20
–1
–25
–2
–25
–2
–30
–3
–30
–3
–35
–4
0.9
1.0
VVSET (V)
1.1
1.2
1.3
1.4
–35
Figure 33. POUT and Error vs. VVSET at 140 MHz
4
5
0
3
0
+85°C
+25°C
–40°C
0.8
0.9
1.0
VVSET (V)
1.1
1.2
1.3
1.4
4
3
+85°C
+25°C
–40°C
–10
1
–10
1
–15
0
–15
0
–20
–1
–20
–1
–25
–2
–25
–2
–30
–3
–30
–3
–4
0.5
0.6
0.7
0.8
0.9
1.0
VSET (V)
1.1
1.2
1.3
POUT (dBm)
ERROR (dB)
–5
07664-034
POUT (dBm)
0.7
2
–35
2
–35
1.4
–4
0.5
Figure 34. POUT and Error vs. VVSET at 350 MHz
0.6
0.7
0.8
0.9
1.0
VVSET (V)
1.1
1.2
1.3
1.4
Figure 37. POUT and Error vs. VVSET at 1900 MHz
5
3
0
2
–5
2
–10
1
–10
1
–15
0
–15
0
–20
–1
–20
–1
–25
–2
–25
–2
–30
–3
–30
–3
+85°C
+25°C
–40°C
–5
–35
–4
0.5
0.6
0.7
0.8
0.9
1.0
VVSET (V)
1.1
1.2
1.3
1.4
POUT (dBm)
0
ERROR (dB)
4
07664-035
5
POUT (dBm)
0.6
Figure 36. POUT and Error vs. VVSET at 1450 MHz
5
–5
ERROR (dB)
–4
0.5
ERROR (dB)
0.8
07664-037
0.7
Figure 35. POUT and Error vs. VVSET at 860 MHz
4
+85°C
+25°C
–40°C
3
–35
–4
0.5
0.6
0.7
0.8
0.9
1.0
VVSET (V)
1.1
1.2
1.3
Figure 38. POUT and Error vs. VVSET at 2150 MHz
Rev. 0 | Page 18 of 36
1.4
ERROR (dB)
0.6
3
07664-038
0.5
POUT (dBm)
–5
ERROR (dB)
3
+85°C
+25°C
–40°C
07664-033
0
POUT (dBm)
5
4
07664-036
5
ADL5386
CIRCUIT DESCRIPTION
VPOS
VPOS
38 37 36 35
23 22
21
NC
MODOUT ATTI
ENBL
24
10
9
12
IBBP 25
IBBN 26
LOIP 33
LOIN 34
IQ MOD
BIAS
15dB
QUADRATURE
PHASE
SPLITTER
ADL5386
17
ATTCM
14
ATTCM
20
ATTO
6
VREF
7
VDET/VCTL
4
CLPF
3
VSET
I
QBBP 30
LOG
DETECTOR
TEMPERATURE
SENSOR
I
8
TEMP
V
1
39
2
INLO INHI
5
V
11 13 15 16 18 19 27 28 31 32 40
TADJ
COMM
07664-039
QBBN 29
Figure 39. Block Diagram
OVERVIEW
V-to-I Converter
The ADL5386 consists of three sections: a quadrature modulator, a
logarithmic detector, and a voltage variable attenuator (VVA).
The modulator section contains the circuitry for the following
functions:
The differential baseband input voltages that are applied to the
baseband input pins are fed to a pair of common-emitter, voltageto-current converters. The output currents then modulate the
two half-frequency LO carriers in the mixer stage.
•
•
•
•
•
Mixers
Local oscillator (LO) interface
Baseband voltage-to-current (V-to-I) converter
Mixers
Differential-to-single-ended (D-to-S) amplifier
Temperature sensor and bias circuit
The ADL5386 has two double-balanced mixers: one for the
in-phase channel (I channel) and one for the quadrature channel
(Q channel). These mixers are based on the Gilbert cell design
of four cross-connected transistors. The output currents from
the two mixers are summed together in the resistor-inductor
loads in the D-to-S amplifier.
The detector section contains the logarithmic detector and
amplifiers interfacing to the VSET input and VDET output.
The variable attenuator section consists of a PI network of
PHEMTs and resistors implemented on a GaAs die separate
from the silicon die where the rest of the circuits reside. A
detailed block diagram of the device is shown in Figure 39.
D-to-S Amplifier
The output D-to-S amplifier consists of two emitter followers
driving a totem-pole output stage. Output impedance is established
by the emitter resistors in the output transistors. The output of
this stage connects to the output (VOUT) pin.
QUADRATURE MODULATOR SECTION
The LO interface generates two LO signals at 90° of phase
difference to drive two mixers in quadrature. Baseband signals
are converted into currents by the V-to-I converters that feed
into the two mixers. The outputs of the mixers are combined in
the differential-to-single-ended amplifier, which provides a 50 Ω
output interface. Reference currents to each section are generated
by the bias circuit. A detailed description of each section follows.
LO Interface
The LO interface consists of a buffer amplifier followed by a
pair of frequency dividers that generate two carriers at half the
input frequency and in quadrature with each other. Each carrier
is then amplified and amplitude-limited to drive the doublebalanced mixers.
Bias Circuits
A band gap based bias circuit provides proportional-to-absolute
temperature as well as temperature stable reference currents for
the different circuits in the modulator section. The ENBL input
controls the operation of this bias circuit. When ENBL is pulled
to a low level, the bias references are turned off, and the whole
modulator section is turned off as a result. A voltage that is
proportional to the absolute temperature of the circuit is also
available at the TEMP pin.
A separator bias circuit provides the reference currents as well
as the reference voltages for the detector and voltage variable
attenuator sections. This bias circuit can also be disabled by
pulling the TADJ pin high, which in turn shuts down the
detector section.
Rev. 0 | Page 19 of 36
ADL5386
LOGARITHMIC DETECTOR
VOLTAGE VARIABLE ATTENUATOR (VVA)
The design of the log detector is similar to that of the AD8317
standalone log detector device, where the log function is
generated by a series of limiting amplifiers and detectors. The
output current from this log detector is compared with that
from a voltage-to-current converter connected to the VSET input.
Any net difference between these two currents is pumped into
an on-chip integrating capacitor that is generally augmented by
additional off-chip capacitance. The voltage on the integrating
capacitor is amplified and produces an output error voltage that
is generally used to adjust the attenuation of the voltage variable
attenuator until the VSET current and the current from the log
detector are balanced.
The VVA is implemented on a GaAs die separate from the
silicon die where the modulator and detector reside. The VVA
is formed by PHEMTs and resistors connected in a PI network
to provide the attenuator function. The gate source bias on the
PHEMTs are controlled by the voltages on the VREF and VDET/
VCTL pins, resulting in different attenuation between ATTI and
ATTO as the voltage at VDET/VCTL is varied. The resistance in
the shunt paths between ATTI and ATTO to ATTCM vary in the
opposite manner as the paths between ATTI and ATTO to
maintain good return loss through different attenuation levels.
Rev. 0 | Page 20 of 36
ADL5386
BASIC CONNECTIONS
Figure 40 shows a plot of POUT vs. the control voltage (applied
to the VDET/VCTL pin) at 350 MHz when the modulator is
driven by 1 V p-p sine and cosine signals on its baseband inputs
and a 2 × LO of 700 MHz.
OPEN-LOOP POWER CONTROL MODE
Figure 41 shows the basic connections for operating the ADL5386
when the voltage variable attenuator (VVA) is driven from an
external voltage source and not from the built-in AGC circuit.
In this mode, the inputs to the RF detector should be both
ac-coupled to ground. The TADJ pin is tied to the supply,
disabling the unused detector and reducing the current
consumption by approximately 15 mA. The IQ modulator
is enabled by pulling the ENBL pin high.
In this mode, the detector cannot be used in any kind of
standalone mode because its output pin (VDET/VCTL) is
used as an input.
5
0
The output of the modulator is ac-coupled to the input of
the VVA (Pin ATTI). The VVA is bidirectional; therefore, the
modulator can also be configured to drive ATTO and to take
the final output at ATTI.
POUT (dBm)
–5
The attenuation of the VVA is controlled by the voltages on
Pin VREF and Pin VDET/VCTL. VREF should be tied to
a low impedance external voltage of 2 V. This voltage can be
conveniently derived from the supply voltage using a pair of
resistors, but this voltage must then be buffered with an op
amp to prevent bias current related voltage drops.
–10
–15
–20
–25
–35
With VREF set to 2 V, a variable voltage between 0 V and 2 V
on VDET/VCTL sets the attenuation. Maximum attenuation is
achieved when VVDET/VVCTL = 0 V, and minimum attenuation is
achieved when VVDET/VVCTL = 2 V.
07664-040
–30
0
0.2
0.4
0.6
0.8
1.0
1.2
VVDET /VVCTL (V)
1.4
1.6
1.8
2.0
Figure 40. POUT vs. VVDET/VVCTL at 350 MHz for Open-Loop Power Control Mode
VP
+5V
C1
0.1µF
VPOS
IN
IBBN
C3
1000pF
LO
C4
1000pF
LOIP
37
36
35
ENBL
23
22
C19
1000pF
MODOUT
24
21
10
NC
ATTI
9
12
25
26
33
34
IQ MOD
BIAS
ATTCM
17
15dB
QUADRATURE
PHASE
SPLITTER
C11
1000pF
ATTCM C10 1000pF
14
ATTO
C12 1000pF
20
ATTOUT
LOIN
ADL5386
QBBN
QP
C13
0.1µF
VPOS VPOS
38
IBBP
C14
0.1µF
QBBP
6
VREF
2V
29
4x
30
TEMP
TEMP
39
2
VDET/VCTL
ATTENUATION
CONTROL
0V TO 2V
CLPF
C7
0.1µF
I
1
INLO
C5
0.1µF
4
LOG
DETECTOR
TEMPERATURE
SENSOR
8
7
5
V
3
VSET
11 13 15 16 18 19 27 28 31 32 40
INHI
TADJ
C6
0.1µF
VP
+5V
Figure 41. Basic Connections for Open-Loop Power Control Mode
Rev. 0 | Page 21 of 36
COMM
07664-041
IP
QN
C2
0.1µF
ADL5386
POWER SUPPLY AND GROUNDING
LO INPUT
The VPOS supply pins should be connected to a common 5 V
supply. This supply can vary from 4.75 to 5.5 V. The power
supply pins should be adequately decoupled using 0.1 μF
capacitors located close to each pin. Adjacent pins can share
decoupling capacitors, as shown in Figure 41.
A single-ended LO signal is applied to the LOIP pin through an
ac coupling capacitor. A square wave or a sine wave can be used
to drive the LO port. The recommended LO drive power is
−7 dBm. An LO power level of −7 dBm is the minimum level
that should be used for output frequencies below 140 MHz
(fLO ≤ 280 MHz). At output frequencies above 140 MHz, the
LO power can be reduced to −13 dBm. The LO return pin, LOIN,
should be ac-coupled to ground though a low impedance path.
The COMM ground pins should be connected to a common
low impedance ground plane. The exposed paddle on the
underside of the package is also soldered to a low thermal
and electrical impedance ground plane. If the ground plane
spans multiple layers on the circuit board, the layers should be
stitched together with nine vias under the exposed paddle. The
Analog Devices, AN-772 Application Note, A Design and
Manufacturing Guide for the Lead Frame Chip Scale Package
(LFCSP), discusses the thermal and electrical grounding of the
LFCSP in detail.
DEVICE ENABLE AND DISABLE
The IQ modulator section can be enabled or disabled by pulling
the ENBL pin high or low, respectively. The detector section of
the circuit can be disabled by pulling the TADJ pin high.
BASEBAND INPUTS
The baseband inputs, QBBP, QBBN, IBBP, and IBBN, must be
driven from a differential source. The nominal drive level of
1.4 V p-p differential (700 mV p-p on each pin) is biased to a
common-mode level of 500 mV dc. This drive level generates
an output power level (at MODOUT) of between 2 dBm and
6 dBm based on output frequency.
The dc common-mode bias level for the baseband inputs can
range from 400 mV to 600 mV. This results in a reduction in the
usable input ac swing range. The nominal dc bias of 500 mV allows
for the largest ac swing, limited on the bottom end by the ADL5386
input range and on the top end by the output compliance range
on most Analog Devices DACs.
The nominal LO drive of −7 dBm can be increased to up to
+2 dBm. The effect of LO power on sideband suppression and
carrier feedthrough is shown in Figure 15 and Figure 16.
AGC MODE
The on-board log amp power detector of the ADL5386 can be
used to implement an automatic output power control (commonly
referred to as AGC) loop that effectively linearizes the transfer
function of the VVA. To implement this mode, a number of
circuit modifications are necessary.
A portion of the output signal of the VVA is coupled back to the
input of the log amp detector. This can be done with a power
splitter or with a directional coupler as shown in Figure 42.
The coupling factor or power split ratio should be set so that
the detector never sees a power level that is greater than about
−10 dBm (the transfer function of the detector loses some linearity
above this level). In the example shown in Figure 42, a maximum
output power from the VVA/modulator of +3 dBm is desired. A
directional coupler with a coupling factor of approximately +15 dB
drops this level down to −12 dBm at the input of the detector.
The input signal to the detector produces a current that is
drawn from the summing node (Pin CLPF) into the detector
block. A setpoint voltage that is applied to the VSET pin is
converted into a current that is pumped into the summing
node. If these two currents are not equal, the net current flows
into or out of the CLPF capacitor on Pin 4. This changes the
voltage on the CLPF node that in turn changes the voltage on
the VDET/VCTL pin. This pin is internally connected to the
attenuation control pin of the VVA. Therefore, the attenuation
control voltage on Pin 7 (VDET/VCTL) increases or decreases
until the ISET and IDET currents match. When this equilibrium is
reached, the voltage on CLPF (and thereby on the control
voltage node of the VVA) is held steady.
Rev. 0 | Page 22 of 36
ADL5386
VP
+5V
C1
0.1µF
VPOS
IN
IBBN
C3
1000pF
LO
C4
1000pF
LOIP
37
36
35
ENBL
23
22
21
C19
1000pF
MODOUT
10
24
NC
ATTI
12
9
25
26
33
34
IQ MOD
BIAS
17
14
15dB
QUADRATURE
PHASE
SPLITTER
20
LOIN
ADL5386
QBBN
QP
C13
0.1µF
VPOS VPOS
38
IBBP
C14
0.1µF
QBBP
6
4x
29
7
30
4
LOG
DETECTOR
TEMPERATURE
SENSOR
ATTCM C11
C10 1000pF
ATTO
C12 1000pF
VREF
V
TEMP
TEMP
1
INLO
C5
0.1µF
39
2
5
50Ω
CLPF
3
VSET
8
DIRECTIONAL
COUPLER
POUTMAX = 3dBm
ATTOUT
VDET/VCTL
C7
0.1µF
I
1000pF
ATTCM
OUTPUT
POWER
SETPOINT
0.7V TO 1.5V
11 13 15 16 18 19 27 28 31 32 40
INHI
TADJ
C6
R4
0.1µF 22.1kΩ
R8
49.9Ω
COMM
FREQUENCY
COUPLER
INSERTION COUPLING
LOSS
FACTOR
140MHz
350MHz
860MHz
1450MHz
1900MHz
2150MHz
0.2dB
0.43dB
0.77dB
0.8dB
0.77dB
0.88dB
Figure 42. Basic Connections for AGC Mode
Rev. 0 | Page 23 of 36
15dB
15.51dB
13.68dB
14.33dB
15.2dB
15.97dB
07664-042
IP
QN
C2
0.1µF
ADL5386
5
4
0
3
+85°C
+25°C
–40°C
2
–10
1
–15
0
–20
–1
–25
–2
–30
–3
–35
–4
ERROR (dB)
POUT (dBm)
–5
1.6
4
1.4
3
VOUT (V)
0.6
0.7
0.8
0.9
1.0
VVSET (V)
1.1
1.2
1.3
VVOUT (V)
07664-043
1.0
0.5
2
1.2
1.4
Figure 43. POUT vs. VVSET Transfer Function in AGC Mode
(1 V p-p Differential Baseband Input Voltage on I and Q)
0
0.8
ERROR (dB)
0.6
–1
0.4
–2
0.2
–3
0
The error in decibels is given by
1
–65 –60 –55 –50 –45 –40 –35 –30 –25 –20 –15 –10 –5
0
–4
ERROR (dB)
POUT_IDEAL = SLOPE × (VVSET − INTERCEPT)
In general, the loop should be designed with a level of attenuation
between ATTO and INHI (detector input) that results in the
detector always seeing a power level that is within its linear
operating range. Because the power detector has a linear input
range that is larger than the attenuation range of the VVA this
is generally achievable. In addition, it is desirable to map the
desired VVA output power range into the detector’s region of
maximum linearity. In the example shown, where a maximum
output power of +3 dBm is desired, the input range to the detector
is −12 dBm to −44 dBm. Notice how the degraded linearity of
the detector below −40 dBm (see Figure 44) can also be observed
in the closed-loop transfer function at output power levels below
−25 dBm (Figure 43).
07664-044
Figure 43 shows the resulting transfer function of the AGC
loop, that is, output power (on ATTO) vs. setpoint voltage (on
VSET) at 350 MHz. Figure 43 shows a linear-in-dB relationship
between POUT and VVSET over at least 25 dB. It also includes a
plot of the linearity of the transfer function in dB. The linearity
is calculated by measuring the slope and intercept of the transfer
function using the VVSET and POUT data between VVSET levels of
0.7 and 1 V. This yields an idealized transfer function of
PIN (dBm)
ERROR (dB) = (POUT − POUT_IDEAL)/SLOPE
The relationship between the input level of the detector and the
voltage on VVSET follows from the nominal transfer function of
the detector when operating in measurement mode (VSET is
connected directly to VDET). Figure 44 shows the measurement
mode relationship between the detector input level and the output
voltage at 350 MHz. Figure 44 shows that an input level of −12 dBm
produces an output of 0.6 V. In AGC mode, a setpoint voltage of
0.6 V causes the loop to adjust until the detector input level is
−12 dBm. Remembering the coupling factor of the directional
coupler, the −12 dBm level at the detector corresponds to a
power level of approximately +3 dBm at the output of the VVA.
Therefore, with a 15 dB coupling factor, a setpoint voltage of 0.6
produces an output power from the VVA of 3 dBm, as shown in
Figure 43.
Figure 44. Measurement Mode Relationship Between
VVOUT/VVSET and Detector Input Power at 350 MHz
SETTING THE TADJ RESISTOR
The primary component of the temperature variation of the
VVOUT/VVSET voltage and the detector RF input is the drift of
the intercept. This temperature drift can be compensated by
connecting a resistor between TADJ (Pin 39) and ground.
The optimum resistance value for the frequencies at which the
ADL5386 is characterized has been experimentally determined to
be 22.1 kΩ. Note that the accuracy specifications of the detector
and performance plots assume that this resistance is in place.
Rev. 0 | Page 24 of 36
ADL5386
USING THE DETECTOR IN STANDALONE
MEASUREMENT MODE
DAC MODULATOR INTERFACING
The ADL5386 is designed to interface with minimal components
to members of the Analog Devices family of digital-to-analog
converters (DACs). These DACs feature an output current
swing from 0 mA to 20 mA, and the interface described in this
section can be used with any DAC that has a similar output.
The on-board log detector of the ADL5386 can be used in
measurement mode, that is, where an RF signal is applied to the
INHI pin of the detector, and an output voltage, proportional to
the log of this input signal, is provided at the VDET output. In
this mode, short VDET to VSET and ac couple the ATTI, ATTO,
and ATTCM pins to ground. Note that the VVA cannot be used
because the VVA control voltage shares a common pin with the
output of the detector.
Table 5 summarizes the required configuration changes for the
three operating modes discussed.
Table 5. Configuring Operating Modes
Mode
AGC
Open
loop 1
Standalone
detector
VSET
Externally apply
0.5 V to 1.4 V
Open
AC couple to MODOUT
or other RF signal
Connect to VDET
VDET/VCTL
Open
VREF
Open
ENBL
High
Externally apply
0 V to 2 V
Connect to VSET
Externally
apply 2 V
Open
High
MODOUT
AC couple
to ATTI
AC couple
to ATTI
RF output,
ac-coupled
High
ATTI
AC couple to
MODOUT
AC couple to
MODOUT
AC couple
to GND
ATTO
RF output
RF output
AC couple
to GND
Tie TADJ to VPOS.
VP
+5V
MOD OUT
C20 1000pF
C1
0.1µF
VPOS
IP
IBBP
IN
IBBN
C3
1000pF
LO
C4
1000pF
LOIP
C13
0.1µF
37
36
35
ENBL
23
22
21
C31 1000pF
MODOUT
24
10
NC
ATTI
9
12
25
26
IQ MOD
BIAS
33
ATTCM
17
15dB
QUADRATURE
PHASE
SPLITTER
34
C11
1000pF
ATTCM C10 1000pF
14
ATTO
C30 1000pF
20
LOIN
ADL5386
QBBN
QP
C14
0.1µF
VPOS VPOS
38
QN
C2
0.1µF
QBBP
6
VREF
29
4x
30
INLO
C5
0.1µF
TEMP
2
39
TADJ
INHI
C6
R4
0.1µF 22.1kΩ
VDET/VCTL
VDET
CLPF
C7
0.1µF
I
1
TEMP
4
LOG
DETECTOR
TEMPERATURE
SENSOR
8
7
5
V
3
VSET
11 13 15 16 18 19 27 28 31 32 40
COMM
R8
49.9Ω
07664-045
1
INHI
AC couple to ATTO
via directional coupler
AC couple to GND
DTIN
Figure 45. Connections for Operating the Detector in Standalone Mode
Rev. 0 | Page 25 of 36
ADL5386
TxDAC
An example of the interface using the AD9788 TxDAC is shown
in Figure 46. The baseband inputs of the ADL5386 require a dc
bias of 500 mV. The average output current on each of the outputs
of the AD9788 is 10 mA. Therefore, a single 50 Ω resistor to
ground from each of the DAC outputs results in an average current
of 10 mA flowing through each of the resistors, thus producing
the desired 500 mV dc bias for the inputs to the ADL5386.
OUT1_P
RBIP
50Ω
25
OUT1_P
OUT2_P
RBIP
50Ω
RBIN
50Ω
26
OUT1_N
29
OUT2_N
RBQN
50Ω
RBQP
50Ω
26
29
OUT2_N
IBBP
IBBP
RSLI
100Ω
RBIN
50Ω
OUT1_N
ADL5386
TxDAC
RBQN
50Ω
RBQP
50Ω
IBBN
QBBN
RSLQ
100Ω
30
QBBP
Figure 47. AC Voltage Swing Reduction Through Introduction of Shunt
Resistor Between Differential Pair
IBBN
The value of this ac voltage swing-limiting resistor is chosen based
on the desired ac voltage swing. Figure 48 shows the relationship
between the swing-limiting resistor and the peak-to-peak ac
swing that it produces when 50 Ω bias-setting resistors are used.
QBBN
2.0
1.8
Figure 46. Interface Between AD9788 and ADL5386 with 50 Ω Resistors to
Ground to Establish the 500 mV DC Bias for the ADL5386 Baseband Inputs
1.6
The AD9788 output currents source from 0 mA to 20 mA. With
the 50 Ω resistors in place, the ac voltage swing going into the
ADL5386 baseband inputs ranges from 0 V to 1 V. A full-scale
sine wave out of the AD9788 can be described as a 1 V p-p singleended (or 2 V p-p differential) sine wave with a 500 mV dc bias.
The AD9788 also has the capability of easily compensating for
gain, offset, and phase mismatch in the IQ signal path; therefore,
optimizing performance of the ADL5386.
1.4
1.2
1.0
0.8
0.6
0.4
07664-048
QBBP
DIFFERENTIAL SWING (V p-p)
30
07664-046
0.2
0
10
100
1000
10000
RL (Ω)
Limiting the AC Swing
Figure 48. Relationship Between AC Swing-Limiting Resistor and
Peak-to-Peak Voltage Swing with 50 Ω Bias-Setting Resistors
There are situations in which it is desirable to reduce the ac voltage
swing for a given DAC output current. To reduce the ac voltage
swing, add an additional resistor to the interface. This resistor is
placed in shunt between each side of the differential pair, as shown
in Figure 47. It has the effect of reducing the ac swing without
changing the dc bias already established by the 50 Ω resistors.
I
CHANNEL
1/2
AD9788
50Ω LINE
50Ω
50Ω LINE
50Ω
317.4nH
67.5pF
Filtering
When driving a modulator from a DAC, it is necessary to introduce
a low-pass filter between the DAC and the modulator to reduce
the DAC images. The interface for setting up the biasing and ac
swing lends itself well to the introduction of such a filter. The
filter can be inserted between the dc bias setting resistors and the ac
swing-limiting resistor, thus establishing the input and output
impedances for the filter. A filter example is shown in Figure 49.
156.9pF
317.4nH
67.5pF
100Ω LINE
372.5nH
124.7pF
372.5nH
156.9pF
0Ω
100Ω LINE
IBBP
200Ω
0Ω
IBBN
124.7pF
ADL5386
Q
CHANNEL
1/2
AD9788
50Ω LINE
50Ω
67.5pF
50Ω LINE
50Ω
317.4nH
67.5pF
156.9pF
317.4nH
100Ω LINE
372.5nH
124.7pF
372.5nH
156.9pF
0Ω
100Ω LINE
124.7pF
QBBP
200Ω
0Ω
QBBN
07664-050
OUT2_P
ADL5386
25
07664-047
Driving the ADL5386 with an Analog Devices TxDAC®
Figure 49. 39 MHz, 5-Pole Chebychev Filter with In-Band Ripple of 0.1 dB for a 155 MSPS, 128 QAM Transmitter
Rev. 0 | Page 26 of 36
ADL5386
SPECTRAL PRODUCTS FROM HARMONIC MIXING
LO GENERATION USING PLLs
For broadband applications, such as cable TV head-end
modulators, special attention must be paid to harmonics of the
LO. Figure 50 shows the level of these harmonics (out to 3 GHz)
as a function of the output frequency from 125 MHz to 1000 MHz,
in a single-sideband (SSB) test configuration, with a baseband
signal of 1 MHz and a SSB level of approximately 0 dBm. To read
this plot correctly, first pick the output frequency of interest on the
trace called POUT. The associated harmonics can be read off the
harmonic traces at multiples of this frequency. For example, at
an output frequency of 500 MHz, the fundamental power is
0 dBm. The power of the second (P2fc − BB) and third (P3fc + BB)
harmonics is −57 dBm (at 1000 MHz) and −11 dBm (at
1500 MHz), respectively. Of particular importance are the
products from odd harmonics of the LO, generated from
the switching operation in the mixers.
Analog Devices has a line of PLLs that can be used for generating
the LO signal. Table 6 lists the PLLs together with their maximum
frequency and phase noise performance.
For cable TV operation at frequencies above approximately
500 MHz, these harmonics fall out of the band and can be
filtered by a fixed filter. However, as the frequency drops
below 500 MHz, these harmonics start to fall close to or inside
the cable band. This calls for either limitation of the frequency
range to above 500 MHz or the use of a switchable filter bank
to block in-band harmonics at low frequencies.
10
POUT
0
–20
P7LO + BB
P5LO – BB
–30
–40
P2LO – BB
–50
–60
–70
P6LO – BB
–80
100
200
300
P4LO + BB
400
500
600
700
800
OUTPUT FREQUENCY (MHz)
900
Figure 50. Spectral Components for Output Frequencies
from 125 MHz to 1000 MHz
1000
Model
ADF4002
ADF4106
ADF4110
ADF4111
ADF4112
ADF4113
ADF4116
ADF4117
ADF4118
Frequency fIN (MHz)
400
6000
550
1200
3000
4000
550
1200
3000
At 1 kHz Phase Noise
dBc/Hz, 200 kHz PFD
−103 @ 400 MHz
−93 @ 900 MHz
−91 @ 540 MHz
−87@ 900 MHz
−90 @ 900 MHz
−91 @ 900 MHz
−89 @ 540 MHz
−87 @ 900 MHz
−90 @ 900 MHz
The ADF4360-x comes as a family of chips, with nine operating
frequency ranges. One can be chosen depending on the local
oscillator frequency required. While the use of the integrated
synthesizer may come at the expense of slightly degraded noise
performance from the ADL5386, it can be a cheaper alternative
to a separate PLL and VCO solution. Table 7 shows the options
available. An up-to-date list of available PLLs can be found at
www.analog.com/pll.
Table 7. ADF4360-x Family Operating Frequencies
P3LO + BB
07664-049
POUT, PHARMONIC (dBm)
–10
Table 6. PLL Selection Table
Model
ADF4360-0
ADF4360-1
ADF4360-2
ADF4360-3
ADF4360-4
ADF4360-5
ADF4360-6
ADF4360-7
ADF4360-8
ADF4360-9
Rev. 0 | Page 27 of 36
Output Frequency Range (MHz)
2400 to 2725
2050 to 2450
1850 to 2150
1600 to 1950
1450 to 1750
1200 to 1400
1050 to 1250
350 to 1800
65 to 400
1.1 to 200 (using auxiliary dividers)
ADL5386
TRANSMIT DAC OPTIONS
MODULATOR/DEMODULATOR OPTIONS
The AD9788 recommended in the previous sections is by no
means the only DAC that can be interfaced with the ADL5386.
There are other appropriate DACs depending on the level of
performance required. Table 8 lists the dual TxDACs that Analog
Devices offers for use in transmitter applications with the ADL5386.
Table 9 lists other Analog Devices modulators and demodulators.
Table 8. Dual TxDAC Selection Table
Part No.
AD9114/AD9115/AD9116/AD9117
AD9741/AD9743/AD9745/AD9746/
AD9747
AD9780/AD9781/AD9783
AD9776A/AD9778A/AD9779A
AD9785/AD9787/AD9788
Resolution
(Bits)
8, 10, 12, 14
8, 10, 12,
14, 16
12, 14, 16
12, 14, 16
12,14, 16
Output
Update
Rate (MSPS)
125
250
500
1000
800
All DACs listed have nominal bias levels of 0.5 V and use the
same DAC-modulator interface shown in Figure 46.
Table 9. Modulator/Demodulator Options
Part No.
AD8345
AD8346
AD8349
ADL5390
Modulator/
Demodulator
Modulator
Modulator
Modulator
Modulator
Frequency
Range (MHz)
140 to 1000
800 to 2500
700 to 2700
20 to 2400
ADL5370
ADL5371
ADL5372
ADL5373
ADL5374
ADL5375
AD8347
AD8348
ADL5382
ADL5387
ADL5590
ADL5591
AD8340
AD8341
Modulator
Modulator
Modulator
Modulator
Modulator
Modulator
Demodulator
Demodulator
Demodulator
Demodulator
Modulator
Modulator
Vector modulator
Vector modulator
300 to 1000
500 to 1500
1500 to 2500
2300 to 3000
3000 to 4000
400 to 6000
800 to 2700
50 to 1000
700 to 2700
50 to 2000
869 to 960
1805 to 1990
700 to 1000
1500 to 2400
Rev. 0 | Page 28 of 36
Comments
External
quadrature
ADL5386
EVALUATION BOARD
A populated, RoHS-compliant ADL5386 evaluation board is
available. The ADL5386 has an exposed paddle underneath the
package, which is soldered to the board.
VP
R22
10kΩ
C15
OPEN
R5
0Ω
C17
OPEN
R15 R23
C16
0Ω 0Ω
OPEN
R6
0Ω
ENBL
C18
OPEN
R16
0Ω
C1
0.1µF
IN
R17
0Ω
R18
0Ω
LO
QN
R29
OPEN
IBBP
R26
OPEN
R20
0Ω
R24
OPEN
37
36
35
ENBL
23
22
21
C12
1000pF
C9
1000pF
C19
OPEN
MODOUT
10
24
R2
OPEN
NC
ATTI
12
9
C11
ATTCM 1000pF
25
26
17
IQ MOD
BIAS
33
ATTCM
C10
1000pF
15dB
QUADRATURE
PHASE
SPLITTER
34
14
20
ADL5386
QBBN
C30
VREF 1000pF
QBBP
6
29
I
30
8
TEMP
R12
0Ω
TEMP
INLO
C5
0.1µF
7
4
39
2
VDET
CLPF
R13
0Ω
P2
C7
0.1µF
I
1
VSS1
R11
0Ω
VDET/VCTL
V
LOG
DETECTOR
TEMPERATURE
SENSOR
ATTOUT
ATTO
LOIN
R25
OPEN
QP
C13
0.1µF
VPOS VPOS
38
R28
OPEN
IBBN
R27
OPEN
C3
1000pF
LOIP
C4
1000pF
R19
0Ω
VPOS
C14
0.1µF
ATTIN
5
V
3
VSET
VSET
R9
0Ω
11 13 15 16 18 19 27 28 31 32 40
INHI
TADJ
C6
R4
0.1µF 22.1kΩ
COMM
R8
49.9Ω
DTIN
07664-051
IP
C2
0.1µF
VMOD
Figure 51. Evaluation Board Schematic
Table 10. Evaluation Board Configuration Options
Component
VP, GND
R22
R2, C9, C12,
C19
R17 to R20,
R24 to R29
Description
Power Supply and Ground Clip Leads.
Device Enable. Apply either 5 V or 0 V to the SMA connector labeled ENBL to enable or disable
the IQ modulator section of the circuit. If the ENBL SMA connector is left open, this node is
pulled high by R22, enabling the IQ modulator.
Modulator VVA Interconnect. The output of the IQ modulator is available at the VMOD SMA
connector. The input and output of the VVA can be accessed through the ATTIN and ATTOUT
SMA connectors. The IQ modulator output can be connected to the VVA by installing a 0 Ω
resistor at R2 and a 1000 pF capacitor at C19. In this mode, C9 and C12 should be removed.
Baseband Input Filters. These component pads can be used to implement a low-pass filter for
the baseband input signals.
Rev. 0 | Page 29 of 36
Default Condition
VP = 5 V, GND = 0 V
R22 = 10 kΩ
C9, C12 = 1000 pF (0402)
R2, C19 = open (0402)
R17 to R20 = 0 Ω (0402)
R24to R29 = open (0402)
ADL5386
Default Condition
P2 = installed
07664-052
Description
Detector Controller Mode vs. Measurement Mode. When P2 is installed, the detector operates
in standalone measurement mode, measuring the signal strength on the DTIN SMA connector
and providing an output voltage on the VDET and VSET SMA connectors. To operate the
device in AGC mode, P2 should be removed, a sample of the output of the VVA is connected
to DTIN (using a directional coupler or a power splitter), and a setpoint voltage should be
applied to the VSET SMA connector. To operate the VVA in open-loop mode, disable the
detector by connecting TADJ to VP. DTIN should be ac-coupled to ground, and P2 should be
removed. The VVA control voltage (0 V to 2 V) is applied to VDET, which becomes an input. The
VSS1 terminal must be connected to a fixed 2 V source.
Figure 52. Layout of the Evaluation Board, Top Layer
07664-053
Component
P2
Figure 53. Layout of the Evaluation Board, Bottom Layer
Rev. 0 | Page 30 of 36
ADL5386
CHARACTERIZATION SETUP
SSB SETUP
DETECTOR SETUP
Figure 54 is a diagram of the characterization test stand setup
for the ADL5386, which can test the product as a single sideband
modulator. The Aeroflex IFR 3416 signal generator provides the
I and Q inputs as well as the LO input. Output signals are measured
directly using the spectrum analyzer, and currents and voltages
are measured using the Agilent 34401A multimeter.
Figure 55 is a diagram of the characterization test stand setup
for the ADL5386, which can test the product as a log detector.
The HP 8648D signal generator provides the input signal of the
detector. All currents and voltages are measured using the
Agilent 34401A multimeter.
AEROFLEX IFR 3416 250kHz TO 6GHz
SIGNAL GENERATOR
FREQ 100MHz TO 4GHz LEVEL – 7dBm
BIAS 0.5V
BIAS 0.5V
GAIN 0.7V
GAIN 0.7V
RF OUTPUT
LO
ROHDE & SCHWARTZ SPECTRUM ANALYZER
FSU 20Hz TO 8GHz
CONNECT TO BACK OF UNIT
50MHz TO 2GHz
+6dBm
Q OUT Q/AM I OUT I/FM
90°
Q
0°
I
RF IN
AGILENT 34401A MULTIMETER
0.215ADC
OUTPUT
AGNDA
VP
LO
VMOD
5.0000 0.215A
QN
QP
AGILENT E3631A
POWER SUPPLY
IP
IN
±25V
+ COM –
07664-054
–
ADL5386 MODULATOR
TEST RACK
Figure 54. ADL5386 Characterization Board SSB Test Setup
ADL5386 DETECTOR TEST RACK
HP8648D 9kHz TO 4000MHz SIGNAL GENERATOR
AGILENT 34401A MULTIMETER
FREQUENCY = 860MHz
–30dBm
1.00 VDC
AGILENT 34401A MULTIMETER
0.015ADC
5.0000 0.015A
AGILENT E3631A
POWER SUPPLY
6V
+
–
±25V
+ COM –
ADL5386
AGNDA
VP
VDET/VSET
DTIN
07664-055
6V
+
ADL5386
Figure 55. ADL5386 Characterization Board Detector Test Setup
Rev. 0 | Page 31 of 36
ADL5386
VVA S-PARAMTERS SETUP
VVA INTERMODULATION TEST SETUP
Figure 56 is a diagram of the characterization test stand setup
for the ADL5386, which can test the product as a VVA. The HP
8753D network analyzer measures the s-parameters, while the
Data Precision 8200 sweeps the VCTL voltage. Currents and
voltages are measured using the Agilent 34401A multimeter.
Figure 57 is a diagram of the characterization test stand setup
for the ADL5386, which can test the product as a VVA. The IFR
2026B provides the two-tone signal to the VVA input, the Data
Precision 8200 sweeps the VCTL voltage, while the spectrum
analyzer measures the output tones of the VVA output. Currents
and voltages are measured using the Agilent 34401A multimeter.
ADL5386 VVAS-PARAMETERS TEST RACK
DATA PRECISION 8200
AGILENT 34401A MULTIMETER
HP8753D NETWORK ANALYZER
0.004ADC
AGNDA
VP
5.0000 0.004A
2.0000 0.00A
AGILENT E3631A
POWER SUPPLY
VDET
ATTIN
VSS1
ATTOUT
±25V
6V
–
+ COM –
07664-056
+
ADL5386
Figure 56. ADL5386 Characterization Board VVA S-Parameters Test Setup
IFR2026B 2.51GHz TRIPLE SOURCE
ROHDE & SCHWARTZ SPECTRUM ANALYZER
FSU 20Hz TO 8GHz
50MHz TO 2GHz
+6dBm
RF IN
DATA PRECISION 8200
ADL5386 VVA INTERMOD TEST RACK
AGILENT 34401A MULTIMETER
5.0000 0.004A
2.0000 0.00A
AGILENT E3631A
POWER SUPPLY
ADL5386
VDET
ATTIN
VSS1
ATTOUT
±25V
–
+ COM –
07664-057
6V
+
0.004 ADC
AGNDA
VP
Figure 57. ADL5386 Characterization Board VVA Intermodulation Test Setup
Rev. 0 | Page 32 of 36
ADL5386
OUTLINE DIMENSIONS
6.00
BSC SQ
0.60 MAX
0.60 MAX
TOP
VIEW
0.50
BSC
5.75
BSC SQ
0.50
0.40
0.30
12° MAX
0.05 MAX
0.02 NOM
0.30
0.23
0.18
1
4.25
4.10 SQ
3.95
EXPOSED
PAD
(BOT TOM VIEW)
21
20
11
10
0.25 MIN
4.50
REF
0.80 MAX
0.65 TYP
SEATING
PLANE
40
0.20 REF
COPLANARITY
0.08
FOR PROPER CONNECTION OF
THE EXPOSED PAD, REFER TO
THE PIN CONFIGURATION AND
FUNCTION DESCRIPTIONS
SECTION OF THIS DATA SHEET.
072108-A
PIN 1
INDICATOR
1.00
0.85
0.80
PIN 1
INDICATOR
31
30
COMPLIANT TO JEDEC STANDARDS MO-220-VJJD-2
Figure 58. 40-Lead Lead Frame Chip Scale Package [LFCSP_VQ]
6 mm × 6 mm Body, Very Thin Quad
(CP-40-1)
Dimensions shown in millimeters
ORDERING GUIDE
Model
ADL5386ACPZ-R2 1
ADL5386ACPZ-R71
ADL5386-EVALZ1
1
Temperature Range
–40°C to +85°C
–40°C to +85°C
Package Description
40-Lead LFCSP_VQ, 7” Tape and Reel
40-Lead LFCSP_VQ, 7” Tape and Reel
Evaluation Board
Z = RoHS Compliant Part.
Rev. 0 | Page 33 of 36
Package Option
CP-40-1
CP-40-1
Ordering Quantity
250
750
1
ADL5386
NOTES
Rev. 0 | Page 34 of 36
ADL5386
NOTES
Rev. 0 | Page 35 of 36
ADL5386
NOTES
©2009 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D07664-0-1/09(0)
Rev. 0 | Page 36 of 36