A 167 µW 915 MHz Gain-Boosted LC VCO
M. Shahriar Jahan, Tan Yang, Junjie Lu and Jeremy Holleman
I. INTRODUCTION
T
HE need for highly integrated and low-power frequency
synthesizers for implantable and wearable wireless medical
devices
is
continuously
growing.
Typically,
the
voltage-controlled oscillator (VCO) and frequency divider,
running at full radio frequency, dominate power consumption.
Performance improvement of the two common topologies of
VCOs is well documented in the literature. The LC VCOs are
still popular for their superior phase noise performance and low
supply sensitivity. But due to low quality factors of on-chip
inductors, active parts of the LC VCOs need high power to
counter the loss in the LC tanks. This puts a hard limit on
reduction of minimum startup power [1] [2]. LC VCOs also
suffer from limited tuning range. On the other hand, ring
oscillators (RO) offer easy integration and high tunability. At
the same time, they require considerable power to achieve
acceptable phase noise because of poor frequency stability [3]
[4]. Various techniques, such as injection-locking, current
reuse, etc., have been developed to improve performance for
both these types. Injection-locked ring oscillators can achieve
superb phase noise performance at low power, such as [5],
sacrificing tunability. Current reuse can lower the startup power
significantly in LC oscillators, as reported in [6].
As illustrated in Fig. 1, low-data-rate wireless links with
simple modulation schemes are able to tolerate higher phase
noise than that in most of the recently published VCOs. For
example, system-level simulations (using the MATLAB™
communications toolbox) indicate that a 200 kbps BFSK link
with 500 kHz frequency shift yields a bit error rate (BER) of
only 5.5 ppm with -80 dBc/Hz carrier phase noise at 1 MHz
This work was supported by the National Science Foundation
(DBI-1152361).
978-1-4799-8391-9/15/$31.00 ©2015 IEEE
882
5
50 kbps
100 kbps
200 kbps
500 kbps
1 Mbps
0
10
(-70,-90)
(-60,-80)
(-50,-70)
Phase Noise @(100 kHz, 1 MHz) (dBc/Hz)
GB-LC
RO
Colpitts
-80
-90
-100
-110
-120 -2
10
-1
0
Frequency Shift with
Supply Variation (kHz/mV)
Index Terms—915 MHz, LC VCO, ISM, low-power, FSK VCO,
gain-boosted, phase noise.
10
Fig. 1. Bit error rate (BER) of BFSK system with 500 kHz frequency shift for
different data rate and carrier phase noise levels.
Phase Noise (dBc/Hz)
at 1 MHz offset
Abstract— This paper presents the design and performance of a
gain-boosted LC voltage-controlled oscillator (VCO) topology for
ultra-low-power applications. The proposed topology utilizes a
second active gain stage to reduce startup power while
maintaining acceptable phase noise for low-data-rate
applications. The VCO consumes 167 µW from a 1.2 V supply
when operating at 915 MHz and exhibits phase noise of
-97.9 dBc/Hz at 1 MHz offset. It has a 4-bit digital tuning range of
about 80 MHz and an analog tuning range of at least 22.5 MHz.
The VCO also has a binary frequency-shift keying (BFSK)
modulating system with 550 kHz shift. The VCO is realized in a
0.13 µm CMOS process and occupies 0.26 mm2 of area.
Bit Error Rate (ppm)
Department of Electrical Engineering and Computer Science
The University of Tennessee
Knoxville, TN, USA
Email: {mjahan, tyang4, jlu9, jhollema}@utk.edu
2
10
GB-LC
RO
1
10
-2
-1
0
10
10
10
10
10
Power (mW)
Power (mW)
(a)
(b)
Fig. 2. Simulated (a) phase noise of 1 GHz signals, at 1 MHz offset and (b)
supply sensitivity from generalized structures of a single-ended, 5-stage ring
oscillator (RO), a single-ended Colpitts oscillator and a GB-LC oscillator for
different core power consumptions from 1.2 V supply.
offset. This shows that for simple low-data-rate communication
systems, phase noise can be compromised as a trade-off for low
power consumption.
While LC oscillators consume less power for a given phase
noise level than ring oscillators, their startup requirements
prevent them from taking full advantage of relaxed phase noise
requirements. In this paper, we describe a novel topology of LC
oscillator design, where an active gain cell is introduced into a
conventional LC oscillator to boost its startup gm. While this
degrades the frequency stability of the LC oscillator to some
extent, it still exhibits adequate phase noise performance in the
desired power range, whereas the RO structure does not. Fig. 2
shows a comparison between simulated phase noise and supply
sensitivity of simplified structures for a single-ended Colpitts
oscillator, a single-ended current-starved RO and the proposed
gain-boosted LC (GB-LC) oscillator at different power
consumption levels. For example, assuming a modest 10 dB
link margin and 1 Mbps data rate, a 60 µW RO would yield a
BER of 10000 ppm where a 50 µW GB-LC would still have
BER below 1 ppm. The proposed oscillator, with its moderate
phase noise and low startup criteria, fits the gap between the
high-noise, low-power RO and low-noise, startup-limited
Colpitts oscillator. This topology is an improvement over
conventional LC oscillator design, suitable for relaxed noise
requirements, and its performance should further improve with
smaller technology nodes and when combined with other
techniques, such as current reuse.
This paper describes the design and measurement results of a
GB-LC VCO operating in the 915 MHz ISM band. Section II
describes the structure and principle of operation of the
proposed GB-LC VCO. The measured performance of the
fabricated oscillator is shown in Section III. Section IV gives
the conclusion.
M6
M7
Large
capacitor
Large
capacitor
Vtune
M2
RF
M4
Cc
II. VCO STRUCTURE AND OPERATION
Gain cell
B. Tuning
The proposed VCO includes three frequency adjustment
mechanisms: coarse digital tuning to counter process variation,
fine analog tuning for use with a PLL for channel selection, and
a BFSK modulation system. All three modify the tank
capacitance and thereby change the tank’s resonant frequency.
The digital tuning system provides 9-step tuning controlled
by a 4-bit word by selectively connecting between 0 and 8 equal
capacitors to the tank to lower oscillation frequency. This
system provides a tuning range of about 80 MHz with the
902 – 928 MHz ISM band at center, which is sufficient to
counter process variations.
The analog fine-tuning system consists of a varactor, Ctune,
connected to the tank. It is controlled by a rail-to-rail (0 – 1.2 V)
input voltage, Vtune, with the highest frequency obtained when
Vtune = 0 V. The fine-tuning frequency range is designed to
cover only the ISM band and varies within 22.5 – 30.2 MHz,
depending on the coarse-tuning setting. A relatively low VCO
tuning gain, and thus a narrow tuning range, was chosen to
reduce reference spurs when the oscillator is used in a PLL.
The BFSK modulation system is similar to the digital tuning
system. Between one and three equal capacitors can be enabled,
providing a frequency shift of 550 kHz, 1.2 MHz, or
1.825 MHz, respectively.
C. Principle of Operation
The principle of operation of the proposed GB-LC VCO is
shown in Fig. 4. A conventional LC oscillator requires high
power to achieve gm large enough to counter the energy loss in a
low-Q on-chip LC tank. In the proposed GB-LC structure, the
gain cell is introduced in the loop to boost a smaller gm,
reducing startup power. The gain cell, driving only the gate
capacitance of the gm-device, can achieve the desired boosting
gain with much lower power consumption than the
transconductor in a conventional LC oscillator.
Large reduction of power consumption is possible by
bringing the bandwidth of the gain block close to the desired
883
vout
C1
M3 +1
Gm cell
Ctune
C2
vo,Gm
vo,A
M1
A. Core Structure
Fig. 3 shows the schematic of the proposed oscillator. The
core structure consists of a Gm cell, a gain cell, and an LC tank.
The gain cell is self-biased with a large resistor RF at its
threshold point to provide maximum gain. The Gm cell is
dc-coupled to the gain cell. The two cells have equal transistor
lengths and current density in order to ensure equal threshold
voltages. A single-ended inverter chain operates as a buffer to
convert the sinusoid voltage vtank to a rail-to-rail square
waveform.
vtank
Digitizing
buffer
L
M5
BFSK
Digital
tuning (+C FSK*1~3)
(+C bit*1~8)
C5
Fig. 3. Schematic of the proposed gain-boosted LC VCO.
R
-1
g m1 ≥ 1
R
gm1
-A
A ⋅ gm 2 ≥ 1
R
Phase lead by
tank to balance
phase lag in
gain cell
gm2
f
fosc
R
g m 2 < g m1
Fig. 4. Derivation of core structure of the proposed VCO and frequency of
oscillation.
M2
vt
M1
gm2,
ro2
gm1,
ro1
(a)
vtank
io,gm
vo,A
RL
CL
C2
vo,gm
C3
L
R
C1
(b)
Fig. 5. AC equivalent circuits of (a) the gain cell and (b) Gm cell and LC tank
for estimating oscillating frequency.
frequency of oscillation. However, the phase delay of the gain
block will cause oscillation to occur at a frequency offset from
tank resonance where the tank will be slightly inductive and
provide necessary phase lead to counter the delay. The tank’s Q
and the bandwidth of the gain cell determine the offset of the
oscillation frequency from the resonant frequency. For a
suitable tradeoff between power and frequency stability, the
oscillation frequency should be in the steep portion of tank
phase curve, as shown in Fig. 4.
D. Frequency of Oscillation
The oscillation frequency of the GB-LC can be easily
estimated using the ac equivalent circuit as shown in Fig. 5. As
explained in the previous sub-section, reduction of power
consumption will incur a phase delay in the gain cell as its
bandwidth, ωc, approaches the oscillation frequency. This
phase delay, θA, can be expressed as
⎛ω⎞
(1)
θ A = tan −1 ⎜ ⎟ = tan −1 (ω RLCL ) .
⎝ ωc ⎠
Here, RL is determined from RF and the small-signal output
resistances of M1 and M2 and CL is the total load capacitance
driven by the gain cell. Oscillation will occur at the frequency
(
)
where C3 is total parasitic capacitance off the vtank node.
Equating the two phases from (1) and (2) yieldds the equation for
oscillation frequency.
1
ωc R
(3)
f osc =
2π L (1 + ωc RC eff )
For this design, fosc is calculated to be 1.1554 GHz, ignoring
the added capacitors of the tuning systems. Siimulation predicts
oscillation at 1.126 GHz. The tuning capaacitors with their
parasitics will add to C3 and with the tuniing switched off,
simulation predicts fosc to be 948.5 MHz wherre θt is about 48º.
The digital tuning system is then used to tune to the ISM band.
E. Gm cell Bias Stabilization
Non-linear effects, such as unbalanced biaas currents in the
Gm cell, can cause the oscillation to disrupt thee bias point of the
Gm cell. A negative feedback loop comprisinng M5, a buffering
unity-gain amplifier, and the filter capacitor C5 stabilizes the Gm
cell’s DC output level, ensuring robust operattion.
Pad-driver
Decoupling
capacitors
Core
Bias
Decoupling
capacitors
with its own phase
where the LC tank balances this phase delay w
lead, which is given by the following equationn.
R 1 − ω 2 LCeff
(2)
θt = tan −1
ωL
Here, R is equivalent parallel resistance oof the inductor L,
which depends on the Q of the tank. Cefff = C3 + C1C2 C1 +C2 ,
Fig. 6. Microphotograph of a bare die co
ontaining the fabricated GB-LC
oscillator. The core structure occupies 360 × 340
3 µm2 area. Total area including
the bias circuit and a pad-driver buffeer needed only for testing is
700 × 340 µm2.
Fig. 7. Output spectra (overlaid) of the prop
posed BFSK GB-LC VCO which
show about 550 kHz frequency shift around 914
9 MHz center frequency.
III. MEASUREMENT RESULTS
The proposed GB-LC oscillator was im
mplemented in a
0.13 µm 1P8M CMOS process. Fig. 6 shows the
The core and bias
microphotograph of the fabricated oscillator. T
structures together occupy only 0.206 m
mm2 silicon area
including the 220 × 220 µm2, 15-turn, 37 nnH inductor. The
inductor is foundry-modeled. This areaa excludes the
pad-driving test buffer and supply decouplingg capacitors.
Fig. 7 shows the overlaid output spectra of the proposed
hybrid oscillator operating at 914 MHz ± 2255 kHz, selected by
one BFSK input. The 550 kHz shift can be increased to
The digital tuning
1.825 MHz using all three inputs together. T
range is measured to be 80 MHz, which is suufficient to allow
for process variations. The analog tuning raange varies from
22.5 to 30.2 MHz. With the help of analog aand digital tuning,
any frequency in the ISM band can be selecteed.
The phase noise spectrum is shown in Fiig. 8. At 1 MHz,
phase noise is measured to be -97.9 dBc/Hz. Fig. 9 shows the
constellation diagram and error statistics off FSK-modulated
output of the hybrid oscillator. The oscillator iis modulated with
a 100 kHz square wave, simulating a ‘010100101’ bitstream at
200 kbps. The selected frequency shift is 5500 kHz. Measured
rms FSK error is about 11.5% which is addequate for most
low-cost wireless applications [7].
The proposed GB-LC oscillator consumes 166.8 µW from a
Hz. This includes
1.2 V power supply, when tuned to 914.5 MH
the digitizing buffer used to obtain rail-to--rail square-wave
signal, but excludes power consumed byy the additional
pad-driving test buffer. The digitizing outputt buffer consumes
about 30% of the total 166.8 µW power, as predicted by
post-layout simulation. Minimum startup currrent, including the
digitizing buffer, is measured to be 100 µA.
884
Fig. 8. Phase noise spectrum of proposed
d GB-LC VCO output tuned to
914.5 MHz. Phase noise is -97.9 dBc/Hz at 1 MHz offset.
Fig. 9. Constellation diagram and FSK error results of the proposed VCO
output. The 914.5 MHz GB-LC is 2-FSK modulated
m
with a 100 kHz square
wave, simulating a 200 kbps ‘01010101’ bittstream. RMS FSK error is about
11.5%.
The figure of merit (FoM) used to compare VCO
performance is calculated using the following equation [8].
2
(4)
FoM = 10log10 ⎡ P1 Δf0f ⎤ − L ( Δf )
⎢⎣
⎥⎦
d
at Δf offset from
Here L(Δf) is phase noise in dBc/Hz
oscillation frequency fo with power consumption
c
of P mW. The
( )
TABLE I
PERFORMANCE COMPARISON WITH EXISTING WORKS
Ring (Calibrated)
Ring
LC (Current reuse)
LC
LC
LC
LC
Process
(nm)
65
65
65
65
130
90
180
Area
(mm2)
0.06
0.02
0.294
0.46
0.5
Gain-boosted LC
130
0.206
Works
Topology
[9]
[10]
[6]
[8]
[11]
[12]
[13]
This
work
Power
consumption
46 µW
10 mW
65 µW
9.8 mW
600 µW
380 µW
1.06 mW
166.8 µW
116.9 µW (core)
Frequency
1.38 GHz
685 MHz
4.9 GHz
5.52 GHz
14.1 GHz
915 MHz
1.19 GHz
914.5 MHz
FoM for this VCO is calculated to be 164.9 dB. Table I shows a
comparison of this oscillator to previously published works.
The FoM achieved in this work is somewhat inferior to the LC
oscillators, and comparable to ring oscillators in Table I, but
with lower power consumption than other published oscillators
at this frequency. This work is motivated by the need of an
ultra-low-power oscillator. Whereas the conventional LC
oscillators are hard-limited in case of power reduction because
of their startup criteria and the ring oscillators require higher
power to achieve phase noise performance comparable to LC
oscillators, this hybrid LC VCO topology allows low-power
operation with phase noise adequately low for simple
low-data-rate systems.
IV. CONCLUSION
We have described a novel gain-boosted LC VCO topology
that provides designers an intermediate option between the high
startup power required by LC VCOs and the poor stability of
ring oscillators. A summary of measured performance is given
in Table II. The designed VCO in this work operates at a center
frequency of 914.5 MHz with -97.9 dBc/Hz phase noise at
1 MHz offset, while consuming only 167 µW power. The VCO
is implemented with a BFSK system with 550 kHz shift that
shows only 11.5% rms error at 200 kbps, sufficient for
BER < 100 ppm. The novel hybrid topology allows reduction
of the startup power compared to LC oscillators and thus allows
ultra-low-power operation with phase noise adequately low for
Phase noise
(dBc/Hz)
-98 @ 10 MHz
-110.8 @ 1 MHz
-100 @ 1 MHz
-151.7 @ 20 MHz
-100.6 @ 1 MHz
-117 @ 1 MHz
-126 @ 1 MHz
Supply sensitivity
(ppm/mV)
53.3
-
FoM
(dB)
154.2
157
186
190.6
186
180.4
187.3
-97.9 @ 1 MHz
35
164.9
simple low-data-rate communication systems.
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TABLE II
PERFORMANCE SUMMARY OF THIS WORK
Technology
Silicon area
Operating frequency
Digital tuning range
Analog tuning range
Power consumption
Supply voltage
Phase noise
Supply sensitivity
FOM
0.13 µm 1P8M CMOS process
0.206 mm2
914.5 MHz
80 MHz
22.5~30.2 MHz
166.8 µW *
1.2 V
-97.9 dBc/Hz @ 1 MHz offset
32 kHz/mV (35 ppm/mV)
164.9 dB
BFSK (min. 550 kHz shift,
Modulation system
11.5% rms error @ 200 kbps)
* Core power 116.9 µW, excluding digitizing buffer, estimated from
simulation. Both figures exclude pad-driver. Core power is equally
divided between gain cell and Gm cell.
885
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frequency synthesizer dedicated to implantable medical microsystems,"
Analog Integrated Circuits and Signal Processing, vol. 58, no. 3, pp.
205-214, 2009.
[13] A. Italia, C. M. Ippolito, and G. Palmisano, "A 1-mW 1.13–1.9 GHz
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