Channel engineering of SOI MOSFETs for RF applications
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Citation
Chen, C.L. et al. “Channel engineering of SOI MOSFETs for RF
applications.” SOI Conference, 2009 IEEE International. 2009. 12. © 2009 IEEE
As Published
http://dx.doi.org/10.1109/SOI.2009.5318756
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Institute of Electrical and Electronics Engineers
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Wed May 25 21:53:04 EDT 2016
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http://hdl.handle.net/1721.1/53745
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Detailed Terms
Channel Engineering of SOI MOSFETs for RF Applications
C. L. Chen, J. M. Knecht, J. Kedzierski, C. K. Chen, P. M. Gouker, D-R. Yost,
P. Healey, P. W. Wyatt, and C. L. Keast
Lincoln Laboratory, Massachusetts Institute of Technology, Lexington, MA 02420-9108
Email: CLCHEN@LL.MIT.EDU, Tel: (781) 981-4507
Abstract-Channel engineering of SOI MOSFETs is
explored by altering ion implantation without adding any
new fabrication steps to the standard CMOS process. The
effects of implantation on characteristics important for RF
applications, such as transconductance, output resistance,
breakdown voltage, are compared. Data show that the best
overall RF MOSFET has no body and drain-extension
implants.
Introduction
Silicon MOSFETs have been used for RF circuits for
their high performance and relatively low power
consumption. Most RF circuits are integrated with logic
CMOS to provide mixed-signal functions or to realize a
compact system on a chip (SOC). High speed and low
leakage current are the most critical requirement for logic
circuits and they are achieved usually by deep scaling
while maintaining a high threshold voltage VT. However,
for most RF circuits, in addition to a low gate resistance, a
high output resistance, high drive current with high
breakdown, and high linearity are desirable.
The requirements for logic and RF MOSFETs are not
always the same and in some cases they are even opposite
to each other. Although different devices tailored for
logic and RF can be optimized separately, added
processes may not be compatible and they definitely
increase the cost. In this work, we showed that desired
RF properties can be obtained by simply modifying
channel implants of standard SOI logic MOSFETs
without additional masks or process steps.
Processing and implant engineering
The n-MOSFETs were fabricated using 150-nm fully
depleted (FD) SOI CMOS process with added metal Tgate [1] for RF applications. Poly-Si gate with 2.5-nm
gate oxide was used. Standard- and high-VT FETs were
implemented using different body implant doses. The
source/drain (S/D) extension and halo were implanted
before depositing an 85-nm-wide spacer, which was
followed by heavy S/D contact implants. Standard Co
salicide was used for contacts. The thicknesses for SOI
and BOX are 42 and 400 nm, respectively. Body doping
of the standard device is around 5×1017 cm-3 while the
unimplanted device is around 1×1017 cm-3 p-type.
The FETs compared in this work have either one of
the two body implants or no body implant at all.
Deviating from conventional devices, some FETs did not
have extension implants for drain, source, or both.
Because the same mask was used, no extension implant
also means no halo implant. All FETs use the standard
S/D contact implant.
Test results
The effects of body implant on 150-nm FETs are
shown in Fig. 1(a). As expected, the FET without body
implant (NoB) has lower VT, therefore, higher drain
current, and is still on at 0-V gate bias, Vg. It also shows
higher output resistance (Rout) in the saturation region and
higher breakdown voltage. Without the body implant, the
inversion charge is controlled dominantly by the gate bias
and less affected by the drain bias, resulting in a smaller
short channel effect (SCE). The peak transconductance
(gm) increases from 506 for the standard FET to
563 μS/μm without the body implant.
For high-VT FETs with higher body doping, as shown
in Fig. 1(b), the Rout also increases and this is the
conventional approach for SCE reduction. The apparent
kink in the I-V plot suggests that the FET is no longer
fully depleted and a higher body doping also lowers the
drain current Id at the same Vg, limiting power handling
capability for RF applications. Note that the drain is
biased beyond the designed 1.5 V to reveal breakdown
characteristics. Even biased below 1.5 V, it is not
uncommon to drive the FET into this regime when a large
signal is applied, and any sharp decrease in Rout will
degrade the linearity of RF circuits. Therefore, a high
breakdown voltage is highly desirable.
Obviously, a longer effective gate can reduce the
SCE and our data show that this can be achieved by
eliminating the drain extension implant (NoD) without
significant performance degradation. As shown in Fig.
2(a), the Rout and breakdown voltage (VBD) increase by
eliminating the drain extension implant. However, the
series resistance and the knee voltage also increase
because of higher drain resistance. Similar improvements
on Rout and breakdown, but without the negative effects,
were observed for the FET-NoB-NoD, as shown in Fig.
2(b). Although the SCE can be further reduced by
eliminating both source and drain extension implant
(NoSD), the device performance is severely degraded. At
absence of source to gate overlap, the gm is lowered by
more than 50% (not shown).
Figure 3 compares the gm and the subthreshold plots
of the standard FET with and without both body and drain
extension implants. Compared to the standard FET, the
FET-NoB-NoD shows more than 12% increase in gm
which peaks at lower Vg, characteristics favored for RF.
1
This work was supported by the Defense Advanced Research Projects Agency under Air Force Contract FA8721-05-C-0002. Opinions,
interpretations, conclusions, and recommendations are those of the authors, and are not necessarily endorsed by the United States
Government.
978-1-4244-5232-3/09/$25.00 ©2009 IEEE
Authorized licensed use limited to: MIT Libraries. Downloaded on April 05,2010 at 14:06:27 EDT from IEEE Xplore. Restrictions apply.
800
800
800
800
700
700
600
600
600
600
Standard
No drain-extension implant
400
400
300
300
800
800
0.5
0.5
1.0
1.0
400
400
300
300
200
200
0
0
0
0.0
0.5
0.5
1.0
1.0
1.5
1.5
Vd (V)
Vd
(V)
2.0
2.0
2.5
2.5
3.0
3.0
2.0
2.0
2.5
2.5
(b)
00
3.0
3.0
0
0.0
0.5
0.5
1.0
1.0
1.5
1.5
2.0
2.0
10
1.E-03
700
700
No body/drain-extension implant
10
ggm
m (μS/μm)
(μS/μm)
-6
1.E-06
10
400
400
Standard
1.E-07
300
300
-8
1.E-08
10
1.E-09
1.5 V
-12
1.E-12
-0.4 -0.2
-0.2
-0.4
10
0.0
0
Vd = 0.5 V
100
100
(a)
0.5 V
0.5 V
200
200
-10
1.E-10
1.E-11
1.5 V
Vd = 1.5 V
500
500
1.E-05
10
No body/drain-extension implant
600
600
-4
1.E-04
Standard
(b)
0
0
-0.4 -0.2
-0.2
-0.4
0.2 0.4
0.4 0.6
0.6 0.8
0.8 1.0
1.0 1.2
1.2 1.4
1.4 1.6
1.6
0.2
0.0
0
0.2 0.4
0.4 0.6
0.6 0.8
0.8 1.0
1.0 1.2
1.2 1.4
1.4
1.6
0.2
1.6
Vg (V)
(V)
Vg
Vg (V)
(V)
Vg
Fig. 3 Comparison of standard FET and FET-NoB-NoD with 150-nm
gate length and 10-μm-wide T-gate. (a) Subthreshold plot. (b) gm plot.
120
120
fT
fmax
110
110
180 nm metal-T gate length
(GHz)
ffTT, ffmax
max (GHz)
100
100
90
90
80
80
70
70
60
60
50
50
40
40
30
30
2x10T-180
2x10T-180-B2
Standard
High
VT
2x10T-180-NoB
No
body
2x10T-180-NoD
1x10T-180-NoD-NoB
No
drain No
body/drain
FET
Fig. 4 Measured fT and fmax of 180-nm-gate MOSFETs all with 10μm-side T-gate. The Vd is fixed at 1.5 V and Vg varies for maximum
fmax.
130
130
120
120
110
110
fmax (GHz)
(GHz)
fTf,T,fmax
100
100
90
90
150 nm
80
80
180 nm
fT
fmax
70
70
60
60
50
50
40
40
Standard
No drain 1x10T-150No
Standard1x10T-180No drain1x10T-180No
2x5T-150 1x10T-1501x10T-180
drain/body
NoD drain/body
NoD-NoB
NoD
NoD-NoB
FET
Fig. 5 Comparison of fT and fmax of FETs with different channel
implant and gate length. All FETs have one 10-μm wide T-gate finger
except for 150-nm standard FET, which has two 5-μm wide gate fingers.
Because of narrower gate, this FET inherently has slightly higher fT and
fmax than the others. The bias condition is the same as in Fig. 4.
Table I. Effects of implant on DC characteristics
High body doping
FETS
300
300
Id
gm
Rout
VBD
SS
Ioff
Standard
High threshold
(b)
0.5
0.5
1.0
1.0
1.5
1.5
2.0
2.0
2.5
2.5
3.0
3.0
Vd
Vd (V)
(V)
-2
1.E-02
Standard
400
400
2.5
2.5
wide T-gate. (a) Standard and no drain-extension implant. (b) Standard
and no body/drain-extension implant.
500
500
00
0
0.0
100
100
Fig. 2 Id-Vd of n-MOSFETs with 150-nm gate length and 10-μm-
Vg = 0 to 1.25 V
100
100
(a)
300
300
Vd
(V)
Vd (V)
200
200
100
100
1.5
1.5
30
30
600
600
Standard
500
500
Id(μA/μm)
(μA/μm)
Id
Id
(μA/μm)
Id (μA/μm)
600
600
400
400
(a)
00
0
0.0
700
700
No body implant
Standard
200
200
100
100
C. L. Chen, et al., IEEE Electron Device Lett., vol. 23, no. 1, 2002,
pp. 52-54.
Vg = 0 to 1.25 V
No body/drain implant
500
500
200
200
1.
700
700
Vg = 0 to 1.25 V
Id (μA/μm)
500
500
References
800
800
Id (μA/μm)
Id
(μA/μm)
Id (μA/μm)
Vg = 0 to 1.25 V
700
700
(A/μm)
IdId(A/μm)
Lack of body implant results in a higher subthreshold
swing (SS), 99.5 vs. 70.7 mV/dec for the standard FET at
Vd = 1.5V, and higher leakage current at 0 V. However,
unlike for logic circuits, these parameters are often not as
important for RF devices. Table I summarizes the effects
of various channel implants on the DC device parameters.
The results suggest that the FET-NoB-NoD has the most
desirable properties as an RF device.
On-wafer scattering (S) parameters were measured
and Fig. 4 compares the effects of channel engineering on
the fT and fmax. MOSFETs with 180-nm gate are
compared because of completeness of the implant splits
and similar trend is observed for 150-nm devices. In this
measurement, Vd is kept at 1.5 V while varying Vg and
the highest fT and fmax are shown. The fT increases with
gm and it peaks at the Vg coinciding with that for
maximum gm. The data show that the FET-NoB has the
highest fT because of the highest gm. However, the fmax
actually suffers slightly from a lower Rout. Despite a
lower fT, absence of the drain extension implant increases
Rout and decreases overlapping capacitance, resulting in a
Figure 5 shows similar
large increase in fmax.
improvement for 150-nm gate FETs which has a higher fT
than those with 180 nm gate. The highest fmax measured
is 119 GHz, a 20% increase compared to a standard FET.
A combination of no body and drain extension implant
provides the best overall RF performance. Although not
shown here, in this work, we also found that the FET
always degrades with increasing total gate width.
Therefore, for the same drive current and power of RF
circuits, smaller total gate width is desirable which also
favors the FETs without body implant.
Summary
Our results demonstrate that by simply changing the
implants in the channel of a FDSOI MOSFET, both DC
and RF performance can be improved and such
optimization can be easily integrated into the standard
logic CMOS. The best fT can be achieved by eliminating
the body implant while the highest fmax is obtained by also
eliminating the drain, but not source, extension and halo
implants.
No body
3.0
3.0
Vd
(V)
Vd (V)
No drain
Fig. 1 Id-Vd of n-MOSFETs with 150-nm gate length and 10-μm-wide
T-gate. (a) Standard and no body implant. (b) Standard and high VT.
No source/drain
No body/drain
2
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