ADSP-BF561 EZ-KIT Lite®
Evaluation System Manual
Revision 2.0, January 2005
Part Number
82-000811-01
Analog Devices, Inc.
One Technology Way
Norwood, Mass. 02062-9106
a
Copyright Information
© 2005 Analog Devices, Inc., ALL RIGHTS RESERVED. This document may not be reproduced in any form without prior, express written
consent from Analog Devices, Inc.
Printed in the USA.
Limited Warranty
The EZ-KIT Lite evaluation system is warranted against defects in materials and workmanship for a period of one year from the date of purchase
from Analog Devices or from an authorized dealer.
Disclaimer
Analog Devices, Inc. reserves the right to change this product without
prior notice. Information furnished by Analog Devices is believed to be
accurate and reliable. However, no responsibility is assumed by Analog
Devices for its use; nor for any infringement of patents or other rights of
third parties which may result from its use. No license is granted by implication or otherwise under the patent rights of Analog Devices, Inc.
Trademark and Service Mark Notice
The Analog Devices logo, VisualDSP++, the VisualDSP++ logo, Blackfin,
CROSSCORE, the CROSSCORE logo, and EZ-KIT Lite are registered
trademarks of Analog Devices, Inc.
All other brand and product names are trademarks or service marks of
their respective owners.
Regulatory Compliance
The ADSP-BF561 EZ-KIT Lite evaluation system has been certified to
comply with the essential requirements of the European EMC directive
89/336/EEC (inclusive 93/68/EEC) and, therefore, carries the “CE”
mark.
The ADSP-BF561 EZ-KIT Lite evaluation system has been appended to
Analog Devices Development Tools Technical Construction File referenced “DSPTOOLS1” dated December 21, 1997 and was awarded CE
Certification by an appointed European Competent Body and is on file.
The EZ-KIT Lite evaluation system contains ESD
(electrostatic discharge) sensitive devices. Electrostatic charges readily accumulate on the human
body and equipment and can discharge without
detection. Permanent damage may occur on devices
subjected to high-energy discharges. Proper ESD
precautions are recommended to avoid performance
degradation or loss of functionality. Store unused
EZ-KIT Lite boards in the protective shipping
package.
CONTENTS
PREFACE
Purpose of This Manual ................................................................. xii
Intended Audience ........................................................................ xiii
Manual Contents .......................................................................... xiii
What’s New in This Manual ........................................................... xiv
Technical or Customer Support ...................................................... xiv
Supported Processors ....................................................................... xv
Product Information ....................................................................... xv
MyAnalog.com .......................................................................... xv
Processor Product Information .................................................. xvi
Related Documents .................................................................. xvi
Online Technical Documentation ........................................... xviii
Accessing Documentation From VisualDSP++ .................... xviii
Accessing Documentation From Windows ............................ xix
Accessing Documentation From Web ................................... xix
Printed Manuals ....................................................................... xix
VisualDSP++ Documentation Set .......................................... xx
Hardware Tools Manuals ....................................................... xx
Processor Manuals ................................................................. xx
ADSP-BF561 EZ-KIT Lite Evaluation System Manual
v
CONTENTS
Data Sheets .......................................................................... xx
Notation Conventions ................................................................... xxi
USING EZ-KIT LITE
Package Contents ......................................................................... 1-2
Default Configuration .................................................................. 1-3
Installation and Session Startup ..................................................... 1-5
Evaluation License Restrictions ..................................................... 1-6
External Memory .......................................................................... 1-6
LEDs and Push Buttons ................................................................ 1-9
Audio Interface ........................................................................... 1-10
Video Interface ........................................................................... 1-11
Example Programs ...................................................................... 1-12
Flash Programmer Utility ............................................................ 1-12
Background Telemetry Channel .................................................. 1-13
VisualDSP++ Interface ................................................................ 1-13
Target Options ...................................................................... 1-14
Reset Options ................................................................... 1-14
On Emulator Exit ............................................................. 1-14
XML File ......................................................................... 1-15
Other Options .................................................................. 1-15
Restricted Software Breakpoints ............................................. 1-17
EZ-KIT LITE HARDWARE REFERENCE
System Architecture ...................................................................... 2-2
vi
ADSP-BF561 EZ-KIT Lite Evaluation System Manual
CONTENTS
External Bus Interface Unit ...................................................... 2-3
SPORT0 Audio Interface ......................................................... 2-3
SPI Interface ........................................................................... 2-3
Programmable Flags ................................................................. 2-4
PPI Interfaces .......................................................................... 2-6
Video Output (PPI1) .......................................................... 2-7
Video Input (PPI0) ............................................................. 2-8
UART Port .............................................................................. 2-8
Expansion Interface ................................................................. 2-8
JTAG Emulation Port .............................................................. 2-9
Jumper and DIP Switch Settings .................................................. 2-10
Video Configuration Switch (SW2) ....................................... 2-10
Boot Mode Switch (SW3) ...................................................... 2-11
Push Button Enable Switch (SW4) ......................................... 2-12
PPI Clock Select Switch (SW5) .............................................. 2-13
Test DIP Switches (SW10 and SW11) .................................... 2-13
LEDs and Push Buttons .............................................................. 2-14
Reset Push Button (SW1) ...................................................... 2-14
Programmable Flag Push Buttons (SW9–6) ............................ 2-15
Power LED (J7) ..................................................................... 2-15
Reset LEDs (LED2 and LED3) .............................................. 2-15
USB Monitor LED (LED4) ................................................... 2-16
User LEDs (LED12–5, LED20–13) ....................................... 2-16
Connectors ................................................................................. 2-17
ADSP-BF561 EZ-KIT Lite Evaluation System Manual
vii
CONTENTS
Expansion Interface (J3–1) .................................................... 2-17
Audio (J4 and J5) .................................................................. 2-18
Video (J6) ............................................................................. 2-18
Power (J7) ............................................................................ 2-18
USB (J8) .............................................................................. 2-19
RS232 (P2) ........................................................................... 2-20
SPORT0 (P3) ....................................................................... 2-20
JTAG (P4) ............................................................................ 2-20
BILL OF MATERIALS
INDEX
viii
ADSP-BF561 EZ-KIT Lite Evaluation System Manual
PREFACE
Thank you for purchasing the ADSP-BF561 EZ-KIT Lite®, Analog
Devices, Inc. evaluation system for Blackfin® processors.
The Blackfin processors are embedded processors that support a Media
Instruction Set Computing (MISC) architecture. This architecture is the
natural merging of RISC, media functions, and digital signal processing
(DSP) characteristics towards delivering signal processing performance in
a microprocessor-like environment.
The evaluation board is designed to be used in conjunction with the VisualDSP++® development environment to test the capabilities of the
ADSP-BF561 Blackfin processors. The VisualDSP++ development environment gives you the ability to perform advanced application code
development and debug, such as:
• Create, compile, assemble, and link application programs written
in C++, C and ADSP-BF561 assembly
• Load, run, step, halt, and set breakpoints in application program
• Read and write data and program memory
• Read and write core and peripheral registers
• Plot memory
Access to the ADSP-BF561 processor from a personal computer (PC) is
achieved through a USB port or an optional JTAG emulator. The USB
interface gives unrestricted access to the ADSP-BF561 processor and the
evaluation board peripherals. Analog Devices JTAG emulators offer faster
ADSP-BF561 EZ-KIT Lite Evaluation System Manual
ix
communication between the host PC and target hardware. Analog Devices
carries a wide range of in-circuit emulation products. To learn more about
Analog Devices emulators and processor development tools, go to
http://www.analog.com/dsp/tools/.
ADSP-BF561 EZ-KIT Lite provides example programs to demonstrate
the capabilities of the evaluation board.
ADSP-BF561 EZ-KIT Lite installation is part of the VisuL The
alDSP++ installation. The EZ-KIT Lite is a licensed product that
offers an unrestricted evaluation license for the first 90 days. Once
the initial unrestricted 90-day evaluation license expires:
• VisualDSP++ allows a connection to the ADSP-BF561
EZ-KIT Lite via the USB Debug Agent interface only. Connections to simulators and emulation products are no longer
allowed.
• The linker restricts a users program to 41 KB of internal
memory for code space with no restrictions for data space.
The board features:
• Analog Devices ADSP-BF561 processor
D
D
256-pin Mini-BGA package
30 MHz CLKIN oscillator
• Synchronous Dynamic Random Access Memory (SDRAM)
D
64 MB (16M x 16 bits x 2 chips)
• Flash Memory
D
x
8 MB (4M x 16 bits)
ADSP-BF561 EZ-KIT Lite Evaluation System Manual
Preface
• Analog Audio Interface
D
D
D
AD1836 A – Analog Devices 96 kHz audio codec
4 input RCA phono jacks (2 Stereo Channels)
6 output RCA phono jacks (3 Stereo Channels)
• Analog Video Interface
D
D
ADV7183A video decoder w/ 3 input RCA phono jacks
ADV7179 video encoder w/ 3 output RCA phono jacks
• Universal Asynchronous Receiver/Transmitter (UART)
D
D
ADM3202 RS-232 line driver/receiver
DB9 male connector
• LEDs
D
20 LEDs: 1 power (green), 1 board reset (red), 1 USB (red),
16 general purpose (amber), and 1 USB monitor (amber)
• Push Buttons
D
5 push buttons with debounce logic: 1 reset,
4 programmable flags
• Expansion Interface
D PPI0, PPI1, SPI, EBIU, Timers11-0, UART,
Programmable Flags, SPORT0, SPORT1
• Other Features
D
JTAG ICE 14-pin header
The EZ-KIT Lite board holds 8 MB of flash memory, which can be used
to store user-specific boot code, allowing the board to run as a stand-alone
unit. The board also holds 512-Mb SDRAM, which can be used at runtime. For more information see “External Memory” on page 1-6.
ADSP-BF561 EZ-KIT Lite Evaluation System Manual
xi
Purpose of This Manual
interfaces with the AD1836A audio codec, allowing you to create
audio signal processing applications. SPORT0 also attaches to an off-board
connector to allow communication with other serial devices. For information about SPORT0, see “SPORT0 Audio Interface” on page 2-3.
SPORT0
The Parallel Peripheral Interfaces (PPIs) of the processor connect to both
a video encoder and video decoder, allowing you to create video signal
processing applications. For information on how the board utilizes the
processor’s PPIs, see “PPI Interfaces” on page 2-6.
The UART of the processor connects to an RS232 Line Driver and a DB9
male connector, allowing you to interface with a PC or other serial device.
For information about the UART, see “UART Port” on page 2-8.
Additionally, the EZ-KIT Lite board provides access to most of the processor’s peripheral ports. Access is provided in the form of a
three-connector expansion interface. For information about the expansion
interface, see “Expansion Interface” on page 2-8.
Purpose of This Manual
The ADSP-BF561 EZ-KIT Lite Evaluation System Manual provides
instructions for installing the product hardware (board). The text
describes the operation and configuration of the board components and
provides guidelines for running your own code on the ADSP-BF561
EZ-KIT Lite. Finally, a schematic and a bill of materials are provided as a
reference for future designs.
The product software installation is detailed in the VisualDSP++ Installation Quick Reference Card.
xii
ADSP-BF561 EZ-KIT Lite Evaluation System Manual
Preface
Intended Audience
The primary audience for this manual is a programmer who is familiar
with Analog Devices processors. This manual assumes that the audience
has a working knowledge of the appropriate processor architecture and
instruction set. Programmers who are unfamiliar with Analog Devices
processors can use this manual but should supplement it with other texts
(such as the ADSP-BF561 Blackfin Processor Hardware Reference and
Blackfin Processor Instruction Set Reference) that describe your target
architecture.
Programmers who are unfamiliar with VisualDSP++ should refer to the
VisualDSP++ online Help and user’s or getting started guides. For the
locations of these documents, see “Related Documents”.
Manual Contents
The manual consists of:
• Chapter 1, “Using EZ-KIT Lite” on page 1-1
Describes the EZ-KIT Lite functionality from a programmer’s perspective and provides an easy-to-access memory map
• Chapter 2, “EZ-KIT Lite Hardware Reference” on page 2-1
Provides information on the EZ-KIT Lite hardware components.
ADSP-BF561 EZ-KIT Lite Evaluation System Manual
xiii
What’s New in This Manual
• Appendix A, “Bill Of Materials” on page A-1
Provides a list of components used to manufacture the EZ-KIT
Lite board.
• Appendix B, “Schematics” on page B-1
Provides the resources to allow EZ-KIT Lite board-level debugging
or to use as a reference design.
appendix is not part of the online Help. The online Help
L This
viewers should go to the PDF version of the ADSP-BF561 EZ-KIT
Lite Evaluation System Manual located in the Docs\EZ-KIT Lite
Manuals folder on the installation CD to see the schematics. Alternatively, the schematics can be found on the Analog Devices Web
site, www.analog.com/processors.
What’s New in This Manual
This revision of the ADSP-BF561 EZ-KIT Lite Evaluation System Manual
provides an updated listing of related documents and updated licensing
information.
Technical or Customer Support
You can reach DSP Tools Support in the following ways.
• Visit the Embedded Processing and DSP products Web site at
http://www.analog.com/processors/technicalSupport
• E-mail tools questions to
dsptools.support@analog.com
• E-mail processor questions to
dsp.support@analog.com
• Phone questions to 1-800-ANALOGD
xiv
ADSP-BF561 EZ-KIT Lite Evaluation System Manual
Preface
• Contact your Analog Devices, Inc. local sales office or authorized
distributor
• Send questions by mail to:
Analog Devices, Inc.
One Technology Way
P.O. Box 9106
Norwood, MA 02062-9106
USA
Supported Processors
This EZ-KIT Lite evaluation system supports the Analog Devices
ADSP-BF561 Blackfin embedded processors.
Product Information
You can obtain product information from the Analog Devices Web site,
from the product CD-ROM, or from the printed publications (manuals).
Analog Devices is online at www.analog.com. Our Web site provides information about a broad range of products—analog integrated circuits,
amplifiers, converters, and digital signal processors.
MyAnalog.com
MyAnalog.com is a free feature of the Analog Devices Web site that allows
customization of a Web page to display only the latest information on
products you are interested in. You can also choose to receive weekly
e-mail notifications containing updates to the Web pages that meet your
interests. MyAnalog.com provides access to books, application notes, data
sheets, code examples, and more.
ADSP-BF561 EZ-KIT Lite Evaluation System Manual
xv
Product Information
Registration:
Visit www.myanalog.com to sign up. Click Register to use MyAnalog.com.
Registration takes about five minutes and serves as means for you to select
the information you want to receive.
If you are already a registered user, just log on. Your user name is your
e-mail address.
Processor Product Information
For information on embedded processors and DSPs, visit our Web site at
www.analog.com/processors, which provides access to technical publications, data sheets, application notes, product overviews, and product
announcements.
You may also obtain additional information about Analog Devices and its
products in any of the following ways.
• E-mail questions or requests for information to
dsp.support@analog.com
• Fax questions or requests for information to
1-781-461-3010 (North America)
+49 (89) 76 903-557 (Europe)
• Access the FTP Web site at
ftp ftp.analog.com or ftp
137.71.23.21
ftp://ftp.analog.com
Related Documents
For information on product related development software, see the following publications.
xvi
ADSP-BF561 EZ-KIT Lite Evaluation System Manual
Preface
Table 1. Related Processor Publications
Title
Description
ADSP-BF561 Blackfin Embedded Symmetric Multi-Processor Datasheet
General functional description, pinout, and timing
ADSP-BF561 Blackfin Processor Hardware
Reference
Description of internal processor architecture and
all register functions
Blackfin Processor Instruction Set Reference
Description of all allowed processor assembly
instructions
Table 2. Related VisualDSP++ Publications
Title
Description
VisualDSP++ User’s Guide
Description of VisualDSP++ features and usage
VisualDSP++ Assembler and Preprocessor
Manual
Description of the assembler function and commands
VisualDSP++ C/C++ Complier and
Library Manual for Blackfin Processors
Description of the complier function and commands for Blackfin processors
VisualDSP++ Linker & Utilities Manual
Description of the linker function and commands
VisualDSP++ Loader Manual
Description of the loader/splitter function and commands
you plan to use the EZ-KIT Lite board in conjunction with a
L IfJTAG
emulator, also refer to the documentation that accompanies
the emulator.
All documentation is available online. Most documentation is available in
printed form.
Visit the Technical Library Web site to access all processor and tools manuals and data sheets:
http://www.analog.com/processors/resources/technicalLibrary
ADSP-BF561 EZ-KIT Lite Evaluation System Manual
xvii
Product Information
Online Technical Documentation
Online documentation comprises the VisualDSP++ Help system, software
tools manuals, hardware tools manuals, processor manuals, the Dinkum
Abridged C++ library, and Flexible License Manager (FlexLM) network
license manager software documentation. You can easily search across the
entire VisualDSP++ documentation set for any topic of interest. For easy
printing, supplementary .PDF files of most manuals are provided in the
Docs folder on the VisualDSP++ installation CD.
Each documentation file type is described as follows.
File
Description
.CHM
Help system files and manuals in Help format
.HTM or
.HTML
Dinkum Abridged C++ library and FlexLM network license manager software documentation. Viewing and printing the .HTML files requires a browser, such as
Internet Explorer 4.0 (or higher).
.PDF
VisualDSP++ and processor manuals in Portable Documentation Format (PDF).
Viewing and printing the .PDF files requires a PDF reader, such as Adobe Acrobat
Reader (4.0 or higher).
If documentation is not installed on your system as part of the software
installation, you can add it from the VisualDSP++ CD at any time by running the Tools installation. Access the online documentation from the
VisualDSP++ environment, Windows® Explorer, or the Analog Devices
Web site.
Accessing Documentation From VisualDSP++
To view VisualDSP++ Help, click on the Help menu item or go to the
Windows task bar and navigate to the VisualDSP++ documentation via
the Start menu.
xviii
ADSP-BF561 EZ-KIT Lite Evaluation System Manual
Preface
To view ADSP-BF561 EZ-KIT Lite Help, which is part of the VisualDSP++ Help system, use the Contents or Search tab of the Help
window.
Accessing Documentation From Windows
In addition to any shortcuts you may have constructed, there are many
ways to open VisualDSP++ online Help or the supplementary documentation from Windows.
Help system files (.CHM) are located in the Help folder, and .PDF files are
located in the Docs folder of your VisualDSP++ installation CD-ROM.
The Docs folder also contains the Dinkum Abridged C++ library and the
FlexLM network license manager software documentation.
Your software installation kit includes online Help as part of the Windows® interface. These help files provide information about VisualDSP++
and the ADSP-BF561 EZ-KIT Lite evaluation system.
Accessing Documentation From Web
Download manuals at the following Web site:
http://www.analog.com/processors/resources/technicalLibrary/manuals.
Select a processor family and book title. Download archive (.ZIP) files, one
for each manual. Use any archive management software, such as WinZip,
to decompress downloaded files.
Printed Manuals
For general questions regarding literature ordering, call the Literature
Center at 1-800-ANALOGD (1-800-262-5643) and follow the prompts.
ADSP-BF561 EZ-KIT Lite Evaluation System Manual
xix
Product Information
VisualDSP++ Documentation Set
To purchase VisualDSP++ manuals, call 1-603-883-2430. The manuals
may be purchased only as a kit.
If you do not have an account with Analog Devices, you are referred to
Analog Devices distributors. For information on our distributors, log onto
http://www.analog.com/salesdir/continent.asp.
Hardware Tools Manuals
To purchase EZ-KIT Lite and In-Circuit Emulator (ICE) manuals, call
1-603-883-2430. The manuals may be ordered by title or by product
number located on the back cover of each manual.
Processor Manuals
Hardware reference and instruction set reference manuals may be ordered
through the Literature Center at 1-800-ANALOGD (1-800-262-5643),
or downloaded from the Analog Devices Web site. Manuals may be
ordered by title or by product number located on the back cover of each
manual.
Data Sheets
All data sheets (preliminary and production) may be downloaded from the
Analog Devices Web site. Only production (final) data sheets (Rev. 0, A,
B, C, and so on) can be obtained from the Literature Center at
1-800-ANALOGD (1-800-262-5643); they also can be downloaded from
the Web site.
To have a data sheet faxed to you, call the Analog Devices Faxback System
at 1-800-446-6212. Follow the prompts and a list of data sheet code
numbers will be faxed to you. If the data sheet you want is not listed,
check for it on the Web site.
xx
ADSP-BF561 EZ-KIT Lite Evaluation System Manual
Preface
Notation Conventions
Text conventions used in this manual are identified and described as
follows.
Example
Description
Close command
(File menu)
Titles in reference sections indicate the location of an item within the
VisualDSP++ environment’s menu system (for example, the Close
command appears on the File menu).
{this | that}
Alternative required items in syntax descriptions appear within curly
brackets and separated by vertical bars; read the example as this or
that. One or the other is required.
[this | that]
Optional items in syntax descriptions appear within brackets and separated by vertical bars; read the example as an optional this or that.
[this,…]
Optional item lists in syntax descriptions appear within brackets
delimited by commas and terminated with an ellipse; read the example
as an optional comma-separated list of this.
.SECTION
Commands, directives, keywords, and feature names are in text with
letter gothic font.
filename
Non-keyword placeholders appear in text with italic style format.
L
Note: For correct operation, ...
A Note provides supplementary information on a related topic. In the
online version of this book, the word Note appears instead of this
symbol.
a
Caution: Incorrect device operation may result if ...
Caution: Device damage may result if ...
A Caution identifies conditions or inappropriate usage of the product
that could lead to undesirable results or product damage. In the online
version of this book, the word Caution appears instead of this symbol.
[
Warning: Injury to device users may result if ...
A Warning identifies conditions or inappropriate usage of the product
that could lead to conditions that are potentially hazardous for the
devices users. In the online version of this book, the word Warning
appears instead of this symbol.
ADSP-BF561 EZ-KIT Lite Evaluation System Manual
xxi
Notation Conventions
conventions, which apply only to specific chapters, may
L Additional
appear throughout this document.
xxii
ADSP-BF561 EZ-KIT Lite Evaluation System Manual
1 USING EZ-KIT LITE
This chapter provides specific information to assist you with development
of programs for the ADSP-BF561 EZ-KIT Lite evaluation system.
The information appears in the following sections.
• “Package Contents” on page 1-2
Lists the items contained in your ADSP-BF561 EZ-KIT Lite
package.
• “Default Configuration” on page 1-3
Shows the default configuration of the ADSP-BF561 EZ-KIT Lite.
• “Installation and Session Startup” on page 1-5
Instructs how to start a new or open an existing
ADSP-BF561EZ-KIT Lite session using VisualDSP++.
• “Evaluation License Restrictions” on page 1-6
Describes the restrictions of the VisualDSP++ demo license
shipped with the EZ-KIT Lite.
• “External Memory” on page 1-6
Defines the ADSP-BF561 EZ-KIT Lite’s external memory map.
• “LEDs and Push Buttons” on page 1-9·
Describes the board’s LEDs and push buttons.
• “Audio Interface” on page 1-10
Describes the board’s audio interface.
• “Video Interface” on page 1-11
Describes the board’s video interface.
ADSP-BF561 EZ-KIT Lite Evaluation System Manual
1-1
Package Contents
• “Example Programs” on page 1-12
Provides information about the example programs included in the
ADSP-BF561 EZ-KIT Lite evaluation system.
• “Flash Programmer Utility” on page 1-12
Highlights the advantages of the Flash Programmer utility of
VisualDSP++.
• “Background Telemetry Channel” on page 1-13
Highlights the advantages of the Background Telemetry Channel
feature of VisualDSP++.
• “VisualDSP++ Interface” on page 1-13
Describes the target options facilities of the EZ-KIT Lite system.
For more detailed information about programming the ADSP-BF561
Blackfin processor, see the documents referred to as “Related
Documents”.
Package Contents
Your ADSP-BF561 EZ-KIT Lite evaluation system package contains the
following items.
• ADSP-BF561 EZ-KIT Lite board
• VisualDSP++ Installation Quick Reference Card
• CD containing:
D
D
D
D
D
1-2
VisualDSP++ software
ADSP-BF561 EZ-KIT Lite software
USB driver files
Example programs
ADSP-BF561 EZ-KIT Lite Evaluation System Manual (this
document)
ADSP-BF561 EZ-KIT Lite Evaluation System Manual
Using EZ-KIT Lite
• Universal 7.5V DC power supply
• USB 2.0 cable
• Registration card (please fill out and return)
If any item is missing, contact the vendor where you purchased your
EZ-KIT Lite or contact Analog Devices, Inc.
Default Configuration
The EZ-KIT Lite evaluation system contains ESD
(electrostatic discharge) sensitive devices. Electrostatic
charges readily accumulate on the human body and
equipment and can discharge without detection. Permanent damage may occur on devices subjected to
high-energy discharges. Proper ESD precautions are
recommended to avoid performance degradation or
loss of functionality. Store unused EZ-KIT Lite boards
in the protective shipping package.
The ADSP-BF561 EZ-KIT Lite board is designed to run outside your personal computer as a stand-alone unit. You do not have to open your
computer case.
When removing the EZ-KIT Lite board from the package, handle the
board carefully to avoid the discharge of static electricity, which may damage some components. Figure 1-1 shows the default jumper settings, DIP
switch, connector locations, and LEDs used in installation. Confirm that
your board is set up in the default configuration before using the board.
ADSP-BF561 EZ-KIT Lite Evaluation System Manual
1-3
Default Configuration
Figure 1-1. EZ-KIT Lite Hardware Setup
1-4
ADSP-BF561 EZ-KIT Lite Evaluation System Manual
Using EZ-KIT Lite
Installation and Session Startup
correct operation, install the software and hardware in the
L For
order presented in the VisualDSP++ Installation Quick Reference
Card.
1. Verify that the yellow USB monitor LED (LED4, located near the
USB connector) is lit. This signifies that the board is communicating properly with the host PC and is ready to run VisualDSP++.
2. From the Start menu, navigate to the VisualDSP++ environment
via the Programs menu.
If you are running VisualDSP++ for the first time, the New Session
dialog box appears on the screen (skip the rest of the procedure and
go to step 3).
If you have run VisualDSP++ previously, the last opened session
appears on the screen.
To switch to another session, via the Session List dialog box, hold
down the Ctrl key while starting VisualDSP++ (go to step 5).
3. In Debug target, select Blackfin Emulators/EZ-KIT Lites.
In Platform, select the appropriate EZ-KIT Lite via a debug agent
(ADSP-BF561 EZ-KIT Lite via Debug Agent).
In Session name, type a new name or accept the default.
4. Click OK to return to the Session List.
5. Highlight the session and click Activate.
ADSP-BF561 EZ-KIT Lite Evaluation System Manual
1-5
Evaluation License Restrictions
Evaluation License Restrictions
The ADSP-BF561 EZ-KIT Lite installation is part of the VisualDSP++
installation. The EZ-KIT Lite is a licensed product that offers an unrestricted evaluation license for the first 90 days. Once the initial
unrestricted 90-day evaluation license expires:
• VisualDSP++ allows a connection to the ADSP-BF561 EZ-KIT
Lite via the USB Debug Agent interface only. Connections to simulators and emulation products are no longer allowed.
• The linker restricts a users program to 41 KB of internal memory
for code space with no restrictions for data space.
EZ-KIT Lite hardware must be connected and powered up to
L The
use VisualDSP++ with a valid evaluation or permanent license.
Refer to the VisualDSP++ Installation Quick Reference Card for details.
External Memory
EZ-KIT Lite board includes two types of external memory, 64-MB
SDRAM and 8-MB flash. Table 1-1 shows the memory map of these
devices. The complete configuration of the ADSP-BF561 processor internal SRAM is detailed in Figure 1-2.
Table 1-1. EZ-KIT Lite External Memory Map
Start Address End Address Description
0x00000000
0x3FFFFFF
SDRAM Bank 0; see “External Memory” on page 1-6
0x20000000
0x207FFFFF
ASYNC Memory Bank 0; see “External Memory” on page 1-6.
All other locations
1-6
Not used
ADSP-BF561 EZ-KIT Lite Evaluation System Manual
Using EZ-KIT Lite
CORE A MEMORY MAP
CORE B MEMORY MAP
0XFFFF FFFF
CORE MMR REGISTERS
0XFFE0 0000
0XFFB0 1000
0XFFB0 0000
0XFFA1 4000
0XFFA1 0000
0XFFA0 4000
0XFFA0 0000
0XFF90 8000
0XFF90 4000
0XFF90 0000
0XFF80 8000
0XFF80 4000
0XFF80 0000
RESERVED
L1 SCRATCHPAD SRAM (4K)
RESERVED
L1 INSTRUCTION SRAM/CACHE (16K)
RESERVED
L1 INSTRUCTION SRAM (16K)
L1 DATA BANK B SRAM (16K)
RESERVED
L1 DATA BANK A SRAM/CACHE (16K)
L1 DATA BANK A SRAM (16K)
RESERVED
L1 SCRATCHPAD SRAM (4K)
0XFF70 0000
RESERVED
0XFF61 4000
L1 INSTRUCTION SRAM/CACHE (16K)
0XFF61 0000
RESERVED
0XFF60 4000
0XFF50 8000
0XFF50 4000
0XFF50 0000
0XFF40 8000
0XFF40 4000
0XFF40 0000
0XFEB2 0000
0XFEB0 0000
0XEF00 0800
RESERVED
RESERVED
L1 DATA BANK B SRAM/CACHE (16K)
0XFF70 1000
0XFF60 0000
CORE MMR REGISTERS
SYSTEM MMR REGISTERS
0XFFC0 0000
RESERVED
L1 INSTRUCTION SRAM (16K)
RESERVED
L1 DATA BANK B SRAM/CACHE (16K)
L1 DATA BANK B SRAM (16K)
RESERVED
L1 DATA BANK A SRAM/CACHE (16K)
L1 DATA BANK A SRAM (16K)
RESERVED
L2 SRAM (128K)
RESERVED
Figure 1-2. ADSP-BF561 Processor Internal Memory Map
The 8 MB of flash memory is organized as 4M x 16 bit and mapped into a
ADSP-BF561 processor’s ASYNC Memory Bank 0 (~AMS0, memory select
signal connects to the flash memory’s output enable pin).
The 64 MB of SDRAM is organized as 16M x 32 bits wide. The processor’s memory select pin ~SMS0 is configured for the SDRAM. Three
SDRAM control registers must be initialized in order to access the
SDRAM memory.
When in a VisualDSP++ EZ-KIT Lite session, you can automatically configure the SDRAM registers by selecting the Use XML reset values box on
the Target Options dialog box, which is accessible through the Settings
ADSP-BF561 EZ-KIT Lite Evaluation System Manual
1-7
External Memory
pull-down menu. The values for the EBIU_SDGCTL, EBIU_SDBCTL, and
EBIU_SDRRC registers have been set in the ADSP-BF561.xml file found in
your VisualDSP\SYSTEM folder under the RegReset tag. These values can
be changed to be more optimal depending on the SCLK frequency.
The values in Table 1-2 are programmed by default whenever Bank 0 is
accessed through the debugger (for example, when viewing memory windows or loading a program). The numbers are derived for maximum
flexibility and work for a system clock frequency between 60 MHz and
133 MHz.
Table 1-2. EZ-KIT Lite Session SDRAM Default Settings
Register
Value
Function
EBIU_SDGCTL
0x0091998D
Calculated with SCLK = 133 MHz
EBIU_SDBCTL
0x00000013
EBIU_SDRRC
0x000001CF
Calculated with SCLK = 120 MHz
The EBIU_SDGCTL register can only be written once after the processor
comes out of reset. Therefore, the user code should not reinitialize this
register. Clearing the Use XML reset values checkbox allows manual configuration of the EBIU registers. For more information, see “Target
Options” on page 1-14.
Automatic configuration of the SDRAM is not optimized for a specific
SCLK frequency. Table 1-3 shows the optimized configuration for the
SDRAM registers using a 120 MHz SCLK. The frequency of 120 MHz is
the maximum SCLK frequency when using a 600 MHz core frequency,
the maximum frequency for the EZ-KIT Lite. Only the SDRRC register
needs to be modified in the user code to achieve maximum performance.
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Using EZ-KIT Lite
Table 1-3. SDRAM Optimum Settings1
Register
Value
EBIU_SDGCTL
0x0091998D
EBIU_SDBCTL
0x00000013
EBIU_SDRRC
0x000003A0
1
Calculated with SCLK = 120 MHz
For more information about the memory connection on the EZ-KIT Lite,
see “External Bus Interface Unit” on page 2-3.
program is included in the EZ-KIT installation direcL Antoryexample
to demonstrate how to set up the SDRAM interface.
LEDs and Push Buttons
The EZ-KIT Lite provides four push buttons and sixteen LEDs for general-purpose IO.
Sixteen LEDs labeled LED5 through LED20 are controlled by the processor’s
programmable flags PF32 through PF47 (equivalent to PPI0 D15–8 and
PPI1 D15–8). These LEDs are accessed through the Flag 2 registers. First,
the direction must be configured to output by setting the bits of the
FIO2_DIR register to “1”. Then the value of the LEDs can be modified
using one the FIO2_FLAG_D, FIO2_FLAG_C, FIO2_FLAG_S, or FIO2_FLAG_T
registers.
The four general-purpose push buttons are labeled SW6 through SW9. These
connect to the programmable flags PF8–5. A status of each individual button can be read through the FIO0_FLAG_D register. When the
corresponding bit of the register reads “1”, a switch is being pressed-on.
When the switch is released, the bit reads “0”. A connection between the
ADSP-BF561 EZ-KIT Lite Evaluation System Manual
1-9
Audio Interface
push button and PF input is established through the SW4 DIP switch. For
information on how to disconnect the switch from the programmable flag
and use it for another objective, see “Push Button Enable Switch (SW4)”.
program is included in the EZ-KIT installation direcL Antoryexample
to demonstrate the functionality of the LEDs and push
buttons.
Audio Interface
The AD1836A audio codec provides three channels of stereo audio output
and two channels of multichannel 96 kHz input. The SPORT0 interface of
the processor links with the stereo audio data input and output pins of the
AD1836A codec. The processor is capable of transferring data to the
audio codec in Time-Division Multiplexed (TDM) or Two-Wire Interface
(TWI) mode.
The TWI mode allows the codec to operate with a 96 kHz sample rate but
restricts the output to two channels. TDM mode can operate at a maximum of 48 kHz sample rate but allows simultaneous use of all input and
output channels. When using TWI mode, the TSCLK0 and RSCLK0 pins, as
well as the TFS0 and RFS0 pins of the processor, must be tied together
externally to the processor. This is accomplished with the SW4 DIP switch.
See “Push Button Enable Switch (SW4)” on page 2-12 for more
information.
The AD1836A audio codec’s internal configuration registers are configured using the processor’s PF4 programmable flag pin is used as the select
for this device. For more information on how to configure the multichannel codec, download the datasheet from Analog Devices website,
www.analog.com.
1-10
ADSP-BF561 EZ-KIT Lite Evaluation System Manual
Using EZ-KIT Lite
The AD1836A codec reset is controlled by the processor’s programmable
flag PF15. When PF15 is “0”, the reset is asserted. When PF15 is “1”, the
reset is de-asserted. Note, when PF15 is not driven (configured as input),
the AD1836A reset is asserted due to the pull-down resistor. See “Programmable Flags” on page 2-4 for more information.
programs are included in the EZ-KIT installation direcL Example
tory to demonstrate the AD1836A codec operation.
Video Interface
The board supports video input and output applications. The ADV7179
video encoder provides up to three output channels of analog video, while
the ADV7183A video decoder provides up to three input channels of analog video. The video encoder connects to the Parallel Peripheral
Interface 1 (PPI1), while the video decoder connects to the Parallel
Peripheral Interface 0, ( PPI0). Each PPI interface has an individual clock
that is configured by the SW5 switch settings. See “PPI Clock Select Switch
(SW5)” on page 2-13 for more information.
Both the encoder and the decoder connect to the Parallel Peripheral Interfaces (PPI input clock) of the ADSP-BF561 processor. For additional
information on the video interface hardware, refer to “PPI Interfaces” on
page 2-6.
For the video interface to be operational, the following basic steps must be
performed.
1. Configure the SW2 DIP switch as required by the application. Refer
to “Video Configuration Switch (SW2)” on page 2-10 for details.
2. De-assert the video device’s reset by setting a corresponding programmable flag “High”. Note that PF14 controls the ADV7179
encoder’s reset, while PF13 controls the ADV7183A decoder’s
reset.
ADSP-BF561 EZ-KIT Lite Evaluation System Manual
1-11
Example Programs
3. If using the decoder:
D
D
Enable device by driving programmable flag output PF2 to “0”.
Select PPI0 clock; for details, refer to “PPI Clock Select Switch
(SW5)” on page 2-13.
4. Program internal registers of the video device in use. Both video
encoder and decoder use a 2-wire serial interface to access internal
registers. The PF0 programmable flag functions as a serial clock
(SCL), and PF1 functions as a serial data (SDAT).
5. Program the ADSP-BF561 processor’s PPI interfaces (configuration registers, DMA, and so on).
programs are included in the EZ-KIT installation direcL Example
tory to demonstrate the capabilities of the video interface.
Example Programs
Example programs are provided with the ADSP-BF561 EZ-KIT Lite to
demonstrate various capabilities of the evaluation board. These programs
are installed with the EZ-KIT Lite software and can be found in the
\…\Blackfin\EZ-KITs\ADSP-BF561\Examples subdirectory of the VisualDSP++ installation directory. Please refer to the readme file provided
with each example for more information.
Flash Programmer Utility
The ADSP-BF561 EZ-KIT Lite evaluation system includes a Flash Programmer utility. The utility allows you to program the flash memory on
the EZ-KIT Lite. The Flash Programmer is installed with VisualDSP++.
Once the utility is installed, it is accessible from the Tools pull-down
menu.
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Using EZ-KIT Lite
The Flash Programmer driver is core-specific (core A) and must be loaded
to the core A in order to operate correctly. The Flash Programmer relies
on the user to set the correct core focus. To set up the correct core, select
the core A in the multiprocessor window before opening the Flash Programmer interface.
For more information on the Flash Programmer utility, refer to the online
Help.
Background Telemetry Channel
The ADSP-BF561 USB debug agent supports the Background Telemetry
Channel (BTC), which facilitates data exchange between VisualDSP++
and the processor without interrupting processor execution.
The BTC allows to view a variable as it is updated or changed, all while
the processor continues to execute. For increased performance of the
BTC, including faster reading and writing, please check out our latest line
of processor emulators at
www.analog.com/Analog_Root/productPage/productHome/0,2121,EMULATORS,00.html.
For more information about the Background Telemetry
Channel, see the VisualDSP++ User’s Guide or online Help.
VisualDSP++ Interface
This section provides information on the following parts of the VisualDSP++ graphical user interface:
• “Target Options” on page 1-14
• “Restricted Software Breakpoints” on page 1-17
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1-13
VisualDSP++ Interface
Target Options
Choosing Target Options from the Settings menu opens the Target
Options dialog box (Figure 1-3). Use target options to control certain
aspects of the processor on the ADSP-BF561 EZ-KIT Lite evaluation
system.
Figure 1-3. Target Options Dialog Box
Reset Options
Reset options control how the processor behaves when a reset occurs. The
reset options are described in Table 1-4.
Table 1-4. Reset Options
Option
Description
Core reset
Resets the core when the debugger executes a reset. Note that a core reset of
either core effects both cores as does a system reset.
System reset
Resets the peripherals when the debugger executes a reset.
On Emulator Exit
This target option controls processor behavior when VisualDSP++ relinquishes processor control (for example, when exiting VisualDSP++). The
option is described in Table 1-5.
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Using EZ-KIT Lite
Table 1-5. On Emulator Exit Target Options
Option
Description
On Emulator Exit Determines the state the processor is left in when the board relinquishes
control of the processor:
Reset DSP and Run causes the processor to reset and begin execution from
its reset vector location.
Run from current PC causes the processor to begin running from its current
location.
Stall the DSP resets the processor and then writes a JUMP 0 to the first location in internal memory so the processor is stuck in a tight loop after exiting.
XML File
These read-only fields show the version information for the processor-specific XML file, in the \…\SYSTEM\ADSP-BF561.xml subdirectory of the
VisualDSP++ installation directory, as well as the parser program
(Table 1-6).
Table 1-6. XML File Information
Option
Description
XML File Version
The version of the processor’s XML file.
XML Parser Version
The version of the program that parses the XML file.
Other Options
Table 1-7 describes other available target options.
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1-15
VisualDSP++ Interface
Table 1-7. Miscellaneous Target Options
Option
Description
Verify all writes to target
memory
Validates all memory writes to the processor. After each write, a read
is performed and the values are checked for a matching condition.
Enable this option during initial program development to locate
and fix initial build problems (such as attempting to load data into
non-existent memory).
Clear this option to increase performance while loading executable
files, since VisualDSP++ does not perform the extra reads that are
required to verify each write.
Reset cycle counters on
run
Resets the cycle count registers to zero before a Run command is
issued. Select this option to count the number of cycles executed
between breakpoints in a program.
Use opcode scan method
Enables the debugger to use a highly optimized JTAG scan method.
This provides extremely fast communication between the EZ-KIT
Lite and the processor. In certain circumstances, this causes JTAG
scan failures. Typically, JTAG scan failures occur when using this
method combined with debugging situations that hold off or stall
the core (such as debugging, loading, or viewing external memory).
Clearing this option uses a less optimized JTAG scan method.
Use XML reset values
Uses a section in the processor-specific .XML file located in the
installation’s system folder. The file defines registers that are reset
to certain values; the values are read at startup and subsequently
used to set the registers when a reset is performed through VisualDSP++. Applies to both processors.
Mask interrupts during
step
Disables interrupts while single stepping through code. Applies to
both processors.
Disable breakpoints in
shared memory messages
Suppress a warning message caused by setting a breakpoint in
shared memory. Applies to both processors.
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Using EZ-KIT Lite
Restricted Software Breakpoints
The EZ-KIT Lite development system restricts breakpoint placement
when certain conditions are met. That is, under some conditions, breakpoints cannot be placed effectively. Such conditions depend on bus
architecture, pipeline depth, and ordering of the EZ-KIT Lite and its target processor.
ADSP-BF561 EZ-KIT Lite Evaluation System Manual
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VisualDSP++ Interface
1-18
ADSP-BF561 EZ-KIT Lite Evaluation System Manual
2 EZ-KIT LITE HARDWARE
REFERENCE
This chapter describes the hardware design of the ADSP-BF561 EZ-KIT
Lite board. The following topics are covered.
• “System Architecture” on page 2-2
Describes the configuration of the ADSP-BF561EZ-KIT Lite and
explains how the board components interface with the processor.
• “Jumper and DIP Switch Settings” on page 2-10
Shows the location and describes the function of the configuration
jumpers and switches.
• “LEDs and Push Buttons” on page 2-14
Shows the location and describes the function of the LEDs and
push buttons.
• “Connectors” on page 2-17
Shows the location and gives the part number for all of the connectors on the board. Also, the manufacturer and part number
information is given for the mating parts.
ADSP-BF561 EZ-KIT Lite Evaluation System Manual
2-1
System Architecture
System Architecture
This section describes the processor’s configuration on the EZ-KIT Lite
board.
Figure 2-1. System Architecture
The EZ-KIT Lite has been designed to demonstrate the capabilities of the
ADSP-BF561 Blackfin processor. The processor has IO voltage of 3.3V.
The core voltage and the core clock rate can be set on the fly by the processor. The input clock is 30 MHz.
2-2
ADSP-BF561 EZ-KIT Lite Evaluation System Manual
EZ-KIT Lite Hardware Reference
External Bus Interface Unit
The External Bus Interface Unit (EBIU) connects an external memory to
the ADSP-BF561 processor. It includes a 32-bit wide data bus, an address
bus (A25–A2), and a control bus. All 8-bit, 16-bit, and 32-bit accesses are
supported. On the EZ-KIT Lite board, the EBI unit is connected to
SDRAM and flash memory. For more information on using the external
memory see “External Memory” on page 1-6.
All of the address, data, and control signals are available externally via the
extender connectors (J3–J1). The pinout of these connectors can be found
in Appendix B, “Schematics” on page B-1.
SPORT0 Audio Interface
The SPORT0 interface connects to the AD1836A audio codec, the SPORT
connector (P3), and the expansion interface. The AD1836A codec uses
both the primary and secondary data transmit and receive pins to input
and output data from the audio input and outputs.
The pinout of the SPORT connector and the expansion interface connectors can be found in Appendix B, “Schematics” on page B-1.
SPI Interface
The processor’s Serial Peripheral Interconnect (SPI) interface connects to
the AD1836A audio codec and the expansion interface. The SPI connection to the AD1836A is used to access the control registers of the device.
The PF4 flag of the processor acts as the devices select for the SPI port.
The SPI signals are available on the expansion interface. The pinout for
the expansion interface can be found in Appendix B, “Schematics” on
page B-1.
ADSP-BF561 EZ-KIT Lite Evaluation System Manual
2-3
System Architecture
Programmable Flags
The processor has 48 programmable flag pins (PFs). Many of the flags
have a multiple functionality, depending on the processor’s setup.
Table 2-1 shows how the programmable flag pins are used on the EZ-KIT
Lite.
Table 2-1. Programmable Flag Connections
Processor
PF Pin
Processor Function
EZ-KIT Function
PF0
SPI Select S, Timer 0
Serial clock for programming ADV7179 video encoder
and ADV7183A video decoder.
PF1
SPI Select 1, Timer 1
Serial data for programming ADV7179 video encoder and
ADV7183A video decoder.
PF2
SPI Select 2, Timer 2
ADV7183A video decoder’s ~OE.
PF3
SPI Select 3, Timer 3
ADV7183A Field pin. See “Video Configuration Switch
(SW2)” on page 2-10.
PF4
SPI Select 4, Timer 4
AD1836A audio codec’s SPI Select.
PF5
SPI Select 5, Timer 5
Push Button ( SW6). See “LEDs and Push Buttons” on
page 1-9 and “Push Button Enable Switch (SW4)” on
page 2-12 for information on how to disable the push
button.
PF6
SPI Select 6, Timer 6
Push Button ( SW7). See “LEDs and Push Buttons” on
page 1-9 and “Push Button Enable Switch (SW4)” on
page 2-12 for information on how to disable the push
button.
PF7
SPI Select 7, Timer 7
Push Button ( SW8). See “LEDs and Push Buttons” on
page 1-9 and “Push Button Enable Switch (SW4)” on
page 2-12 for information on how to disable the push
button.
PF8
2-4
Push Button (SW9). See “LEDs and Push Buttons” on
page 1-9 and “Push Button Enable Switch (SW4)” on
page 2-12 for information on how to disable the push
button.
ADSP-BF561 EZ-KIT Lite Evaluation System Manual
EZ-KIT Lite Hardware Reference
Table 2-1. Programmable Flag Connections (Cont’d)
Processor
PF Pin
Processor Function
EZ-KIT Function
PF9–PF12
Not used
PF13
ADV7183A video decoder’s reset
PF14
ADV7179 video encoder’s reset
PF15
AD1836 codec’s reset
PF16
Sport 0 Transmit Frame Sync
PF17
Sport 0 Transmit Data Secondary
PF18
Sport 0 Transmit Data Primary
PF19
Sport 0 Receive Frame Sync
PF20
Sport 0 Receive Data Secondary
PF21
Sport 1 Transmit Frame
PF22
Sport 1 Transmit Data Secondary
PF23
Sport 1 Transmit Data Primary
PF24
Sport 1 Receive Frame Sync
PF25
Sport 1 Receive Data Secondary
PF26
UART Transmit
PF27
UART Receive
PF28
Sport 0 Receive Serial Clock
PF29
Sport 0 Transmit Serial Clock
PF30
Sport 1 Receive Serial Clock
PF31
Sport 1 Transmit Serial Clock
PF39–32
PPI1
data 15–8
LED20–13
PF47–40
PPI0
data 15–8
LED12–5
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2-5
System Architecture
PPI Interfaces
The ADSP-BF561 processor employs two independent Parallel Peripheral
Interfaces (PPIs), PPI0 and PPI1. Each PPI interface is a half-duplex,
bi-directional bus consisting of 16 bits of data, a dedicated input clock,
and synchronization signals. The ADSP-BF561 EZ-KIT Lite board utilizes the PPI interfaces for video input and video output.
The PPI0 interface is configured to input video data from the ADV7183A
video decoder device: bits 7–0 connect to the video decoder’s data outputs.
The PPI1 interface is configured to output video data to the ADV7179
video encoder device: bits 7–0 connect to the video encoder’s data inputs.
Each PPI interface has a dedicated clock input configured independently
by the SW5 switch. The clock source can be one of the following: 27 MHz
crystal oscillator, ADV7183A video decoder’s clock output, or external
clock from the expansion interface. See “PPI Clock Select Switch (SW5)”
on page 2-13 for more information about the switch.
The SW2 switch allows flexible connectivity between dedicated synchronization IOs (SYNC1 and SYNC2 of each PPI interface) and the encoder’s and
decoder’s horizontal and vertical synchronization pins. See “Video Configuration Switch (SW2)” on page 2-10 for more information about the
switch. For a detailed description of the ADSP-BF561 processor’s PPI
interfaces, refer to the ADSP-BF561 Blackfin Processor Hardware Reference.
Table 2-2 describes the PPI pins and their use on the EZ-KIT Lite board.
Table 2-2. PPI Connections
Processor PPI
Pin
EZ-KIT Function
PPI0
bits 7–0
ADV7183A data outputs P15–8
PPI1
bits 7–0
ADV7179 data inputs P7–0
PPI0 SYNC1
2-6
Other PRocessor
Function
Timer 8
ADV7179 HSYNC. For more information, see “Video
Configuration Switch (SW2)” on page 2-10.
ADSP-BF561 EZ-KIT Lite Evaluation System Manual
EZ-KIT Lite Hardware Reference
Table 2-2. PPI Connections (Cont’d)
Processor PPI
Pin
Other PRocessor
Function
EZ-KIT Function
PPI0 SYNC2
Timer 9
ADV7179 VSYNC. For more information, see “Video
Configuration Switch (SW2)” on page 2-10.
PPI0
Clock
A choice of ADV7183A output clock, a local 27 MHz
oscillator, or an external clock from
ADSP-BF533/BF561 EZ-KIT Extender 1 board.
PPI1 SYNC1
Timer 10
ADV7183A HSYNC. For more information, see
“Video Configuration Switch (SW2)” on page 2-10.
PPI1 SYNC2
Timer 11
ADV7183A VSYNC. For more information, see “Video
Configuration Switch (SW2)” on page 2-10.
PPI1
Clock
A choice of ADV7183A output clock, a local 27 MHz
oscillator, or an external clock from
ADSP-BF53x/BF561 EZ-Extender 1.
Video Output (PPI1)
The PPI1 interface is configured as output and connects to the on-board
video encoder device, ADV7179. The ADV7179 encoder generates three
analog video channels on DAC A, DAC B, and DAC C. The PPI1 bits 7–0 connect to P7–0 of the encoder’s pixel inputs. The encoder’s input clock is
fixed and comes from an on-board 27 MHz oscillator.
The encoder’s synchronization signals, HSYNC and VSYNC, can be configured as inputs or outputs. Video Blanking control signal is at level “1”.
The HSYNC and VSYNC signals can connect to the ADSP-BF561 processor’s
PPI1 interface SYNC1 and SYNC2 via the SW2 switch, as described in “Video
Configuration Switch (SW2)” on page 2-10.
ADSP-BF561 EZ-KIT Lite Evaluation System Manual
2-7
System Architecture
Video Input (PPI0)
The PPI0 interface is configured as input and connect to the on-board
video decoder device, ADV7183A. The ADV7183A decoder receives three
analog video channels on AIN1, AIN4, and AIN5 input. The decoder’s pixel
data outputs P15–8 drive the PPI0 inputs 8–0. The decoder’s 27 MHz pixel
clock output can be selected to drive any of the PPI clocks, as shown in
Table 2-7 on page 2-13.
Synchronization outputs of the decoder, HS/HACTIVE, VS/VACTIVE, and
FIELD can connect to the processor’s PPI1 SYNC1, SYNC2, and PF3 flag via
the SW2 DIP switch, as described in “Video Configuration Switch (SW2)”
on page 2-10.
UART Port
The processor’s Universal Asynchronous Receiver/Transmitter (UART)
port connects to the ADM3202 RS232 line driver as well as to the expansion interface. The RS232 line driver is attached to the DB9 male
connector, allowing you to interface with a PC or other serial device.
Expansion Interface
The expansion interface consists of the three 90-pin connectors, J3–1.
Table 2-3 shows the interfaces each connector provides. For the exact
pinout of these connectors, refer to Appendix B, “Schematics” on page
B-1. The mechanical dimensions of the connectors can be obtained from
Technical or Customer Support.
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EZ-KIT Lite Hardware Reference
Table 2-3. Connector Interfaces
Connector Interfaces
J1
5V, G ND, Address, Data, PPI0 3–0, PF15–6, PF4
J2
3.3V, GND, SPI, NMI, PPI0 SYNC3–1, SPORT0, SPORT1, PF15–0, EBUI control
signals
J3
5V, 3.3V, GND, UART, PPI1 15–0, Reset, Video control signals
Limits to the current and to the interface speed must be taken into consideration when you use the expansion interface. The maximum current limit
is dependent on the capabilities of the used regulator. Additional circuitry
can also add extra loading to signals, decreasing their maximum effective
speed.
Devices does not support and is not responsible for the
[ Analog
effects of additional circuitry.
JTAG Emulation Port
The JTAG emulation port allows an emulator to access the processor’s
internal and external memory through a 6-pin interface. The JTAG emulation port of the processor also connects to the USB debugging interface.
When an emulator connects to the board at P4, the USB debugging interface is disabled. See “JTAG (P4)” on page 2-20 for more information
about the JTAG connector.
To learn more about available emulators, contact Analog Devices (see
“Product Information”).
ADSP-BF561 EZ-KIT Lite Evaluation System Manual
2-9
Jumper and DIP Switch Settings
Jumper and DIP Switch Settings
This section describes the operation of the jumpers and DIP switches. The
jumper and DIP switch locations are shown in Figure 2-2.
Figure 2-2. DIP Switch Locations
Video Configuration Switch (SW2)
The video configuration switch (SW2) controls how some video signals
from the ADV7183A video decoder and ADV7179 video encoder are
routed to the processor’s PPIs. The switch also determines if the PF2 pin
controls the ~OE signal of the ADV7183A video decoder outputs.
Table 2-4 shows which processor’s signals are connected to the encoder
and decoder when in the “ON” position.
2-10
ADSP-BF561 EZ-KIT Lite Evaluation System Manual
EZ-KIT Lite Hardware Reference
Table 2-4. Video Configuration Switch (SW2)
Switch Position (Default)
Processor Signal
Video Signal
1 (OFF)
PPI1 SYNC1
ADV7179
2 (OFF)
PPI0 SYNC1
ADV7183A
3 (OFF)
PPI1 SYNC2
ADV7183A
4 (OFF)
PPI1 SYNC2
ADV7179
5 (OFF)
PF3 (FIELD)
ADV7183A
6 (ON)
PF2
ADV7183A
Positions 1 thorough 5 of SW2 determine how and if the SYNC1, SYNC2, and
FIELD control signals of the PPI0 and PPI1 interfaces are routed to the processor’s PPIs. In standard configuration of the encoder and decoder, this is
not necessary because the processor is capable of reading the embedded
control information, which is in the data stream.
Position 6 of SW2 determines whether PF2 connects to the ~OE signal of the
ADV7183A. When the switch is “OFF”, PF2 can be used for other operations, and the decoder output enable is held “HIGH” with a pull-up resistor.
Boot Mode Switch (SW3)
The SW3 switch positions 1 and 2 set the ADSP-BF561 processor’s boot
mode as described in Table 2-5. Position 3 sets the processor’s PLL on
boot. When SW3 position 3 is “ON”, the PLL is in bypass.
Table 2-5. Boot Mode Select Switch (SW3)
Position 1 BMODE0
Position 2 BMODE1
Boot Mode
ON
ON
Reserved
ON
OFF
Flash memory
ADSP-BF561 EZ-KIT Lite Evaluation System Manual
2-11
Jumper and DIP Switch Settings
Table 2-5. Boot Mode Select Switch (SW3) (Cont’d)
Position 1 BMODE0
Position 2 BMODE1
Boot Mode
OFF
ON
8-bit SPI PROM
OFF
OFF
16-bit SPI PROM
Push Button Enable Switch (SW4)
The push button enable switch (SW4) positions 1 through 4 allow to disconnect the drivers associated with the push buttons from the PF pins of
the processor. Positions 5 and 6 connect the transmit and receive frame
syncs and clocks of SPORT0. This is important when the AD1836A video
decoder and the processor are communicating in Two-Wire Interface
(TWI) mode. Table 2-6 shows which PF is driven when the switch is in
the “ON” position.
Table 2-6. Push Button Enable Switch (SW4)
Switch Position
Default Setting
Pin #
Signal (Side 1)
Pin #
Signal (Side 2)
1
ON
1
SW6
12
PF5
2
ON
2
SW7
11
PF6
3
ON
3
SW8
10
PF7
4
ON
4
SW9
9
PF8
5
OFF
5
TFS0
8
RFS0
6
OFF
6
RSCLK0
7
TSCLK0
2-12
ADSP-BF561 EZ-KIT Lite Evaluation System Manual
EZ-KIT Lite Hardware Reference
PPI Clock Select Switch (SW5)
The SW5 switch controls a clock selection of PPI interfaces, as described in
Table 2-7 and Table 2-8.
Table 2-7. PPICLK1 Clock Source Setup
SW5 Position 1
PPI0_CKSEL0
SW5 Position 2
PPI0_CKSEL1
PPICLK1 Source
ON
ON
27 MHz Oscillator (default)
OFF
ON
ADV7183 Clock Out
X
OFF
Expansion Interface
Table 2-8. PPICLK2 Clock Source Setup
SW5 Position 3
PPI1_CKSEL0
SW5 Position 4
PPI1_CKSEL1
PPICLK2 Source
ON
ON
27 MHz Oscillator (default)
OFF
ON
ADV7183 Clock Out
X
OFF
Expansion Interface
Test DIP Switches (SW10 and SW11)
Two DIP switches (SW10 and SW11) are located on the bottom of the
board. The switches are used only for testing and should be in the “OFF”
position.
ADSP-BF561 EZ-KIT Lite Evaluation System Manual
2-13
LEDs and Push Buttons
LEDs and Push Buttons
This section describes the functionality of the LEDs and push buttons.
Figure 2-3 shows the locations of the LEDs and push buttons on the
board.
Figure 2-3. LED and Push Button Locations
Reset Push Button (SW1)
The RESET push button resets all of the ICs on the board. One exception is
the USB interface chip (U34). The chip is not being reset when the push
button is pressed after the USB cable has been plugged in and communication with the PC has been initialized correctly. Once communication is
initialized, the only way to reset the USB is by powering down the board.
2-14
ADSP-BF561 EZ-KIT Lite Evaluation System Manual
EZ-KIT Lite Hardware Reference
Programmable Flag Push Buttons (SW9–6)
Four push buttons, SW9–6, are provided for general-purpose user input.
The buttons connect to the processor’s programmable flag pins PF8–5.
The push buttons are active “HIGH” and, when pressed, send a High (1) to
the processor. Refer to “LEDs and Push Buttons” on page 1-9 for more
information on how to use the PFs when programming the processor. The
push button enable switch (SW4) is capable of disconnecting the push buttons from the PF (refer to “Push Button Enable Switch (SW4)” on
page 2-12). The programmable flag signals and their corresponding
switches are shown in Table 2-9.
Table 2-9. Programmable Flag Switches
Processor Programmable Flag Pin
Push Button Reference Designator
PF5
SW6
PF6
SW7
PF7
SW8
PF8
SW9
Power LED (J7)
When J7 is lit (green), it indicates that power is being properly supplied to
the board.
Reset LEDs (LED2 and LED3)
When LED2 is lit, it indicates that the master reset of all the major ICs is
active. When LED3 is lit, the USB interface chip (U34) is being reset. The
USB chips only reset on power-up, or if USB communication has not
been initialized.
ADSP-BF561 EZ-KIT Lite Evaluation System Manual
2-15
LEDs and Push Buttons
USB Monitor LED (LED4)
The USB monitor LED (LED4) indicates that USB communication has
been initialized successfully and you may connect to the processor using a
VisualDSP++ EZ-KIT Lite session. This should take approximately 15
seconds. If the LED does not light, try cycling power on the board and/or
reinstalling the USB driver.
VisualDSP++ is actively communicating with the EZ-KIT
L When
Lite target board, the LED can flicker, indicating communications
handshake.
User LEDs (LED12–5, LED20–13)
Sixteen LEDs are connected to the ADSP-BF561 processor’s programmable flags. Eight LEDs labeled LED5 through LED12 are controlled by
programmable flags PF40 through PF47 (equivalent to PPI0 D15–8). Eight
LEDs labeled LED13 through LED20 are controlled by programmable flags
PF32 through PF39 (equivalent to PPI1 D15–8). To learn how to use the
flash memory when programming the LEDs, refer to “LEDs and Push
Buttons” on page 1-9.
Table 2-10. User LEDs
LED Reference Designator Flash Port Name
LED Reference Designator Flash Port Name
LED5
PB40
LED13
PB32
LED6
PB41
LED14
PB33
LED7
PB42
LED15
PB34
LED8
PB43
LED16
PB35
LED9
PB44
LED17
PB36
LED10
PB45
LED18
PB37
LED11
PB46
LED19
PB38
LED12
PB47
LED20
PB39
2-16
ADSP-BF561 EZ-KIT Lite Evaluation System Manual
EZ-KIT Lite Hardware Reference
Connectors
This section describes the connector functionality and provides information about mating connectors. The locations of the connectors are shown
in Figure 2-4.
Figure 2-4. Connector Locations
Expansion Interface (J3–1)
Three board-to-board connector footprints provide signals for most of the
processor’s peripheral interfaces. The connectors are located at the bottom
of the board. For more information about the expansion interface, see
on page 2-8. For the availability and pricing of the J1, J2, and J3 connectors, contact Samtec.
ADSP-BF561 EZ-KIT Lite Evaluation System Manual
2-17
Connectors
Part Description
Manufacturer
Part Number
90 Position 0.05" Spacing, SMT
(J1, J2, J3)
Samtec
SFC-145-T2-F-D-A
Mating Connector
90 Position 0.05” Spacing
(Through Hole)
Samtec
TFM-145-x1 Series
90 Position 0.05” Spacing
(Surface Mount)
Samtec
TFM-145-x2 Series
90 Position 0.05” Spacing
(Low Cost)
Samtec
TFC-145 Series
Audio (J4 and J5)
Part Description
Manufacturer
Part Number
2x2 RCA Jacks (J4)
SWITCHCRAFT
PJRAS2X2S01
3x2 RCA Jacks (J5)
SWITCHCRAFT
PJRAS3X2S01
Mating Connector
Two channel RCA interconnect cable Monster Cable
BI100-1M
Video (J6)
Part Description
Manufacturer
Part Number
3x2 RCA Jacks (J6)
SWITCHCRAFT
PJRAS3X2S01
Power (J7)
The power connector provides all of the power necessary to operate the
EZ-KIT Lite board. The power connector supplies DC power to the
board. The following table shows the power connector pinout.
2-18
ADSP-BF561 EZ-KIT Lite Evaluation System Manual
EZ-KIT Lite Hardware Reference
Part Description
Manufacturer
Part Number
2.5 mm Power Jack (J7)
SWITCHCRAFT
RAPC712
Digi-Key
SC1152-ND
Mating Power Supply (shipped with EZ-KIT Lite)
7.5V Power Supply
GlobTek
TR9CC2000LCP-Y
The power connector supplies DC power to the EZ-KIT Lite board.
Table 2-11 shows the power supply specifications.
Table 2-11. Power Supply Specification
Terminal
Connection
Center pin
+7.5 VDC@3Amps
Outer Ring
GND
USB (J8)
The USB connector is a standard Type B USB receptacle.
Part Description
Manufacturer
Part Number
Type B USB receptacle (J8)
Mill-Max
897-30-004-90-000
Digi-Key
ED90003-ND
Mating Assembly
USB cable (provided with kit)
Assmann
AK672-5
Digi-Key
AK672-5ND
ADSP-BF561 EZ-KIT Lite Evaluation System Manual
2-19
Connectors
RS232 (P2)
The RS232-compatible connector is described in Table 2-12.
Table 2-12. RS232 Connector
Part Description
Manufacturer
Part Number
DB9, Male, Right Angle (P2)
Digi-Key
A2096-ND
Mating Assembly
2m Female to Female cable
Digi-Key
AE1016-ND
SPORT0 (P3)
The SPORT0 connector is linked to a 20-pin connector. The connector’s
pinout can be found in “Schematics” on page B-1. For pricing and availability of the connectors, contact AMP.
Part Description
Manufacturer
Part Number
20-position AMPMODU system 50
receptacle (P3)
AMP
104069-1
Mating Connectors
20-position ribbon cable connector
AMP
111196-4
20-position AMPMODU system 20
connector
AMP
2-487937-0
20-position AMPMODU system 20
connector (w/o lock)
AMP
2-487938-0
Flexible film contacts (20 per connector)
AMP
487547-1
JTAG (P4)
The JTAG header is the connecting point for a JTAG in-circuit emulator
2-20
ADSP-BF561 EZ-KIT Lite Evaluation System Manual
EZ-KIT Lite Hardware Reference
pod. When an emulator is connected to the JTAG header, the USB debug
interface is disabled.
3 is missing to provide keying. Pin 3 in the mating connector
L Pin
should have a plug.
using an emulator with the EZ-KIT Lite board, follow the
L When
connection instructions provided with the emulator.
ADSP-BF561 EZ-KIT Lite Evaluation System Manual
2-21
Connectors
2-22
ADSP-BF561 EZ-KIT Lite Evaluation System Manual
A BILL OF MATERIALS
The bill of materials corresponds to the board schematics on page B-1.
Please check the latest schematics on the Analog Devices website,
http://www.analog.com/Processors/Processors/DevelopmentTools/tec
hnicalLibrary/manuals/DevToolsIndex.html#Evaluation%20Kit%20Manuals.
ADSP-BF561 EZ-KIT Lite Evaluation System Manual
A-1
A-2
ADSP-BF561 EZ-KIT Lite Evaluation System Manual
U35
10MHZ SMT OSC003 3V
74LVC14A SOIC14
U47
HEX-INVER-SCHMITT-TRIGGER
IDT74FCT3244APY SSOP20
3.3V-OCTAL-BUFFER
1
2
3
MMBT4401 SOT-23
NPN TRANSISTOR 200MA
ADP3331ART SOT23-6
ADJ 200MA REGULATOR
CY7C1019BV33-15VC SOJ32 128K
X 8 SRAM
12.0MHZ THR OSC006
CRYSTAL
DSM2150F5V TQFP80
FLASH-ICP
SN74AHC1G00 SOT23-5
SINGLE-2-INPUT-NAND
5
6
7
8
9
10
U28,U34,U39,U42
U44
Y1
U38
VR7
Q1
CY7C64603-128 PQFP128
U45
USB-TX/RX MICROCONTROLLER
4
U13,U30
Reference Designator
Ref.# Description
TI
ST MICRO
DIG01
CYPRESS
ANALOG
DEVICES
FAIRCHILD
CYPRESS
IDT
TI
RALTRON
Manufacturer
SN74AHC1G00DBVR
DSM2150F5V
300-6027-ND
CY7C1019BV33-12VC
ADP3331ART
MMBT4401
CY7C64603-128NC
IDT74FCT3244APY
74LVC14AD
C04310-10.00
Part Number
U16
12.288MHZ SMT OSC003
TS201/21262
LT1765 SO-8
ADJUSTABLE-3A-SWITCH-REG
GS74116 TSOP44
256Kx16 SRAM
NDS8434A SO-P-MOSFET
MT48LC16M16A2TG-75 TSOP54
256MB-SDRAM
27MHZ SMT OSC003
XC2S150E FT256
XILINX-SPARTANIIE-FPGA
IDT2305-1DC SOIC8
1 TO 5 ZERO DELAY CLK BUF
SN74LVC1G32 SOT23-5
SINGLE-2 INPUT OR GATE
M29W64OD TSOP48
64MBIT 8/16-BIT FLASH MEM
30.0000MHZ SMT OSC003
OSCILLATOR
11
12
13
14
15
16
17
18
19
ADSP-BF561 EZ-KIT Lite Evaluation System Manual
20
21
U14
U27
U10
U19-20
U41
U17
U32-33
U29
U40,U43
VR5
Reference Designator
Ref.# Description
GS74116ATP-10
LT1765ES8
SG-8002CA-PCC-ND
Part Number
XC2S150E-7FT256C
SG-8002CA MP
MT48LC16M16A2TG-75
EPSON
ST MICRO
TI
SG-8002CA30.000M
M29W640DT 90N1
SN74LVC1G32DBVR
INTEGRATED SYS ICS9112AM-16
XILINX
EPSON
MICRON
FAIRCHILD SEMI NDS8434A
GSI TECHNOLOGY
LINEAR TECH
DIG01
Manufacturer
Bill Of Materials
A-3
A-4
ADSP-BF561 EZ-KIT Lite Evaluation System Manual
U31
BF561 24LC32 “U31”
SEE 1000220
1000pF 50V 5% 1206 CERM
2200pF 50V 5% 1206 NPO
ADM708SAR SOIC8
VOLTAGE-SUPERVISOR
ADP3338AKC-33 SOT-223
3.3V-1.0AMP REGULATOR
ADP3339AKC-5 SOT-223
5V-1.5A REGULATOR
ADP3339AKC-33 SOT-223
3.3V 1.5A REGULATOR
ADP3336ARM MSOP8
ADJ 500MA REGULATOR
10MA AD1580BRT SOT23D
1.2V-SHUNT-REF
ADG752BRT SOT23-6
CMOS-SPDT-SWITCH
AD8061ART SOT23-5
300MHZ-AMP
22
23
24
25
26
27
28
29
30
31
32
U1-3
U22-23,U25-26
D1
VR2,VR4
VR6
VR1
VR3
U46
C46,C76-81
C153,C160
Reference Designator
Ref.# Description
ANALOG
DEVICES
ANALOG
DEVICES
ANALOG
DEVICES
ANALOG
DEVICES
ANALOG
DEVICES
ANALOG
DEVICES
ANALOG
DEVICES
ANALOG
DEVICES
AVX
AVX
MICROCHIP
Manufacturer
AD8061ART-REEL
ADG752BRT
AD1580BRT
ADP3336ARM-REEL
ADP3339AKC-3.3-RL
ADP3339AKC-5-REEL
ADP3338AKC-3.3
ADM708SAR
12065A222JAT050
12065A102JAT2A
24LC32A-I/SN “U31”
Part Number
ADSP-BF561 EZ-KIT Lite Evaluation System Manual
AD1836AAS MQFP52
MULTI-CHANNEL-96KHZ-CODEC
ADSP-BF561SKBC-600 256
DUEL BLACKFIN DSP
ADV7179 LFCSP40
VIDEO ENCODER
ADV7183AKST LQFP80
RUBBER FEET BLACK
PWR 2.5MM_JACK CON005 RA
USB 4PIN CON009
RCA 2X2 CON013
.05 10X2 CON014
35
36
37
38
39
40
41
42
43
44
AD8606AR SOIC8 OPAMP
34
SPST-MOMENTARY SWT013 6MM
RA
USB
U21
ADM3202ARN SOIC16
RS232-TXRX
33
SW1,SW6-9
P3
J4
J8
J7
MH1-5
U4
U8
U48
U15
U5-7,U9,U11-12,U1,U24
Reference Designator
Ref.# Description
PANASONIC
AMP
SWITCHCRAFT
MILL-MAX
SWITCHCRAFT
MOUSER
ANALOG
DEVICES
ANALOG
DEVICES
ANALOG
DEVICES
ANALOG
DEVICES
ANALOG
DEVICES
ANALOG
DEVICES
Manufacturer
EVQ-PAD04M
104069-1
PJRAS2X2S01
897-30-004-90-000000
SC1152-ND12
517-SJ-5018BK
ADV7183AKST
ADV7179KCP
ADSP-BF561SKBC-600
AD1836AAS
AD8606AR
ADM3202ARN
Part Number
Bill Of Materials
A-5
A-6
ADSP-BF561 EZ-KIT Lite Evaluation System Manual
DIP4 SWT018
4PIN-SMT-SWT
0.00 1/8W 5% 1206
AMBER-SMT LED001
GULL-WING
330pF 50V 5% 805 NPO
49
50
51
52
DIP6 SWT017
47
RCA 3X2 CON024 RA
0.05 45X2 CON019
SMT SOCKET
46
48
J7
DIP12 SWT014
45
C82,C84,C86,C92-100
LED4-20
R43-44, R55, R71-73, R80,
R90, R133,R159, R163,
R223-225, R228, R247
SW3,SW5,SW11
J5-6
SW2,SW4,SW10
J1-3
Reference Designator
Ref.# Description
AVX
PANASONIC
YAGEO
DIG01
SWITCHCRAFT
DIG01
SAMTEC
DIGI-KEY
Manufacturer
08055A331JAT
LN1461C-TR
0.0ECT-ND
CKN1363-ND
PJRAS3X2S01
CKN1364-ND
SFC-145-T2-F-D-A
CKN3063-ND
Part Number
0.001uF 50V 5% 805
10uF 16V 10% C TANT
56
57
NPO
0.1uF 50V 10% 805
CERM
55
ADSP-BF561 EZ-KIT Lite Evaluation System Manual
AVX
CT17-18,CT20-21, CT23-24 SPRAGUE
C23,C25,C33,C36,
C38-40,C67-68,
C1-2, C4, C12, C19-20, C22, AVX
C27,
C29-30, C35, C37, C48,
C51-60, C65-66, C71, C73,
C83, C85, C87-91, C102,
C109-111, C115, C122-124,
C126, C131-132, C135,
C139, C145, C147-148,
C151-152, C155, C158-159,
C164,C167,C171-172,C175,
C177-179, C183-184, C189,
C191, C233, C236, C241
AVX
0.22uF 25V 10% 805
CERM
54
C104, C106-108, C125,
C129, C143, C162
C3, C5, C28, C41, C49,
AVX
C69-70, C74-75,
C101,C112-114,C127,C134,
C136-138, C140-141, C146,
C149-150, C154, C156-157,
C165-166, C168, C173-174,
C176, C180-182, C185-188,
C190, C200-203, C249, C256
0.01uF 100V 10% 805 CERM
53
Manufacturer
Reference Designator
Ref.# Description
293D106X9016C2T
08055A102JAT2A
08055C104KAT
08053C224FAT
08051C103KAT2A
Part Number
Bill Of Materials
A-7
A-8
ADSP-BF561 EZ-KIT Lite Evaluation System Manual
33 100MW 5% 805
4.7K 100MW 5% 805
1M 100MW 5% 805
1.5K 100MW 5% 805
1.2K 1/8W 5% 1206
49.9K 1/8W 1% 1206
2.21K 1/8W 1% 1206
100pF 100V 5% 1206 NPO
10uF 16V 10% B TANT
100 100MW 5% 805
59
60
61
62
63
64
65
66
67
68
AVX
AVX
DALE
AVX
AVX
AVX
AVX
R242-245
CT1-4,CT15-16
AVX
AVX
C6-11,C26,C34, C61-63,C72 AVX
R88-89
R108-113
R23
R1,R94
R76,R209
R86
R39,R41,R59-61,
R165-166,R172
R2, R7, R11-12, R14, R24,
AVX
R42, R45-47, R52, R57, R78,
R85, R91, R96-98, R131,
R143, R158, R160-162,
R167-170, R174-177, R179,
R181-183, R185, R189-190,
R196, R198-203, R205-206,
R208, R212, R221-222, R229,
R239-241, R246, R248-251
10K 100MW 5% 805
58
Manufacturer
Reference Designator
Ref.# Description
CR21-101J-T
TAJB106K016R
12061A101JAT2A
CR32-2211F-T
CR32-4992F-T
CRCW1206-122JRT1
CR21-1501F-T
CR21-1004F-T
CR21-4701F-T
CR21-330JTR
CR21-103J-T
Part Number
2A S2A_RECT DO-214AA
SILICON RECTIFIER
600 100MHZ 500MA 1206
0.70 BEAD
237 1/8W 1% 1206
750K 1/8W 1% 1206
5.76K 1/8W 1% 1206
11.0K 1/8W 1% 1206
120PF 50V 5% 1206
75 1/8W 5% 1206
30PF 100V 5% 1206
68UF 6.3V 20% D TANT
71
72
73
74
75
76
77
78
79
80
NPO
600 100MHZ 200MA 603
0.50 BEAD
70
DALE/VISHAY
AVX
DIGI-KEY
GENERALSEMI
MURATA
AVX
Manufacturer
DALE
ADSP-BF561 EZ-KIT Lite Evaluation System Manual
CT22
C221-222
PANASONIC
AVX
R4-6,R100-102,R104-105,R1 PHILIPS
07,R114, R134-135
C103,C105,C128,
PHILLIPS
C130,C142,C144, C161,C163
R144-149
R8,R15-16,R40, R49-50,R58, PHYCOMP
R132,R156,R164,R173
R25-26,R53-54
FER2-4,FER6-12,FER14-16
D2-3,D7
FER18-21
C13-18
220pf 50V 10% 1206
69
NPO
Reference Designator
Ref.# Description
ECS-TOJD686R
12061A300JAT2A
9C12063A75R0JLHFT
1206CG121J9B200
CRCW12061102FRT1
9C12063A5761FKHFT
CRCW12067503FRT1
CR32-2370F-T
240-1019-1-ND
S2A
BLM11A601SPT
12061A221JAT2A
Part Number
Bill Of Materials
A-9
A-10
ADSP-BF561 EZ-KIT Lite Evaluation System Manual
698K 1/8W 1% 805
680PF 50V 1% 805
10UF 25V +80-20% 1210
Y5V
2.74K 1/8W 1% 1206
5.49K 1/8W 1% 1206
3.32K 1/8W 1% 1206
1.65K 1/8W 1% 1206
10UF 16V 20% CAP002
ELEC
2A SL22 DO-214AA
SCHOTTKY
53.6K 1/10W 1% 805
332K 1/10W 1% 805
10UH 47 +/-20 IND001
82
83
84
85
86
87
88
89
90
91
92
93
NPO
R211
340K 1/8W 1% 805
81
L11
R207
R75
D6
CT5-14
R28-29,R32-33,R36-37
R137-142
R17-22,R27,R30-31,
R34-35,R38
R150-155
C31,C47,C50
C116-121
R210
Reference Designator
Ref.# Description
DIG01
PHILIPS
PHILIPS
GENERAL SEMI
DIG01
PANASONIC
DALE
PANASONIC
DALE
MURATA
AVX
DALE
DALE
Manufacturer
445-1202-2-ND
9C08052A3323FKRT/R
9C08052A5362FKRT/R
SL22
PCE3062TR-ND
ERJ-8ENF1651V
CRCW12063321FRT1
ERJ-8ENF5491V
CRCW12062741FRT1
GRM235Y.5V106Z025
08055A681FAT2A
CRCW0805-6983FT
CRCW0805-3403FT
Part Number
RN3
10K 31MW 5% RNET8
10K 50MW 5% BGA36
0.00 100MW 5% 805
190 100MHZ 5A FER002
3.32K 100MW 1% 805
22 1/10W 5% 805
0.68UH 0.72 10% 805
82NF 50V 5% 805 X7R
1A ZHCS1000 SOT23D
SCHOTTKY
2.2UH 0.63 10% 805
0.47UF 16V 10% 805
1UF 10V 10% 805
10UF 6.3V 10% 805
94
95
96
97
98
99
100
101
102
103
104
105
106
CTS
CTS
Manufacturer
DIG01
MURATA
ADSP-BF561 EZ-KIT Lite Evaluation System Manual
AVX
AVX
MURATA
ZETEX
AVX
MURATA
C208,C217,C219, C243,C255 AVX
C21,C24,C32,C44-45
C218,C230
L5,L7,L9
D5
C64
L1-4,L6,L8
R67-68,R187-188, R204,R226 VISHAY/DALE
R194-195, R227
FER5
R66,R74,R77,R79,R81,R83-8 VISHAY
4,R87,R99, R103,R106,R178,
R192, R252
RN2
Reference Designator
Ref.# Description
080560106KAT2A
0805ZC105KAT2A
0805YC474KAT2A
LQG21N2R2K10
ZHCS1000
08055C823JAT2A
LQG21NR68K10T1
CRCW0805220JRT1
P3.32KCCTR-ND
DLW5BSN191SQ2
CRCW0805 0.0 RT1
RT130B7
746X101103J
Part Number
Bill Of Materials
A-11
A-12
ADSP-BF561 EZ-KIT Lite Evaluation System Manual
0.01UF 16V 10% 402
1.5UH 45MOHM 20% IND003 2.8A
100MA CMDSH-3 SOD-323
SUPERMINI SCHOTTKY
0.18uF 25V 10% 805 CERM
100uF 10V 10% C
TANT-LOW-ESR
2.2uF 10V 10% 805
CERM
76.8K 100MW 1% 1206
110
111
112
113
114
115
0.1UF 10V 10% 402
108
109
C169
4.7UF 6.3V 10% 805
107
AVX
Manufacturer
R48
C43
CT19
C170
D4
L10
DALE
AVX
AVX
AVX
CENTRAL SEMI
TYCO
C204-205,C207,C214,C216, AVX
C223,C227-229,C231-232,C2
39-240,
C246-247,C251-252,C254,C2
57
C192-199,C206,
AVX
C209-213,C215,
C220,C224-226, C234-235,
C237-238,C242,
C244-245,C248, C250,C253,
C258-259
Reference Designator
Ref.# Description
CRCW1206-7682FRT1
0805ZD225KAT2A
TPSC107K010R0075
08053C184KAT2A
CMDSH-3
DS6630-1R5M
0402YC103KAT2A
0402ZD104KAT2A
08056D475KAT2A
Part Number
R56
147K 100MW 1% 1206
10 62.5MW/R 5% RA8/38V
RESISTOR ARRAY
17.4K 1/10W 1% 805
ADSP-BF561-EZLITE PCB
DB9 9PIN DB9M
RIGHT ANGLE MALE
1K 1/8W 5% 1206
100K 1/8W 5% 1206
22 1/8W 5% 1206
270 1/8W 5% 1206
680 1/8W 5% 1206
10.0K 1/8W 1% 1206
150 1/8W 1% 1206
116
117
118
119
120
121
122
123
124
125
ADSP-BF561 EZ-KIT Lite Evaluation System Manual
126
127
R3
R186
R119
R120,R193,R197,R213-220,
R230-237
R92-93
R9,R13,R157
R10,R95,R115-118,R136
P2
R180
RN1,RN4-12
Reference Designator
Ref.# Description
PANASONIC
DALE
AVX
AVX
DALE
DALE
AVX
3M
ANALOD
DEVICES
PANASONIC
PANASONIC
DALE
Manufacturer
ERJ-8ENF1500V
CRCW1206-1002FRT1
CR32-681J-T
CR32-271J-T
CRCW1206220JRT1
CR1206-1003FRT1
CR32-102J-T
787203-2
ERJ-6ENF1742V
EXB-38V100JV
CRCW1206-1473FRT1
Part Number
Bill Of Materials
A-13
A-14
ADSP-BF561 EZ-KIT Lite Evaluation System Manual
IDC 2X1 IDC2X1
IDC 7X2 IDC7X2 HEADER
2.5A RESETABLE FUS001
133
134
135
GOLD
ADG774A QSOP16
QUICKSWITCH-257
132
604 1/8W 1% 1206
130
1uF 25V 20% A
TANT -55+125
GREEN-SMT LED001
GULL-WING
129
131
LED2-3
RED-SMT LED001
GULL-WING
128
F1
P4
P1
U36-37
CT25-28
R125-130
LED1
Reference Designator
Ref.# Description
54102-T08-07
ADG774ABRQ
ECS-T1EY105R
CRCW12066040FRT1
LN1361C
LN1261C
Part Number
RAYCHEM CORP. SMD250-2
BERG
ANALOG
DEVICES
PANASONIC
DALE
PANASONIC
PANASONIC
Manufacturer
A
B
C
D
1
1
2
2
ADSP-BF561 EZ-KIT Lite
Schematic
3
3
ANALOG
DEVICES
4
Approvals
Drawn
JSZ
Checked
Engineering
A
B
C
Date
Title
ADSP-BF561 EZ-KIT LITE:
20 Cotton Road
Nashua, NH 03063
4
PH: 1-800-ANALOGD
TITLE
10/10/03
Size
Board No.
C
Date
Rev
A0185-2003
1.3A
Sheet
12-16-2003_11:50
D
1
of
18
A
B
C
D
U48
D0
D[31:0]
1
B16
D1
C15
D2
E12
D3
C16
D4
E14
D5
D15
D6
D16
D7
E15
D8
F13
D9
F15
D10
F12
D11
F16
D12
F14
3.3V
D13
G15
D14
G13
D15
G12
A[25:2]_S
D0
A2
D1
A3
D2
A4
D3
A5
D4
A6
D5
A7
D6
A8
D7
A9
D8
A10
D9
A11
D10
A12
D11
A13
D12
A14
D13
A15
D14
A16
D15
A17
R42
10K
805
D16
R60
33
805
U14
1
OE
OUT
3
H12
D17
H15
D18
H13
D19
H16
D20
H14
D21
J15
OSC_30MHZ
30.0000MHZ
OSC003
R51
DNP
805
EXT_DSP_CLK
D22
J13
D23
J16
D24
K14
D25
K15
D26
K13
D27
L15
3.3V
2
R160
10K
805
R196
10K
805
D28
K12
D29
L16
D30
D31
J12
M15
D16
A18
D17
A19
D18
A20
D19
A21
D20
A22
D21
A23
D22
A24
D23
A25
B12
ARDY
F1
3.3V
G1
D27
D28
D29
D30
SDQM0/ ABE0
SDQM1/ ABE1
SDQM2/ ABE2
SDQM3/ ABE3
BR
BGH
ARDY
ARE
RESET
CLKIN
AMS1
XTAL
AMS2
SRAS
SCAS
R170
10K
805
SWE
SA10
SMS0
3
DSP_BYPASS
BMODE0
G4
M10
BMODE1
N10
BYPASS
SMS1
SMS2
BMODE0
SMS3
BMODE1
SCKE
P11
NMI0
NMI1
R9
A5_S
B14
A6_S
C14
A7_S
A2_S
1
F11
A8_S
A3_S
2
RN4
D7
A9_S
A4_S
3
A6
A10_S
A5_S
4
C6
A11_S
A12_S
E6
A13_S
A5
A14_S
A6_S
1
E5
A15_S
A7_S
2
B4
A16_S
A8_S
3
A17_S
B3
A18_S
A9_S
4
A3
A20_S
F5
A21_S
A10_S
1
B2
A22_S
A11_S
2
D4
A23_S
A12_S
3
C3
A25_S
R2B
R3A
R3B
R4A
R4B
1
BMODE0
2
BMODE1
ON
ON
RESERVED
OFF
ON
8-BIT FLASH
ON
OFF
SPI SROM 8-BIT
OFF
OFF
SPI SROM 16-BIT
A13_S
NMI0
SCLK0
NMI1
SCLK1
6
A4
5
A5
R1A
R1B
R2A
R2B
R3A
R3B
R4A
R4B
8
A6
7
A7
1
A15_S
2
A16_S
3
A17_S
4
R1A
R2A
R3A
R4A
4
R1B
R2B
R3B
R4B
8
A14
7
A15
6
A16
5
A17
8
A18
7
A19
6
A20
5
A21
8
A22
7
A23
6
A24
5
A25
E11
ABE0_S
1
B13
ABE1_S
2
A14
ABE2_S
3
A15
ABE3_S
4
A13
6
A8
5
A18_S
1
A19_S
2
A20_S
3
A21_S
4
R1A
R2A
A9
R3A
R4A
R1B
R2B
R3B
R4B
R1A
R1B
R2A
R2B
R3A
R3B
R4A
R4B
8
A10
7
A11
6
A12
RN8
5
A22_S
1
A23_S
2
A24_S
3
A25_S
4
R1A
R2A
A13
R3A
R4A
R1B
R2B
R3B
R4B
A[25:2]
R1A
R1B
R2A
R2B
R3A
R3B
R4A
R4B
8
C12
7
ABE1
6
ABE2
5
ABE3
BGH
C7
AOE
B8
ARE
A8
AWE
C8
AMS0
B7
AMS1
E7
AMS2
A7
AMS3
RN10
C10
SRAS_S
1
D10
SCAS_S
2
E10
SWE_S
3
D11
SA10_S
4
E9
SMS0_S
B9
SMS1_S
C9
SMS2_S
A10
SMS3_S
1
2
B10
A11
SCKE
3
SCLK0_S
4
A12
R1A
R1B
R2A
R2B
R3A
R3B
R4A
R4B
8
SRAS
7
SCAS
6
SWE
5
SA10
10
RA8/38V
RN9
SCLK1_S
3
R1A
R1B
R2A
R2B
R3A
R3B
R4A
R4B
8
SMS0
7
SMS1
6
SMS2
5
SMS3
R187
22
805
SCLK0
3.3V
U20
1
REF
CLKOUT
CLK1
DEFAULT
6
VDD
4
GND
CLK3
CLK4
R68
22
805
8
3
CLK_OUT_EXP1
2
R67
22
805
5
CLK_OUT_EXP2
7
R65
22
805
IDT2305-1DC
SOIC8
SW3
ON
1
3
6
4
5
2
3
ANALOG
DEVICES
8
7
2
ABE0
10
RA8/38V
BG
SCLK1
2
1
10
RA8/38V
CLK2
DNP
4
SWT018
DIP4
Approvals
Drawn
JSZ
Checked
Engineering
A
A14_S
RN6
R176
10K
805
BOOT MODE
4
RN12
10
RA8/38V
R188
22
805
1
A3
RN7
ADSP-BF561SKBC-600
MBGA256
SW3: BOOT MODE/BYPASS Select
(Default = OFF, ON, ON, OFF)
7
10
RA8/38V
10
RA8/38V
R169
10K
805
A2
10
RA8/38V
A19_S
A24_S
R2A
8
RN5
C4
A2
R1B
10
RA8/38V
B5
F6
R1A
D31
AMS3
R168
10K
805
G10
RN11
C42
0.1UF
805
DNP
R167
10K
805
A4_S
D26
AMS0
DSPCK_30MHZ
A3_S
B15
10
RA8/38V
AWE
F3
RESET
G11
D25
AOE
D9
A2_S
D24
BG
BR
D13
B
C
Date
Title
ADSP-BF561 EZ-KIT LITE:
20 Cotton Road
Nashua, NH 03063
4
PH: 1-800-ANALOGD
DSP - EXT MEM INTERFACE
10/10/03
Size
Board No.
C
Date
Rev
A0185-2003
1.3A
Sheet
5-12-2004_16:35
D
2
of
18
A
B
C
D
U48
P15
RSCLK0
1
R16
RFS0
L12
DR0PRI
P16
DR0SEC
N16
TSCLK0
L13
TFS0
M16
DT0PRI
N15
DT0SEC
RSCLK0/PF28
PF15/TMRXCLK
RFS0/PF19
PF14
DR0PRI
PF13
DR0SEC/PF20
PF12
TSCLK0/PF29
PF11
TFS0/PF16
PF10
DT0PRI/PF18
PF9
DT0SEC/PF17
PF8
PF7/SPIS7/TMR7
P13
RSCLK1
N13
RFS1
M12
DR1PRI
T14
DR1SEC
R14
TSCLK1
P14
TFS1
R15
DT1PRI
T15
DT1SEC
RSCLK1/PF30
PF6/SPIS6/TMR6
RFS1/PF24
PF5/SPIS5/TMR5
DR1PRI
PF4/SPIS4/TMR4
DR1SEC/PF25
PF3/SPIS3/TMR3
TSCLK1/PF31
PF2/SPIS2/TMR2
TFS1/PF21
PF1/SPIS1/TMR1
DTIPRI/PF23
PF0/SPISS/TMR0
P8
PF15
R8
PF14
N8
PF13
T7
PF12
P7
PF11
PF[15:0]
1
RN1
R7
N6
R6
PF15
1
PF14
2
PF13
3
PF10
PF9
PF8
4
R1A
R2A
R1B
R2B
R3A
R3B
R4B
M7
PF7
R4A
T5
PF6
10
RA8/38V
P6
PF5
R5
PF4
M6
PF3
T4
PF2
N5
PF1
P4
PF0
8
AD1836_RESET
7
VENC_RESET
6
VDEC_RESET
5
DT1SEC/PF22
PROGR. FLAG
T13
RX
R13
TX
N11
MOSI
2
R12
MISO
3.3V
M11
SCK
R10
T10
T9
R85
10K
805
R200
10K
805
R179
10K
805
P10
RX/PF27
SLEEP
TX/PF26
MOSI
MISO
SCK
TDI
TDO
N9
TDO
TMS
TCK
TRST
EMU
FUNCTION
T11
R11
EMU
PF15
AD1836 CODEC RESET
PF14
ADV7179 VIDEO ENCODER RESET
PF13
ADV7183A VIDEO DECODER RESET
PF12
GENERAL PURPOSE
PF11
GENERAL PURPOSE
PF10
GENERAL PURPOSE
PF9
GENERAL PURPOSE
PF8
GENERAL PURPOSE / PUSH BUTTON STATUS INPUT
PF7
GENERAL PURPOSE / PUSH BUTTON STATUS INPUT
PF6
GENERAL PURPOSE / PUSH BUTTON STATUS INPUT/ UART SIGNAL
PF5
GENERAL PURPOSE / PUSH BUTTON STATUS INPUT/ UART SIGNAL
2
PF4
GENERAL PURPOSE / AD1836 LATCH SIGNAL
TDI
PF3
GENERAL PURPOSE / VIDEO DECODER FIELD
TMS
PF2
GENERAL PURPOSE / VIDEO DECODER OUTPUT ENABLE
PF1
GENERAL PURPOSE / I2C SERIAL DATA
PF0
GENERAL PURPOSE / I2C SERIAL CLOCK
TCK
ADSP-BF561SKBC-600
MBGA256
TRST
R86
4.7K
805
DSP_VDD_EXT
DSP_VDD_INT
U48
A1
A16
A4
A9
B11
B6
D12
E16
F2
G16
G3
J6
K16
K6
L10
L5
M14
T1
T12
T16
T3
T6
T8
3
C11
C13
C5
D14
D5
D6
D8
E1
E13
F10
F8
G14
G2
G6
G7
G8
H1
H10
H2
H8
H9
4
VDDEXT1
VDDEXT2
VDDEXT3
VDDEXT4
VDDEXT5
VDDEXT6
VDDEXT7
VDDEXT8
VDDEXT9
VDDEXT10
VDDEXT11
VDDEXT12
VDDEXT13
VDDEXT14
VDDEXT15
VDDEXT16
VDDEXT17
VDDEXT18
VDDEXT19
VDDEXT20
VDDEXT21
VDDEXT22
VDDEXT23
VDDINT1
VDDINT2
VDDINT3
VDDINT4
VDDINT5
VDDINT6
VDDINT7
VDDINT8
VDDINT9
VDDINT10
VDDINT11
VDDINT12
VDDINT13
VDDINT14
VROUT1
VROUT2
NC0
NC1
GND1
GND2
GND3
GND4
GND5
GND6
GND7
GND8
GND9
GND10
GND11
GND12
GND13
GND14
GND15
GND16
GND17
GND18
GND19
GND20
GND21
GND41
GND40
GND39
GND38
GND37
GND36
GND35
GND34
GND33
GND32
GND31
GND30
GND29
GND28
GND27
GND26
GND25
GND24
GND23
GND22
ADSP-BF561SKBC-600
MBGA256
E8
F7
F9
G9
H11
H6
H7
J10
J8
J9
K11
K8
L8
M8
J1
3
VROUT
J2
M5
M13
P9
P5
P2
P12
N7
N14
N12
M9
M4
L9
L7
L3
L14
L11
K9
K7
K10
J7
J14
J11
ANALOG
DEVICES
Approvals
Drawn
JSZ
Checked
Engineering
A
B
C
Date
Title
ADSP-BF561 EZ-KIT LITE:
20 Cotton Road
Nashua, NH 03063
4
PH: 1-800-ANALOGD
DSP - PROGR. FLAGS, SPI
10/10/03
Size
Board No.
C
Date
Rev
A0185-2003
1.3A
Sheet
5-6-2004_16:04
D
3
of
18
A
B
C
D
SW5: PPI CLK Routing Select
(Default: 1 = OFF, 2 = ON, 3 = ON, 4 = ON)
1 or 3
PPIxCLK_SEL0
2 or 4
PPIxCLK_SEL1
PPIxCLK
ON
ON
PPI_27MHZ_CLK
OFF
ON
VDEC_CLKOUT
X
OFF
EXPANSION_CLK
3.3V
3.3V
R166
33
805
VDEC_27MHZ_CLK
R165
33
805
1
R162
10K
805
U22
3
R174
10K
805
VENC_27MHZ_CLK
3.3V
R175
10K
805
R182
10K
805
R181
10K
805
R171
33
805
R59
33
805
U17
1
OE
OUT
3
U23
1
1
R66
0.00
805
3
6
1
PPI0_CLK
6
4
EXT_27MHZ_CLK
U19
4
OSC_27M
OSC27M
1
REF
CLKOUT
CLK1
27MHZ
OSC003
CLK2
6
VDD
CLK3
4
GND
CLK4
8
ADG752BRT
SOT23-6
3
ADG752BRT
SOT23-6
EXP_PPI0_CLK
2
R172
33
805
5
U26
7
PPI_27MHZ_CLK
3
U25
1
IDT2305-1DC
SOIC8
SW5
1
6
VDEC_CLKOUT
2
7
PPI0CLK_SEL1
3
6
PPI1CLK_SEL0
4
5
PPI1CLK_SEL1
ON
PPI0CLK_SEL0
1
8
R178
0.00
805
3
1
PPI1_CLK
6
4
2
4
3
4
SWT018
DIP4
ADG752BRT
SOT23-6
ADG752BRT
SOT23-6
EXP_PPI1_CLK
U48
2
PPI0_D[15:0]
PPI0_D15
D2
PPI0_D14
G5
PPI0_D13
D1
PPI0_D12
E3
PPI0_D11
E2
PPI0_D10
F4
PPI0_D9
H3
PPI0_D8
K3
PPI0_D7
H4
PPI0_D6
K1
H5
PPI0_D4
K2
PPI0_D3
J4
PPI0_D2
J3
PPI0_D1
J5
PPI0_D0
L1
3
PPI0_D13/PF45
PPI1_D13/PF37
PPI0_D12/PF44
PPI1_D12/PF36
PPI0_D11/PF43
PPI1_D11/PF35
PPI0_D10/PF42
PPI1_D10/PF34
PPI0_D9/PF41
PPI1_D9/PF33
PPI1_D8/PF32
PPI0_D7
PPI1_D7
PPI0_D6
PPI1_D6
PPI0_D5
PPI1_D5
PPI0_D4
PPI1_D4
PPI0_D3
PPI1_D3
PPI0_D2
PPI1_D2
PPI1_D1
PPI1_D0
PPI0_CLK
C1
D3
PPI0_SYNC3
PPI1_D14/PF38
PPI0_D0
E4
PPI0_SYNC2
PPI0_D14/PF46
PPI0_D1
C2
PPI0_SYNC1
PPI1_D15/PF39
PPI0_D8/PF40
PPI0_D5
PPI0_CLK
PPI0_D15/PF47
PPI1_CLK
PPI0_SYN1/TMR8
PPI1_SYN1/TMR10
PPI0_SYN2/TMR9
PPI1_SYN2/TMR11
PPI0_SYN3
PPI1_SYN3
M1
PPI1_D15
K5
PPI1_D14
M2
PPI1_D13
N1
PPI1_D12
L6
PPI1_D11
PPI1_D8
2
N2
PPI1_D10
PPI1_D9
4
M3
PPI1_D9
PPI1_D10
6
P1
PPI1_D8
PPI1_D11
8
R1
PPI1_D7
PPI1_D12
11
R2
PPI1_D6
PPI1_D13
13
PPI1_D14
15
PPI1_D15
17
2
PPI1_D[15:0]
U13
1A1
1A2
1A3
1A4
2A1
2A2
P3
PPI1_D5
T2
PPI1_D4
N3
PPI1_D3
R3
PPI1_D2
1
N4
PPI1_D1
19
R4
PPI1_D0
2A3
2A4
18
1Y1
16
1Y2
14
1Y3
12
1Y4
9
2Y1
7
2Y2
5
2Y3
3
2Y4
OE1
LED20
AMBER-SMT
LED001
OE2
LED19
AMBER-SMT
LED001
LED18
AMBER-SMT
LED001
LED17
AMBER-SMT
LED001
LED16
AMBER-SMT
LED001
LED15
AMBER-SMT
LED001
LED14
AMBER-SMT
LED001
LED13
AMBER-SMT
LED001
IDT74FCT3244APY
SSOP20
B1
PPI1_CLK
K4
R237
270
1206
PPI1_SYNC1
L2
R236
270
1206
R235
270
1206
R234
270
1206
R233
270
1206
R232
270
1206
R231
270
1206
R230
270
1206
PPI1_SYNC2
L4
3
PPI1_SYNC3
ADSP-BF561SKBC-600
MBGA256
U30
PPI0_D8
2
PPI0_D9
4
PPI0_D10
6
PPI0_D11
8
PPI0_D12
11
PPI0_D13
13
PPI0_D14
15
PPI0_D15
17
1
19
18
1A1
1Y1
1A2
1Y2
1A3
1Y3
1A4
1Y4
2A1
2Y1
2A2
2Y2
2A3
2Y3
2A4
2Y4
16
14
12
9
7
5
3
OE1
OE2
LED12
AMBER-SMT
LED001
LED11
AMBER-SMT
LED001
LED10
AMBER-SMT
LED001
LED9
AMBER-SMT
LED001
LED8
AMBER-SMT
LED001
LED7
AMBER-SMT
LED001
LED6
AMBER-SMT
LED001
LED5
AMBER-SMT
LED001
ANALOG
DEVICES
IDT74FCT3244APY
SSOP20
4
R220
270
1206
R219
270
1206
R218
270
1206
R217
270
1206
R216
270
1206
R215
270
1206
R214
270
1206
R213
270
1206
Approvals
Drawn
JSZ
Checked
Engineering
A
B
C
Date
Title
ADSP-BF561 EZ-KIT LITE:
20 Cotton Road
Nashua, NH 03063
4
PH: 1-800-ANALOGD
DSP - PPI0 AND PPI1
10/10/03
Size
Board No.
C
Date
Rev
A0185-2003
1.3A
Sheet
5-12-2004_16:32
D
4
of
18
A
B
C
FLASH A (8MB)
D
SDRAM 64MB
(256Mb x 2 Chips)
4M x 16
D[31:0]
1
1
U32
A[25:2]
U27
25
ABE3
A2
24
A3
23
A4
22
A5
21
A6
20
A7
19
A8
A9
8
A10
7
A11
6
A12
5
A13
3.3V
2
R190
10K
805
R177
10K
805
4
A14
3
A15
2
A16
1
A17
48
A18
17
A19
16
A20
R189
10K
805
18
9
A21
10
A22
13
26
AMS0
28
AOE
11
AWE
47
FLASH_WP
14
FLASH_RP
12
3.3V
A0
A1
A2
VCC
37
A3
A4
D0
A5
D1
A6
D2
A7
D3
A8
D4
A9
D5
A10
D6
A11
D7
A12
D8
A13
D9
A14
D10
A15
D11
A16
D12
A17
D13
A18
D14
A19
D15
29
D0
31
D1
33
D2
35
D3
38
D4
40
D5
42
D6
44
D7
30
D8
32
D9
34
D10
36
D11
23
A3
24
A4
25
A5
26
A6
29
A7
30
A8
31
A9
32
A10
33
A11
34
SCAS
41
D13
SRAS
43
D14
45
D15
R183
10K
805
A20
D4
10
D5
11
D6
13
D7
42
D8
44
D9
DQ7
A8
DQ8
A9
DQ9
45
DQ10
47
DQ11
48
DQ12
50
DQ13
51
DQ14
53
DQ15
A10
A11
A12_NC
21
8
DQ6
A7
A19
D3
DQ5
A6
20
D2
7
DQ4
A5
A18
5
DQ3
A4
36
D1
DQ2
A3
A14
D0
4
DQ1
A2
35
2
DQ0
A1
A13
BA0
BA1
16
SWE
3.3V
A0
22
SA10
D12
39
A2
D10
D11
D12
D13
D14
D15
19
CS
37
CKE
38
CLK
WE
17
CAS
18
RAS
SMS0
2
SCKE
SCLK0
15
ABE0
DQML
39
ABE1
DQMH
A21
CE
RDY
15
MT48LC16M16A2TG-75
TSOP54
FLASH_RDY
OE
U33
WE
BYTE
VSS2
WP/VPP
VSS1
46
A2
23
A3
24
A4
25
A5
26
A6
29
A7
30
A8
31
A0
27
RP
M29W64OD
TSOP48
A1
34
A7
36
A11
A12_NC
A18
20
A19
21
D21
11
D22
13
D23
42
D24
44
D25
45
DQ10
47
DQ11
48
DQ12
50
DQ13
51
DQ14
53
DQ15
D26
DQ9
A10
A14
D20
10
DQ8
A9
35
8
DQ7
A8
A13
D19
DQ6
22
3
D18
7
DQ5
A6
A11
5
DQ4
A5
33
D17
DQ3
A4
32
4
DQ2
A3
A9
D16
DQ1
A2
A10
2
DQ0
BA0
BA1
3
D27
D28
D29
D30
D31
Memory Map
16
START
0x0000 0000
0x2000 0000
END
0x03FF FFFF
0x207F FFFF
BANK
SDRAM Bank 0
ASYNC Memory Bank 0
19
CS
37
CKE
38
CLK
WE
DEVICE
17
CAS
18
64MB SDRAM
8MB FLASH
RAS
ABE2
ABE3
15
DQML
39
DQMH
MT48LC16M16A2TG-75
TSOP54
ANALOG
DEVICES
4
Approvals
Drawn
JSZ
Checked
Engineering
A
B
C
Date
Title
ADSP-BF561 EZ-KIT LITE:
20 Cotton Road
Nashua, NH 03063
4
PH: 1-800-ANALOGD
MEMORY - FLASH & SDRAM
10/10/03
Size
Board No.
C
Date
Rev
A0185-2003
1.3A
Sheet
12-16-2003_11:03
D
5
of
18
A
B
C
D
ADC2
ADC1
R61
33
805
U16
1
OE
1
DAC1
R161
10K
805
DAC2
DAC3
3.3V
LEFT (WHITE)
OUT
3
AD1836_CLK
RIGHT (RED)
1
12.288MHZ
OSC003
OUT (J4)
R18
5.49K
1206
IN (J5)
R145
11.0K
1206
C7
100PF
1206
R138
3.32K
1206
OUT1R-
C96
330PF
805
3.3V
6
U5
7
DAC1 RIGHT
5
C117
680PF
805
R30
5.49K
1206
R57
10K
805
AD8606AR
SOIC8
R29
1.65K
1206
R126
604
1206
OUT1R+
AUDIO CODEC
J5
3X2
CON024
CT8
10UF
CAP002
DAC1_RIGHT 7
U15
47
DR0PRI
OUT1L+
OUT1L+
ASDATA2
9
OUT1L-
OUT1L-
48
DR0SEC
44
RFS0
31
ABCLK
OUT1R+
OUT1R+
30
2
OUT1R45
AD1836_CLK
OUT1R-
6
CLATCH
51
SCK
ADC1 LEFT
R46
10K
805
R45
10K
805
ADC1 RIGHT
IN1L+
OUT3L+
OUT3L+
IN1L-
5
OUT3L-
OUT3L-
OUT2R+
32
OUT2R-
4
35
IN1R+
19
IN1R-
DAC1 RIGHT
2
DAC2 LEFT
AGND
33
OUT2R-
18
IN1R+
OUT2L-
OUT2R+
17
IN1L-
OUT2L+
7
OUT2L-
COUT
16
IN1L+
R47
10K
805
OUT2L+
CDATA
49
MISO
9
R109
49.9K
1206
C77
2200PF
1206
CCLK
2
MOSI
C14
220PF
1206
MCLK
50
PF4
R151
2.74K
1206
DAC1 LEFT
ALRCLK
43
RSCLK0
8
ASDATA1
OUT3R+
OUT3R+
34
IN1R-
OUT3R-
OUT3R-
DAC2 RIGHT
DAC3 LEFT
R17
5.49K
1206
R144
11.0K
1206
DAC3 RIGHT
C6
100PF
1206
R137
3.32K
1206
OUT1L20
IN2L+/CL2/CL2
21
ADC2 LEFT
DSDATA2
NC/IN2L1/IN2L+
DSDATA3
NC/IN2L2/IN2L-
DLRCLK
23
IN2L2
IN2R2
ADC2 RIGHT IN2R1
3
42
TSCLK0
26
IN2R-/CR1/CR1
27
U5
3
R159
0.00
1206
C116
680PF
805
R27
5.49K
1206
AD8606AR
SOIC8
R28
1.65K
1206
C38
0.001UF
805
C39
0.001UF
805
3
DAC1_LEFT 8
CT16
10UF
B
C124
0.1UF
805
CT15
10UF
B
C123
0.1UF
805
R150
2.74K
1206
C13
220PF
1206
9
3
C133
0.001UF
805
R108
49.9K
1206
C76
2200PF
1206
AD1836AAS
MQFP52
C40
0.001UF
805
J5
3X2
CON024
CT7
10UF
CAP002
IN2R+/CR2/CR2
PD/RST
R158
10K
805
R125
604
1206
OUT1L+
3
AD1836_RESET
DAC1 LEFT
13
FILTR
12
FILTD
NC/IN2R1/IN2R+
2
1
TFS0
37
NC/IN2R2/IN2R-
25
C95
330PF
805
DT0SEC
36
DBCLK
24
DT0PRI
41
IN2L-/CL1/CL1
22
IN2L1
DSDATA1
38
U12
1
AD1836_VREF
AGND
2
AD8606AR
SOIC8
R43
0.00
1206
R55
0.00
1206
AGND
5
U12
AGND
7
SW10: Audio Loopback
For Test Purposes
Default = All Off
6
AD8606AR
SOIC8
SW10
ON
11
3
10
4
9
5
8
6
7
3
ADC2_LEFT
4
ADC2_RIGHT
12
2
2
ADC1_RIGHT
1
ADC1_LEFT
4
1
R44
0.00
1206
R71
0.00
1206
DAC1_LEFT
DAC1_RIGHT
20 Cotton Road
Nashua, NH 03063
4
PH: 1-800-ANALOGD
DAC2_LEFT
Approvals
DAC2_RIGHT
5
DAC3_LEFT
AGND
6
DAC3_RIGHT
SWT017
DIP6
Drawn
JSZ
Checked
Engineering
A
ANALOG
DEVICES
B
C
Date
Title
ADSP-BF561 EZ-KIT LITE:
AUDIO CODEC
10/10/03
Size
Board No.
C
Date
Rev
A0185-2003
1.3A
Sheet
5-12-2004_16:35
D
6
of
18
A
B
C
D
1
1
R19
5.49K
1206
R146
11.0K
1206
C8
100PF
1206
R22
5.49K
1206
R139
3.32K
1206
OUT2R-
R149
11.0K
1206
C97
330PF
805
2
C100
330PF
805
3
R31
5.49K
1206
C118
680PF
805
AD8606AR
SOIC8
R32
1.65K
1206
R142
3.32K
1206
OUT3R-
U6
1
DAC2 RIGHT
C11
100PF
1206
6
U7
7
DAC3 RIGHT
R128
604
1206
5
J5
3X2
CON024
CT10
10UF
CAP002
OUT2R+
DAC2_RIGHT
R38
5.49K
1206
4
C121
680PF
805
AD8606AR
SOIC8
R37
1.65K
1206
R130
604
1206
R152
2.74K
1206
C15
220PF
1206
J5
3X2
CON024
CT12
10UF
CAP002
OUT3R+
6
AD1836_VREF
DAC3_RIGHT 1
R111
49.9K
1206
C79
2200PF
1206
R155
2.74K
1206
C18
220PF
1206
3
R113
49.9K
1206
C81
2200PF
1206
2
2
AGND
AGND
R20
5.49K
1206
R147
11.0K
1206
C9
100PF
1206
R21
5.49K
1206
R140
3.32K
1206
R148
11.0K
1206
OUT2L-
R141
3.32K
1206
OUT3L-
C98
330PF
805
6
U6
C99
330PF
805
7
3
C10
100PF
1206
DAC2 LEFT
2
U7
5
R34
5.49K
1206
C119
680PF
805
AD8606AR
SOIC8
R33
1.65K
1206
R127
604
1206
OUT2L+
3
J5
3X2
CON024
CT9
10UF
CAP002
DAC2_LEFT 5
R153
2.74K
1206
C16
220PF
1206
3
1
DAC3 LEFT
R35
5.49K
1206
C120
680PF
805
AD8606AR
SOIC8
R36
1.65K
1206
R129
604
1206
J5
3X2
CON024
CT11
10UF
CAP002
OUT3L+
DAC3_LEFT 2
6
R110
49.9K
1206
C78
2200PF
1206
R154
2.74K
1206
C17
220PF
1206
3
R112
49.9K
1206
C80
2200PF
1206
AGND
AGND
ANALOG
DEVICES
4
Approvals
Drawn
JSZ
Checked
Engineering
A
B
C
Date
Title
ADSP-BF561 EZ-KIT LITE:
20 Cotton Road
Nashua, NH 03063
4
PH: 1-800-ANALOGD
AUDIO OUT
10/10/03
Size
Board No.
C
Date
Rev
A0185-2003
1.3A
Sheet
12-10-2003_18:18
D
7
of
18
A
1
J4
2X2
CON013
B
CT5
10UF
CAP002
FER10
600
1206
2
R121
5.76K
1206
C
R49
5.76K
1206
1
J4
2X2
CON013
5
3
C62
100PF
1206
2
R123
5.76K
1206
R62
5.76K
1206
ADC2_LEFT
6
C142
120PF
1206
C72
100PF
1206
R53
237
1206
U11
AGND
U18
2
1
IN1L-
AGND
AGND
1
AGND
3
C25
0.001UF
805
R50
5.76K
1206
AD8606AR
SOIC8
C26
100PF
1206
R58
5.76K
1206
R63
5.76K
1206
ADC1 LEFT
C130
120PF
1206
6
C23
0.001UF
805
R164
750K
1206
R54
237
1206
U11
U18
6
7
7
IN1L+
5
2
ADC2 LEFT
C144
120PF
1206
AGND
R156
750K
1206
IN2L2
3
AD8606AR
SOIC8
R40
5.76K
1206
CT13
10UF
CAP002
FER12
600
1206
ADC1_LEFT
C128
120PF
1206
D
IN2L1
5
AD8606AR
SOIC8
2
AD8606AR
SOIC8
AGND
AGND
J4
2X2
CON013
CT6
10UF
CAP002
FER11
600
1206
1
R122
5.76K
1206
J4
2X2
CON013
R15
5.76K
1206
ADC1_RIGHT
4
3
C103
120PF
1206
C63
100PF
1206
2
CT14
10UF
CAP002
FER9
600
1206
R25
237
1206
U9
R69
5.76K
1206
ADC2_RIGHT
6
AGND
R124
5.76K
1206
C161
120PF
1206
C61
100PF
1206
2
1
1
IN1R-
AGND
AGND
3
R8
5.76K
1206
AD8606AR
SOIC8
C36
0.001UF
805
R16
5.76K
1206
C34
100PF
1206
R64
5.76K
1206
AGND
6
ADC1 RIGHT
C33
0.001UF
805
R173
750K
1206
6
7
ADC2 RIGHT
C163
120PF
1206
R26
237
1206
U9
3
R70
5.76K
1206
C105
120PF
1206
R132
750K
1206
IN2R2
3
AD8606AR
SOIC8
3
U24
AGND
U24
7
IN1R+
5
IN2R1
5
AD8606AR
SOIC8
AD8606AR
SOIC8
AGND
AGND
AD1836_VREF
ANALOG
DEVICES
4
Approvals
Drawn
JSZ
Checked
Engineering
A
B
C
Date
Title
ADSP-BF561 EZ-KIT LITE:
20 Cotton Road
Nashua, NH 03063
4
PH: 1-800-ANALOGD
AUDIO IN
10/10/03
Size
Board No.
C
Date
Rev
A0185-2003
1.3A
Sheet
12-10-2003_18:18
D
8
of
18
A
B
C
D
SW11
1
7
3
6
4
5
3
VIDEO_AVIN5
8
2
2
VIDEO_AVIN4
ON
1
VIDEO_AVIN1
VIDEO_DAC_A
VIDEO_DAC_C
VIDEO_DAC_B
4
SWT018
DIP4
SW11: Video Loopback
For Test Purposes
Default = All Off
1
R136
1K
1206
1
A3V
VIDEO_DAC_A
U3
L1
0.68UH
805
L5
2.2UH
805
L4
0.68UH
805
1
3
2
R114
75
1206
C92
330PF
805
C86
330PF
805
R104
75
1206
5
4
J6
3X2
CON024
R6
75
1206
8
DAC A
DAC A
DAC B
DAC C
Composite Video
CVSB
CVSB
C
Component Video
G
B
R
Differential Component Video
Y
U
V
S Video
Y
C
AD8061ART
SOT23-5
9
R10
1K
1206
AGND2
VIDEO ENCODER
3V_B
R116
1K
1206
2
2
U8
VAA1
VAA2
VAA3
VAA4
VAA5
PPI1_D7
PPI1_D[15:0]
5
PPI1_D6
4
PPI1_D5
3
PPI1_D4
39
PPI1_D3
38
PPI1_D2
37
PPI1_D1
36
PPI1_D0
35
P7
DAC_A
P6
DAC_B
P5
DAC_C
1
P3
COMP
P2
VREF
P1
RSET
16
3
PF1
PF[15:0]
PF0
22
21
CLOCK
FIELD/VSYNC
GND1
GND2
SDATA
GND3
SCLOCK
GND5
GND6
34
33
25
C115
0.1UF
805
C12
0.1UF
805
R23
1.2K
1206
U1
27
GND7
SCRESET/RTC
GND8
TTX
GND9
TTXREQ
GND10
L9
2.2UH
805
L2
0.68UH
805
1
28
3
2
24
23
R135
75
1206
30
C94
330PF
805
C82
330PF
805
R4
75
1206
DAC B
5
AD8061ART
SOT23-5
6
R115
1K
1206
31
13
VENC_HS
14
VENC_VS
15
R118
1K
1206
6
7
3
8
A3V
1
9
R3
150
1206
11
12
D1
AD1580
SOT23D
VIDEO_DAC_C
2
U2
17
L6
0.68UH
805
26
L7
2.2UH
805
L3
0.68UH
805
1
3
40
2
R134
75
1206
R9
100K
1206
C93
330PF
805
C84
330PF
805
J6
3X2
CON024
R105
75
1206
5
4
19
ADV7179
LFCSP40
R143
10K
805
5
4
L8
0.68UH
805
29
J6
3X2
CON024
R107
75
1206
AGND2
ALSB
3V_B
32
R14
10K
805
RESET
GND4
R13
100K
1206
VIDEO_DAC_B
18
P0
BLANK
20
VENC_RESET
A3V
10
P4
HSYNC
VENC_27MHZ_CLK
2
R5
75
1206
2
DAC C
AD8061ART
SOT23-5
3
R117
1K
1206
AGND2
R133
0.00
1206
ANALOG
DEVICES
4
AGND2
Approvals
Drawn
JSZ
Checked
Engineering
A
B
C
Date
Title
ADSP-BF561 EZ-KIT LITE:
20 Cotton Road
Nashua, NH 03063
4
PH: 1-800-ANALOGD
VIDEO ENCODER (VIDEO OUT)
10/10/03
Size
Board No.
C
Date
Rev
A0185-2003
1.3A
Sheet
5-12-2004_16:35
D
9
of
18
C
DAC_D
B
DAC_B
DAC_C
A
3.3V
(WHITE) OUT
1
D
VIDEO DECODER
R12
10K
805
(RED) IN
R11
10K
805
R131
10K
805
R2
10K
805
Note: Signal Names in brackets refer to ADV7183KST
1
XTAL1
P15
P14
P13
Composite Video
CVBS
CVBS
CVBS
Differential Component Video
Y
S Video
Y
PF[15:0]
V
PF1
67
PF0
68
ALSB
P12
SDA
P11
SCLK
P10
U
P9
C
64
VDEC_RESET
36
J6
3X2
CON024
R99
0.00
805
7
AVIN1
P8
PWRDN
P7
P6
R7
10K
805
C60
0.1UF
805
RESET
65
NC[ISO]
P4
VIDEO_AVIN1
42
41
AIN1
P3
AIN7
P2
9
P1
TP1
J6
3X2
CON024
2
4
AVIN4
44
43
R103
0.00
805
P5
C66
0.1UF
805
P0
46
45
AIN3
LLC2
AIN9
NC[LLCREF]
6
ELPF
58
J6
3X2
CON024
57
R106
0.00
805
1
AVIN5
C65
0.1UF
805
60
59
AIN10
AIN5
AIN11
3
R100
75
1206
R102
75
1206
HS
62
61
CT3
10UF
B
C58
0.1UF
805
CT1
10UF
B
FIELD
NC[VREF]
NC[HREF]
TP3
R101
75
1206
C2
0.1UF
805
AGND2
52
49
AGND2
CT4
10UF
B
C59
0.1UF
805
C68
0.001UF
805
AIN12
REFOUT
CML
CAPY1
CAPY2
54
NC[CLKIN]
SFL[HFF]
NC[AEF]
NC[RD]
OE
CAPC1
NC[GPO3]
CAPC2
NC[GPO2]
3
NC[GPO1]
NC[GPO0]
C4
0.1UF
805
CT2
10UF
B
C57
0.1UF
805
C67
0.001UF
805
50
AVDD
DVDD1
DVDD2
DVDD3
AGND2
A3V
A5V
AGND2
38
C54
0.1UF
805
C1
0.1UF
805
PVDD
DVDDIO1
DVDDIO2
39
DNP
FER13
600
1206
40
47
53
AGND2
5
PPI0_D3
6
PPI0_D2
7
PPI0_D1
8
PPI0_D0
19
R39
33
805
20
AGND2
56
FER14
600
1206
63
21
4
22
SN74LVC1G32
SOT23-5
23
24
PVDD_ADV7183
32
33
27
C5
0.01UF
805
26
25
R1
1.5K
805
37
2
VDEC_HS
1
VDEC_VS
80
VDEC_FIELD
69
VDEC_VREF
70
VDEC_HREF
16
11
C55
0.1UF
805
VENC_HS
11
R24
10K
805
13
78
10
9
VENC_VS
77
8
79
7
1
2
3
4
5
PF3
6
PF2
PPI1_SYNC1
PPI0_SYNC1
PPI0_SYNC2
PPI1_SYNC2
PF[15:0]
17
18
34
DVDD_ADV7183
1.8V
35
FER15
600
1206
30
10
DNP
FER17
600
1206
72
4
3.3V
3
SW2: Video Sync Signals and Encoder Enable Select
Defalut = OFF, OFF, OFF, OFF, OFF, ON
Position
Function
1-5
Connect video sync signals to DSP
ON = PF2 Used to enable or disable
6
the encoder digital interface
OFF = Encoder digital interface always disabled
15
AGND1
AGND2
DGND1
AGND3
DGND2
AGND4
DGND3
AGND5
DGND4
NC[AGND6]
DGND5
3
9
14
31
71
C3
0.01UF
805
C73
0.1UF
805
ANALOG
DEVICES
C74
0.01UF
805
Drawn
AGND2
JSZ
Checked
Engineering
B
SW2
12 ON
12
Approvals
A
2
C64
82NF
805
A1.8V
4
VDEC_CLKOUT
2
ADV7183AKST
LQFP80
PVDD_ADV7183
DNP
FER1
600
1206
FER2
600
1206
R41
33
805
U10
1
SWT017
DIP6
55
C56
0.1UF
805
PPI0_D4
AIN6
NC[DV]
48
76
3.3V
NC[AFF]
51
PPI0_D5
AIN4
VS
VIDEO_AVIN5
75
PPI0_D[15:0]
AIN8
LLC1
TP2
VIDEO_AVIN4
AIN2
PPI0_D6
1
AVIN5
74
2
AVIN4
PPI0_D7
3
66
AVIN1
73
4
28
XTAL
5
29
VDEC_27MHZ_CLK
6
AVIN1
AVIN4
AVIN5
U4
C
Date
Title
ADSP-BF561 EZ-KIT LITE:
20 Cotton Road
Nashua, NH 03063
4
PH: 1-800-ANALOGD
VIDEO ENCODER (VIDEO IN)
10/10/03
Size
Board No.
C
Date
Rev
A0185-2003
1.3A
Sheet
12-16-2003_11:24
D
10
of
18
A
B
C
D
3.3V
3.3V
3.3V
R248
10K
805
PF5
R242
100
805
3
1
R247
0.00
1206
U47
R98
10K
805
SW6
SWT013
SPST-MOMENTARY
4
74LVC14A
SOIC14
R246
10K
805
U47
1
CT25
1UF
A
U47
2
13
74LVC14A
SOIC14
1
12
74LVC14A
SOIC14
5V
3.3V
3.3V
3.3V
RESET
LED2
RED-SMT
LED001
POWER
LED1
GREEN-SMT
LED001
R249
10K
805
R119
680
1206
USB RESET
LED3
RED-SMT
LED001
R120
270
1206
3.3V
PF6
R243
100
805
U47
11
R185
10K
805
R223
0.00
1206
R193
270
1206
10
SW7
SWT013
SPST-MOMENTARY
74LVC14A
SOIC14
CT26
1UF
A
2
4
R229
10K
805
RESET
2
1
MR
4
PFI
SW1
SWT013
SPST-MOMENTARY
USB_RESET
2
SN74AHC1G00
SOT23-5
U46
8
RESET
7
RESET
RESET
5
PFO
3.3V
ADM708SAR
SOIC8
SOFT_RESET
R250
10K
805
PF7
U28
1
USB_CONFIGURED
R244
100
805
R224
0.00
1206
U47
9
SW8
SWT013
SPST-MOMENTARY
8
74LVC14A
SOIC14
3.3V
CT27
1UF
A
C158
0.1UF
805
U21
1
C1+
3
C1-
3
C159
0.1UF
805
R184
0.00
805
PF[15:0]
11
TX
T1IN
PF5
SW4
R225
0.00
1206
U47
2
11
PF6
6
10
PF7
4
9
PF8
5
8
TFS0
6
6
RSCLK0
5
74LVC14A
SOIC14
3
4
5
CT28
1UF
A
PF5
3
R245
100
805
SW9
SWT013
SPST-MOMENTARY
ON 12
2
PF8
1
1
R251
10K
805
10
T2IN
DNP
2
P2
FER19
600
603
14
T1OUT
FER20
600
603
13
R191
0.00
805
7
C148
0.1UF
805
FER18
600
603
8
9
DNP
5
TSCLK0
SWT017
DIP6
SW4 PB Enable Switch
Default = ON, ON, ON, ON, OFF, OFF
Position
Function
Connects the push buttons to the Programmable Flags of the DSP
1-4
Useful if using the PFs for another purpose.
OFF, OFF = AD1836A -> TDM Mode
5,6
ON, ON = AD1836A -> I2S Mode
DB9M
9PIN
ANALOG
DEVICES
Approvals
Drawn
JSZ
Checked
Engineering
A
UART
3
4
NOTE: Remove R192 when populating R191 and R184
4
6
2
7
PF6
RFS0
1
7
T2OUT
R1OUT
R1IN
9
8
R2OUT
R2IN
ADM3202ARN
SOIC16
R192
0.00
805
3
FER21
600
603
6
V-
12
RX
2
IDC2X1
2X1
V+
4
C2+
5
C2-
3.3V
P1
1
C147
0.1UF
805
B
C
Date
Title
ADSP-BF561 EZ-KIT LITE:
20 Cotton Road
Nashua, NH 03063
4
PH: 1-800-ANALOGD
RESET, PUSH-BUTTON SWITCHES, UART
10/10/03
Size
Board No.
C
Date
Rev
A0185-2003
1.3A
Sheet
12-16-2003_11:24
D
11
of
18
A
B
C
D
EXPANSION INTERFACE (TYPE B)
5V
3.3V
D[31:0]
A[25:2]
J1
2
1
4
3
5V
1
A3
6
5
8
7
10
9
A4
A7
12
11
A6
A9
14
13
A8
16
15
MOSI
MISO
A10
A13
18
17
A12
A15
20
19
A14
A17
22
21
A16
PF5
A19
A21
24
23
26
25
28
27
A22
30
29
A24
PPI0_SYNC2
PF0
2
32
31
DT1SEC
34
33
DT1PRI
35
TFS1
38
37
TSCLK1
40
39
D0
DT0SEC
D3
42
41
D2
DT0PRI
D5
44
43
D4
TFS0
D7
46
45
D6
TSCLK0
D9
48
47
D8
D11
50
49
D10
D13
52
51
D12
D15
54
53
D14
D17
56
55
D16
D19
58
57
D18
62
61
D22
D25
64
63
D24
ABE3
D26
ABE2
PPI0_D[15:0]
D29
68
67
D28
ABE1
D31
70
69
D30
ABE0
PPI0_D0
72
71
PPI0_D2
74
73
PF14
PF[15:0]
3
65
76
75
14
13
16
15
18
17
20
19
SCK
22
21
24
23
26
25
28
27
30
29
32
31
34
33
36
35
38
37
40
39
NMI0
7
PPI1_D2
10
9
PPI1_D3
PPI1_D4
12
11
PPI1_D5
PPI1_D7
PPI1_D8
16
15
PPI1_D9
PPI0_SYNC1
PPI1_D10
18
17
PPI1_D11
DR1SEC
PPI1_D12
20
19
PPI1_D13
DR1PRI
PPI1_D14
22
21
PPI1_D15
RFS1
24
23
RSCLK1
26
25
28
27
DR0PRI
30
29
RFS0
32
31
34
33
36
35
38
37
40
39
42
41
44
43
46
45
48
47
RESET
VDEC_HS
RSCLK0
DSP_VDD_EXT
PPI0_D8
PPI1_SYNC2
PPI0_D10
54
53
PPI0_D14
PF2
56
55
PF3
AWE
PPI0_D3
SMS2
SMS0
78
77
PF15
80
79
PF13
PF8
82
81
PF11
PF6
84
83
PF9
85
SRAS
PF7
88
87
SA10
90
89
SWE
45X2
CON019
57
60
59
62
61
64
63
66
65
68
67
70
69
72
71
74
73
76
75
78
77
80
79
82
81
84
83
86
85
88
87
90
89
EXP_PPI1_CLK
CLK_OUT_EXP1
EXT_DSP_CLK
2
VDEC_VS
VDEC_VREF
DSP_3V_VOUT
PPI1_SYNC3
PPI1_SYNC1
PPI0_D12
PPI0_D15
58
RX
13
VDEC_HREF
51
5
8
14
PPI0_D6
52
6
PPI1_D6
PPI0_D4
49
3
PPI1_D1
PPI0_SYNC3
45
50
4
DR0SEC
41
47
1
TX
43
48
1
J3
2
PPI1_D0
46
EXP_PPI0_CLK
PPI0_D1
PF10
86
11
44
AOE
PF12
PF4
9
12
D20
D23
66
10
PPI0_D7
PF0
D27
7
PPI0_D5
PPI0_D13
59
8
3.3V
PPI1_D[15:0]
VDEC_FIELD
PPI0_D11
60
5
42
PPI0_D9
D21
3
6
A20
A25
D1
4
A18
A23
36
1
A2
A5
A11
J2
2
PF1
50
49
AMS3
52
51
AMS2
54
53
AMS1
56
55
AMS0
58
57
ARDY
60
59
ARE
62
61
SMS3
64
63
SMS1
66
65
68
67
70
69
72
71
SCKE
74
73
SCAS
76
75
CLK_OUT_EXP2
78
77
80
79
82
81
84
83
86
85
88
87
90
89
45X2
CON019
EXT_27MHZ_CLK
3
BR
BG
BGH
45X2
CON019
SPORT0
DT0PRI
R72
0.00
1206
DT0SEC
TFS0
TSCLK0
4
P3
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
CON014
10X2
RSCLK0
ANALOG
DEVICES
RFS0
R80
0.00
1206
DR0SEC
DR0PRI
Approvals
Drawn
JSZ
Checked
Engineering
A
B
C
Date
Title
ADSP-BF561 EZ-KIT LITE:
20 Cotton Road
Nashua, NH 03063
4
PH: 1-800-ANALOGD
EXTENDER CARD CONNECTORS
10/10/03
Size
Board No.
C
Date
Rev
A0185-2003
1.3A
Sheet
5-12-2004_16:35
D
12
of
18
A
B
C
5V
F1
2.5A
FUS001
FER5
CHOKE_COIL
1
4
3
1
2
D3
2A
DO-214AA
UNREG_IN
3
INPUT
2
UNREG_IN
A3V
4
OUTPUT2
GND
1
1
2
FER6
600
1206
OUTPUT1
J7
D2
2A
DO-214AA
C160
1000PF
1206
A5V
R163
0.00
1206
VR1
D
R157
100K
1206
CT23
10UF
C
C122
0.1UF
805
ADP3339AKC-5
SOT-223
1
3V_B
VR3
CT24
10UF
C
C29
0.1UF
805
3
3
7.5V_POWER
CON005
2.5MM_JACK
R73
0.00
1206
2
OUTPUT1
4
OUTPUT2
INPUT
GND
1
FER16
600
1206
ADP3338AKC-33
SOT-223
C32
1UF
805
CT17
10UF
C
C35
0.1UF
805
C153
1000PF
1206
3.3V
NOTE: R252 or R253 gets populated
R83
0.00
805
Default is R252 IN and R253 OUT
DSP_VDD_EXT
R252
0.00
805
SHGND
DSP_VCORE
DSP_VDD_INT
TP7
DSP_VDD_EXT
UNREG_IN
DSP_3V_VOUT
VR6
3
INPUT
OUTPUT1
OUTPUT2
GND
1
2
CT20
10UF
C
R253
0.00
805
2
R84
0.00
805
U29
4
DNP
ADP3339AKC-33
SOT-223
C53
0.1UF
805
CT21
10UF
C
R195
3.32K
805
VROUT
L11
10UH
IND001
1
5
2
6
3
7
4
8
D7
2A
DO-214AA
3
1
NDS8434A
SO-8
R82
0.00
805
CT22
68UF
D
D5
ZHCS1000
SOT23D
1A
2
DSP_VDD_INT
C48
0.1UF
805
3.3V
UNREG_IN
D4
CMDSH-3
100MA
SOD-323
VR4
R78
10K
805
VR5
2
VIN
R79
0.00
805
5
SHDN
8
SYNC
4
GND
C43
2.2UF
805
L10
1.5UH
IND003
SW
IN2
R74
0.00
805
6
7
C46
2200PF
1206
D6
SL22
2A
DO-214AA
C169
4.7UF
805
1V2
2
OUT2
R75
53.6K
805
6
SD
5
FB
GND
4 ADP3336ARM
MSOP8
R77
0.00
805
C45
1UF
805
1
OUT1
2
OUT2
3
OUT3
5
FB
GND
4 ADP3336ARM
MSOP8
6
SD
C44
1UF
805
CT18
10UF
C
R48
76.8K
1206
C21
1UF
805
R76
1M
805
A1.8V
FER4
600
1206
VR2
7
IN1
8
IN2
R52
10K
805
DNP
3
R194
3.32K
805
R186
10.0K
1206
1
OUT1
OUT3
R180
17.4K
805
FB
VC
8
3
LT1765
SO-8
3
C170
0.18UF
805
1
BOOST
IN1
1.8V
R81
0.00
805
3.3V
7
3.3V
C24
1UF
805
R56
147K
1206
CT19
100UF
C
3
FER3
600
1206
MH2
MH1
MH3
MH4
MH5
3.3V
FPGA_1V8
TP8
TP5
TP11
TP10
TP6
TP4
TP9
R207
332K
805
SHGND
FER8
600
1206
VR7
2
6
INPUT
SD
3
ERR
R90
0.00
1206
1
OUTPUT
5
FB
C218
0.47UF
805
4
GND
4 ADP3331ART
SOT23-6
C230
0.47UF
805
R211
340K
805
SHGND
SHGND
ANALOG
DEVICES
R210
698K
805
Approvals
Drawn
JSZ
Checked
Engineering
A
B
C
Date
Title
ADSP-BF561 EZ-KIT LITE:
20 Cotton Road
Nashua, NH 03063
4
PH: 1-800-ANALOGD
POWER
10/10/03
Size
Board No.
C
Date
Rev
A0185-2003
1.3A
Sheet
5-12-2004_16:35
D
13
of
18
A
B
C
D
DSP_VDD_EXT
DSP_VDD_INT
1
1
C137
0.01UF
805
C140
0.01UF
805
C49
0.01UF
805
C174
0.01UF
805
3.3V
C30
0.1UF
805
C151
0.1UF
805
C179
0.1UF
805
3.3V
C126
0.1UF
805
C135
0.1UF
805
27MHZ OSC
U3
3.3V
C136
0.01UF
805
5V
C134
0.01UF
805
C168
0.01UF
805
C37
0.1UF
805
C31
10UF
1210
C50
10UF
1210
C47
10UF
1210
C173
0.01UF
805
C154
0.01UF
805
C145
0.1UF
805
C172
0.1UF
805
C178
0.1UF
805
C152
0.1UF
805
C157
0.01UF
805
C156
0.01UF
805
C183
0.1UF
805
C22
0.1UF
805
C138
0.01UF
805
C52
0.1UF
805
C164
0.1UF
805
C139
0.1UF
805
A5V
A5V
C107
0.22UF
805
A5V
C162
0.22UF
805
A5V
C143
0.22UF
805
A5V
C129
0.22UF
805
C184
0.1UF
805
C185
0.01UF
805
C186
0.01UF
805
C201
0.01UF
805
C104
0.22UF
805
AGND
AGND
AGND
AGND
AGND
AGND
AD8606
U16
AD8606
U17
AD8606
U18
AD8606
U19
AD8606
U20
3V_B
3.3V
3.3V
C200
0.01UF
805
C182
0.01UF
805
C20
0.1UF
805
C75
0.01UF
805
C85
0.1UF
805
C256
0.01UF
805
A5V
C125
0.22UF
805
74LVC14A
U10
C70
0.01UF
805
AGND
AGND
AD8606
U13
C83
0.1UF
805
AGND2
AGND2
AD8061
U24
3.3V
2
3.3V
AD8061
U23
3.3V
C106
0.22UF
805
AD8606
U12
A3V
AGND2
3.3V
C41
0.01UF
805
A5V
AD8061
U22
3.3V
C146
0.01UF
805
3.3V
A3V
C71
0.1UF
805
SN74AHC1G08
U21
C167
0.1UF
805
C180
0.01UF
805
A3V
3.3V
C177
0.1UF
805
74LVC00AD
U9
3.3V
AD8606
U15
C171
0.1UF
805
3.3V
SDRAM
U8
C108
0.22UF
805
AGND
C176
0.01UF
805
3.3V
ADSP-DM203
U1
A5V
C131
0.1UF
805
AD1836
U14
3
C51
0.1UF
805
M29W640D
U5
A5V
C19
0.1UF
805
C175
0.1UF
805
3.3V
IDT2305
U4
2
C155
0.1UF
805
C69
0.01UF
805
3.3V
C149
0.01UF
805
C150
0.01UF
805
ADG752
U25
3.3V
ADG752
U26
3
3.3V
DVDD_ADV7183
C101
0.01UF
805
C114
0.01UF
805
C91
0.1UF
805
C89
0.1UF
805
C102
0.1UF
805
C90
0.1UF
805
C109
0.1UF
805
C110
0.1UF
805
C113
0.01UF
805
ADV7179
U27
C112
0.01UF
805
C87
0.1UF
805
C111
0.1UF
805
C88
0.1UF
805
C249
0.01UF
805
ADM708SAR
U29
ADV7183
U28
C141
0.01UF
805
ADM3202
U30
C181
0.01UF
805
IDT74FCT3244APY
U31
C127
0.01UF
805
IDT74FCT3244APY
U36
C165
0.01UF
805
C166
0.01UF
805
ADG752
U40
ADG752
U45
C27
0.1UF
805
IDT2305
U46
C28
0.01UF
805
C132
0.1UF
805
39MHZ OSC
U54
3.3V
C189
0.1UF
805
4
C191
0.1UF
805
C202
0.01UF
805
C203
0.01UF
805
C190
0.01UF
805
C187
0.01UF
805
ANALOG
DEVICES
C188
0.01UF
805
Approvals
Drawn
JSZ
Checked
SDRAM
U53
Engineering
A
B
C
Date
Title
ADSP-BF561 EZ-KIT LITE:
20 Cotton Road
Nashua, NH 03063
4
PH: 1-800-ANALOGD
DECOUPLING CAPS
10/10/03
Size
Board No.
C
Date
Rev
A0185-2003
1.3A
Sheet
5-12-2004_16:35
D
14
of
18
A
B
C
D
All USB interface circuitry is considered propreitary andh has
been omitted from this schematic
When designin your JTAG interface please refer to the
Engineer to Engineer Note EE-68 which can be found at
http://www.analog.com
1
1
3.3V
U36
EMULATOR_TMS
YA
TMS
4
R87
0.00
805
I1A
EMULATOR_TCK
5
I0B
YB
7
TCK
6
USB_TCK
I1B
EMULATOR_TRST
11
I0C
YC
9
TRST
10
USB_TRST
R241
10K
805
I0A
3
USB_TMS
R239
10K
805
2
I1C
EMULATOR_TDI
14
I0D
YD
12
TDI
13
USB_TDI
I1D
1
S
15
E
3.3V
ADG774A
QSOP16
P4
2
1
2
3
4
5
6
7
8
9
10
11
12
13
14
2
R201
10K
805
U37
EMULATOR_EMU
USB_EMU
EMULATOR_TDO
IDC7X2
7X2
USB_TDO
2
I0A
YA
4
EMU
3
I1A
5
I0B
YB
7
TDO
6
I1B
11
I0C
YC
9
10
I1C
14
I0D
YD
12
13
I1D
DSP JTAG HEADER
1
S
15
E
ADG774A
QSOP16
3
3
3.3V
3.3V
C196
0.1UF
402
12.288MHz
3.3V
C195
0.1UF
402
ADG774A
C209
0.1UF
402
ADG774A
ANALOG
DEVICES
4
Approvals
Drawn
JSZ
Checked
Engineering
A
B
C
Date
Title
ADSP-BF561 EZ-KIT LITE:
20 Cotton Road
Nashua, NH 03063
4
PH: 1-800-ANALOGD
DEBUG AGENT - JTAG
10/10/03
Size
Board No.
C
Date
Rev
A0185-2003
1.3A
Sheet
12-11-2003_13:22
D
15
of
18
I
INDEX
A
C
AD1836A, audio codec, 1-10, 2-3, 2-12
address bus (A25-A2), 2-3
ADSP-BF561 processor
audio interface, see SPORT0
core voltage, 2-2
External Bus Interface Unit (EBIU), 2-3
external memory, 1-6
IO voltage, 2-2
parallel peripheral interfaces (PPIs), 2-6
peripheral ports, xii
SDRAM memory map, 1-7
see also input clock
ADV7179, video encoder, 1-11, 2-7, 2-10
ADV7183A, video decoder, 1-11, 2-8, 2-10
~AMS0, memory select pin, 1-7
ASYNC memory bank 0, 1-6
audio
applications, xii
connectors (J4, J5), 2-18
interface, see SPORT0
see AD1836A
clock
frequency, 1-8
PPI interfaces, 2-13
select switch (SW5), 2-13
source setup, 2-13
codecs, see AD1836A, ADV7179, ADV7183A
connectors, 1-3, 2-17
J1-3 (expansion interface), 2-9
J4-5 (audio), 2-18
J6 (video), 2-18
J7 (power), 2-18
J8 (USB), 2-19
P4 (JTAG), 2-9, 2-20
P9 (SPORT0), 2-20
RS232 (P2), 2-20
contents, EZ-KIT Lite package, 1-2
control bus, 2-3
customer support, xiv
cycle counters, 1-16
B
background telemetry channel (BTC), 1-13
bill of materials, A-1
boot mode switch (SW3), 2-11
D
D15-8 pins
PPI0, 1-9
PPI1, 1-9
data bus, 2-3, 2-6
default configuration, 1-3
DIP switches, 2-10
see also SW
disabling breakpoints in shared memory, 1-16
ADSP-BF561 EZ-KIT Lite Evaluation System Manual
I-1
INDEX
E
J
EBIU_SDBCTL register, 1-8, 1-9
EBIU_SDGCTL register, 1-8, 1-9
EBIU_SDRRC register, 1-8, 1-9
evaluation license restrictions, 1-6
example programs, 1-12
expansion
connectors (J3-1), 2-3
interface, 2-3, 2-8, 2-17
External Bus Interface Unit (EBIU), 2-3
external memory, 1-6, 2-9
EZ-KIT Lite board
architecture, 2-2
features, x
JTAG
connector (P4), 2-20
emulation port, 2-9
jumper settings, 1-3, 2-10
F
M
features, EZ-KIT Lite board, x
Field pin, 2-4
FIO0_FLAG_D register, 1-9
flag pins, see programmable flags (PFs)
flash
memory, xi, 2-3
ports PB39-P32, 2-16
ports PB47-P40, 2-16
flash programmer, 1-12
memory
external memory map, 1-6
select pins, see ~AMS0 &~SMS0
writes, 1-16
G
~OE (ADV7183A video decoder) signal, 2-10
opcode scan method, 1-16
general purpose IO, 1-9
graphical user interface (GUI), 1-13
H
Help, online, xix
HSYNC signal, 2-6, 2-7
I
input clock, 2-2, 2-6, 2-7
IO voltage, 2-2
I-2
L
LEDs, 1-3, 1-9, 2-14
J7 (power), 2-15
LED12-5, 2-5, 2-16
LED20-13, 2-5, 2-16
LED2-3, 2-15
LED4, 1-5, 2-16
N
notation conventions, xxi
O
P
P3 (SPORT) connector, 2-3
package contents, 1-2
Parallel Peripheral Interfaces (PPIs), xii, 1-11,
1-12, 2-6
clock select switch (SW5), 2-13
see also PPI0 and PPI1
PFs, see programmable flags
ADSP-BF561 EZ-KIT Lite Evaluation System Manual
INDEX
power
connector (J7), 2-18
specifications, 2-19
supply, 2-19
PPI0, 1-9, 1-11, 2-6, 2-8, 2-16
Clock, primary processor pin, 2-7
primary processor pins 7-0, 2-6
SYNC1, primary processor pin, 2-6
SYNC2, primary processor pin, 2-7
PPI1, 1-9, 2-6
Clock, primary processor pin, 2-7
primary processor pins 7-0, 2-6
SYNC1 signal, 2-7, 2-11
SYNC2 signal, 2-7, 2-11
video output, 2-7
primary processor pins (PPIs)
PPI0 Clock, 2-7
PPI0 SYNC1, 2-6
PPI0 SYNC2, 2-7
PPI1 Clock, 2-7
PPI1 SYNC1, 2-7
PPI1 SYNC2, 2-7
PPIs bits 7-0, 2-6
processor SDRAM map, see ADSP-BF561
processor
programmable flags (PFs), 2-4, 2-16
PF0-1, 1-12, 2-4
PF12-PF9, 2-5
PF13, 1-11, 2-5
PF14, 1-11, 2-5
PF15, 1-11, 2-5
PF16-19, 2-5
PF2, 1-12, 2-4, 2-10
PF20-31, 2-5
PF3, 2-4
PF39-32, 2-5
PF4, 1-10, 2-3, 2-4
PF47-40, 2-5
PF5-8, 1-9, 2-4, 2-12, 2-15
see also push buttons
push buttons, 1-9, 2-14
connecting to PF pins, 2-15
see also SW
R
registering, this product, 1-3
reset
cycle counters, 1-16
options, 1-14
processor, 2-15
push button (SW1), 2-14
RFS0, signal, 2-12
RSCLK0
register, 1-10
signals, 2-12
S
SDRAM, xi, 1-6, 1-7
default settings, 1-8
optimum settings, 1-9
SDRAM memory, 1-7
core MMRs, 1-7
data bank A SRAM, 1-7
data bank B SRAM, 1-7
instruction SRAM, 1-7
instruction SRAM/CACHE, 1-7
reserved, 1-7
scratch pad SRAM, 1-7
system MMRs, 1-7
serial
clock (SCL), 1-12
data (SDAT), 1-12
Serial Peripheral Interconnect (SPI), 2-3
setting target options, 1-14
~SMS0, memory select pin, 1-7
SPI interface, 2-4
SPORT0, xii, 1-10, 2-3, 2-12, 2-20
starting EZ-KIT Lite, 1-5
SW1, reset push button, 2-14
ADSP-BF561 EZ-KIT Lite Evaluation System Manual
I-3
INDEX
SW10-11, test DIP switches, 2-13
SW2, video config switch, 1-11, 2-6, 2-7, 2-8,
2-10
SW3, boot mode switch, 2-10, 2-11
SW4, enable push button, 1-10, 2-12, 2-15
SW5, clock select switch, 2-6, 2-13
SW6-9, general input push buttons, 2-4, 2-12,
2-15
synchronization (SYNC1-2) signals, 2-6
system
architecture, EZ-KIT Lite board, 2-2
U
UART, xi, xii, 2-5, 2-8
USB
cable, 1-3
connector (P7), 2-19, 2-20
interface, 2-9
interface chip (U34), 2-14, 2-15
monitor LED (LED4), 2-16
user LEDs
LED12-5, 2-16
LED20-13, 2-16
see also LEDs
T
target options
miscellaneous, 1-15
on emulator exit, 1-14
reset, 1-14
XML file, 1-15
Target Options dialog box, 1-14
test DIP switches (SW10, SW11), 2-13
TFS0, signal, 2-12
time-division multiplexed (TDM) mode, 1-10
Timer 0-6, 2-4
Timer 1, 2-4
Timer 10, 2-7
Timer 11, 2-7
Timer 2, 2-4
Timer 3, 2-4
Timer 4, 2-4
Timer 5, 2-4
Timer 6, 2-4
Timer 8, 2-6
Timer 9, 2-7
TSCLK0
register, 1-10
signal, 2-12
two-wire interface (TWI) mode, 1-10, 2-12
I-4
V
video, 1-11
blanking control, 2-7
configuration switch (SW2), 2-10
connecting to PPI, xii
connector (J6), 2-18
encoder/decoder, xii
input mode, 2-8
interface, 1-11
output mode, 2-7
VisualDSP++
documentation, xx
online Help, xix
session, 1-7
VSYNC signal, 2-7
X
XML
file version, 1-15
parser version, 1-15
register reset values, 1-16
ADSP-BF561 EZ-KIT Lite Evaluation System Manual