14-Bit, 20 MSPS/40 MSPS/65 MSPS
Dual A/D Converter
AD9248
FUNCTIONAL BLOCK DIAGRAM
FEATURES
AVDD
AGND
OTR_A
VIN+_A
14
SHA
14
ADC
OUTPUT
MUX/
BUFFERS
VIN–_A
REFT_A
CLOCK
DUTY CYCLE
STABILIZER
VREF
GENERAL DESCRIPTION
The AD9248 is a dual, 3 V, 14-bit, 20 MSPS/40 MSPS/65 MSPS
analog-to-digital converter (ADC). It features dual high
performance sample-and hold amplifiers (SHAs) and an
integrated voltage reference. The AD9248 uses a multistage
differential pipelined architecture with output error correction
logic to provide 14-bit accuracy and to guarantee no missing
codes over the full operating temperature range at up to
65 MSPS data rates. The wide bandwidth, differential SHA
allows for a variety of user-selectable input ranges and offsets,
including single-ended applications. It is suitable for various
applications, including multiplexed systems that switch fullscale voltage levels in successive channels and for sampling
inputs at frequencies well beyond the Nyquist rate.
Dual single-ended clock inputs are used to control all internal
conversion cycles. A duty cycle stabilizer is available and can
compensate for wide variations in the clock duty cycle, allowing
the converter to maintain excellent performance. The digital
output data is presented in either straight binary or twos
complement format. Out-of-range signals indicate an overflow
condition, which can be used with the most significant bit to
determine low or high overflow.
CLK_A
CLK_B
DCS
SENSE
AGND
SHARED_REF
0.5V
MODE
CONTROL
PWDN_A
PWDN_B
DFS
REFB_B
OTR_B
VIN+_B
Ultrasound equipment
Direct conversion or IF sampling receivers
WB-CDMA, CDMA2000, WiMAX
Battery-powered instruments
Hand-held scopemeters
Low cost digital oscilloscopes
OEB_A
MUX_SELECT
REFB_A
REFT_B
APPLICATIONS
D13_A TO D0_A
SHA
ADC
14
VIN–_B
OUTPUT 14
MUX/
BUFFERS
D13_B TO D0_B
OEB_B
AD9248
DRVDD DRGND
04446-001
Integrated dual 14-bit ADC
Single 3 V supply operation (2.7 V to 3.6 V)
SNR = 71.6 dB (to Nyquist, AD9248-65)
SFDR = 80.5 dBc (to Nyquist, AD9248-65)
Low power: 300 mW/channel at 65 MSPS
Differential input with 500 MHz, 3 dB bandwidth
Exceptional crosstalk immunity > 85 dB
Flexible analog input: 1 V p-p to 2 V p-p range
Offset binary or twos complement data format
Clock duty cycle stabilizer
Output datamux option
Figure 1.
Fabricated on an advanced CMOS process, the AD9248 is
available in a Pb-free, space saving, 64-lead LQFP or LFCSP and
is specified over the industrial temperature range (−40°C to
+85°C).
PRODUCT HIGHLIGHTS
1. Pin-compatible with the AD9238, 12-bit 20 MSPS/
40 MSPS/65 MSPS ADC.
2. Speed grade options of 20 MSPS, 40 MSPS, and 65 MSPS
allow flexibility between power, cost, and performance to suit
an application.
3. Low power consumption: AD9248-65: 65 MSPS = 600 mW,
AD9248-40: 40 MSPS = 330 mW, and AD9248-20: 20 MSPS =
180 mW.
4. Typical channel isolation of 85 dB @ fIN = 10 MHz.
5. The clock duty cycle stabilizer (AD9248-20/AD9248-40/
AD9248-65) maintains performance over a wide range of
clock duty cycles.
6. Multiplexed data output option enables single-port operation
from either Data Port A or Data Port B.
Rev. B
Information furnished by Analog Devices is believed to be accurate and reliable.
However, no responsibility is assumed by Analog Devices for its use, nor for any
infringements of patents or other rights of third parties that may result from its use.
Specifications subject to change without notice. No license is granted by implication
or otherwise under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.461.3113 ©2005–2010 Analog Devices, Inc. All rights reserved.
AD9248
TABLE OF CONTENTS
Specifications..................................................................................... 3 Clock Circuitry ........................................................................... 22 DC Specifications ......................................................................... 3 Analog Inputs ............................................................................. 22 AC Specifications.......................................................................... 5 Reference Circuitry .................................................................... 22 Digital Specifications ................................................................... 6 Digital Control Logic ................................................................. 22 Switching Specifications .............................................................. 7 Outputs ........................................................................................ 22 Absolute Maximum Ratings ............................................................ 8 LQFP Evaluation Board Bill of Materials (BOM) .................. 24 Explanation of Test Levels ........................................................... 8 LQFP Evaluation Board Schematics ........................................ 25 ESD Caution .................................................................................. 8 LQFP PCB Layers ....................................................................... 29 Pin Configurations and Function Descriptions ........................... 9 Dual ADC LFCSP PCB .................................................................. 35 Terminology .................................................................................... 11 Power Connector........................................................................ 35 Typical Performance Characteristics ........................................... 12 Analog Inputs ............................................................................. 35 Equivalent Circuits ......................................................................... 16 Optional Operational Amplifier .............................................. 35 Theory of Operation ...................................................................... 17 Clock ............................................................................................ 35 Analog Input ............................................................................... 17 Voltage Reference ....................................................................... 35 Clock Input and Considerations .............................................. 18 Data Outputs ............................................................................... 35 Power Dissipation and Standby Mode ..................................... 19 LFCSP Evaluation Board Bill of Materials (BOM) ................ 36 Digital Outputs ........................................................................... 19 LFCSP PCB Schematics ............................................................. 37 Timing.......................................................................................... 19 LFCSP PCB Layers ..................................................................... 40 Data Format ................................................................................ 20 Thermal Considerations............................................................ 45 Voltage Reference ....................................................................... 20 Outline Dimensions ....................................................................... 46 AD9248 LQFP Evaluation Board ................................................. 22 Ordering Guide .......................................................................... 47 REVISION HISTORY
11/10—Rev. A to Rev. B
Changes to Absolute Maximum Ratings Section ......................... 8
Changes to Figure 3 .......................................................................... 9
Add Figure 4; Renumbered Sequentially ....................................... 9
Changes to Theory of Operation Section and Analog Input
Section .............................................................................................. 17
Deleted Note 1 from Dual ADC LFCSP PCB Section ............... 35
Updated Outline Dimensions ....................................................... 46
3/05—Rev. 0 to Rev. A
Added LFCSP ...................................................................... Universal
Changes to Features.......................................................................... 1
Changes to Applications .................................................................. 1
Changes to General Description .................................................... 1
Changes to Product Highlights....................................................... 1
Changes to Table 6 .......................................................................... 10
Changes to Terminology ............................................................... 11
Changes to Figure 22...................................................................... 15
Changes to Clock Input and Considerations Section ................ 18
Changes to Timing Section ........................................................... 19
Changes to Figure 33...................................................................... 19
Changes to Data Format Section .................................................. 20
Changes to Table 10 ....................................................................... 24
Changes to Figure 39...................................................................... 25
Changes to Table 13 ....................................................................... 36
Updated Outline Dimensions ....................................................... 46
Changes to Ordering Guide .......................................................... 47
1/05—Revision 0: Initial Version
Rev. B | Page 2 of 48
AD9248
SPECIFICATIONS
DC SPECIFICATIONS
AVDD = 3 V, DRVDD = 2.5 V, maximum sample rate, CLK_A = CLK_B; AIN = −0.5 dBFS differential input, 1.0 V internal reference,
TMIN to TMAX, DCS enabled, unless otherwise noted.
Table 1.
Parameter
RESOLUTION
ACCURACY
No Missing Codes Guaranteed
Offset Error
Gain Error 1
Differential Nonlinearity (DNL) 2
Integral Nonlinearity (INL)2
TEMPERATURE DRIFT
Offset Error
Gain Error1
INTERNAL VOLTAGE REFERENCE
Output Voltage Error (1 V Mode)
Load Regulation @ 1.0 mA
Output Voltage Error (0.5 V Mode)
Load Regulation @ 0.5 mA
INPUT REFERRED NOISE
Input Span = 1 V
Input Span = 2.0 V
ANALOG INPUT
Input Span = 1.0 V
Input Span = 2.0 V
Input Capacitance 3
REFERENCE INPUT RESISTANCE
POWER SUPPLIES
Supply Voltages
AVDD
DRVDD
Supply Current
IAVDD2
IDRVDD2
PSRR
POWER CONSUMPTION
DC Input 4
Sine Wave Input2
Standby Power 5
Temp
Full
Test
Level
VI
AD9248BST/BCP-20
Min Typ
Max
14
AD9248BST/BCP-40
Min Typ
Max
14
AD9248BST/BCP-65
Min Typ
Max
14
Full
25°C
Full
Full
25°C
Full
25°C
VI
I
IV
V
IV
V
IV
14
14
14
Full
Full
V
V
±2
±12
Full
Full
Full
Full
VI
V
V
V
±5
0.8
±2.5
0.1
25°C
25°C
V
V
2.1
1.05
2.1
1.05
2.1
1.05
LSB rms
LSB rms
Full
Full
Full
Full
IV
IV
V
V
1
2
7
7
1
2
7
7
1
2
7
7
V p-p
V p-p
pF
kΩ
Full
Full
IV
IV
Full
Full
Full
V
V
V
60
5
±0.01
Full
Full
Full
V
VI
V
180
190
2.0
±0.2
±0.25
±0.65
±0.6
±2.7
±2.3
2.7
2.25
3.0
3.0
±1.3
±2.2
±0.2
±0.3
±0.65
±0.6
±2.7
±2.3
±1.0
±4.5
±1.3
±2.4
±0.2
±0.5
±0.7
±0.65
±2.8
±2.4
±1.0
±4.5
±2
±12
±35
3.6
3.6
±5
0.8
±2.5
0.1
2.7
2.25
3.0
3.0
Rev. B | Page 3 of 48
330
360
2.0
±1.0
±4.5
±3
±12
±35
3.6
3.6
110
11
±0.01
217
±1.3
±2.5
±5
0.8
±2.5
0.1
2.7
2.25
3.0
3.0
600
640
2.0
Bits
% FSR
% FSR
LSB
LSB
LSB
LSB
ppm/°C
ppm/°C
±35
3.6
3.6
200
16
±0.01
400
Unit
Bits
mV
mV
mV
mV
V
V
mA
mA
% FSR
700
mW
mW
mW
AD9248
Parameter
MATCHING CHARACTERISTICS
Offset Error
(Nonshared Reference Mode)
Offset Error
(Shared Reference Mode)
Gain Error
(Nonshared Reference Mode)
Gain Error
(Shared Reference Mode)
Temp
Test
Level
AD9248BST/BCP-20
Min Typ
Max
AD9248BST/BCP-40
Min Typ
Max
AD9248BST/BCP-65
Min Typ
Max
25°C
I
±0.19
±1.56
±0.19
±1.56
±0.25
±1.74
% FSR
25°C
I
±0.19
±1.56
±0.19
±1.56
±0.25
±1.74
% FSR
25°C
I
±0.07
±1.43
±0.07
±1.43
±0.07
±1.47
% FSR
25°C
I
±0.01
±0.06
±0.01
±0.06
±0.01
±0.10
% FSR
1
Unit
Gain error and gain temperature coefficient are based on the ADC only (with a fixed 1.0 V external reference).
Measured at maximum clock rate with a low frequency sine wave input and approximately 5 pF loading on each output bit.
Input capacitance refers to the effective capacitance between one differential input pin and AVSS. Refer to Figure 29 for the equivalent analog input structure.
4
Measured with dc input at maximum clock rate.
5
Standby power is measured with the CLK_A and CLK_B pins inactive (that is, set to AVDD or AGND).
2
3
Rev. B | Page 4 of 48
AD9248
AC SPECIFICATIONS
AVDD = 3 V, DRVDD = 2.5 V, maximum sample rate, CLK_A = CLK_B; AIN = −0.5 dBFS differential input, 1.0 V external reference,
TMIN to TMAX, DCS Enabled, unless otherwise noted.
Table 2.
Parameter
SIGNAL-TO-NOISE RATIO (SNR)
fINPUT = 2.4 MHz
fINPUT = 9.7 MHz
fINPUT = 19.6 MHz
fINPUT = 35 MHz
fINPUT = 100 MHz
SIGNAL-TO-NOISE AND DISTORTION
RATIO (SINAD)
fINPUT = 2.4 MHz
fINPUT = 9.7 MHz
fINPUT = 19.6 MHz
fINPUT = 35 MHz
fINPUT = 100 MHz
EFFECTIVE NUMBER OF BITS (ENOB)
fINPUT = 2.4 MHz
fINPUT = 9.7 MHz
fINPUT = 19.6 MHz
fINPUT = 35 MHz
fINPUT = 100 MHz
WORST HARMONIC (SECOND or THIRD)
fINPUT = 2.4 MHz
fINPUT = 9.7 MHz
fINPUT = 19.6 MHz
fINPUT = 35 MHz
Temp
Test
Level
Full
25°C
Full
25°C
Full
25°C
Full
25°C
25°C
V
IV
V
IV
V
IV
V
IV
V
Full
25°C
Full
25°C
Full
25°C
Full
25°C
25°C
V
IV
V
IV
V
IV
V
IV
V
Full
25°C
Full
25°C
Full
25°C
Full
25°C
25°C
V
IV
V
IV
V
IV
V
IV
V
Full
25°C
Full
25°C
Full
25°C
Full
25°C
V
IV
V
I
V
I
V
I
AD9248BST/BCP-20
Min Typ
Max
73.1
72.4
73.4
73.7
72.9
73.1
AD9248BST/BCP-40
Min Typ
Max
72.8
73.1
73.4
72.3
72.7
72.9
AD9248BST/BCP-65
Min Typ
Max
72.3
71.2
70
72.2
70.9
73.0
73.2
72.0
72.2
69.5
72.0
72.8
73.0
71.0
72.1
72.3
71.7
70.0
69.5
11.7
11.5
11.8
11.8
11.7
11.7
69.0
11.7
11.8
11.8
11.5
11.7
11.7
11.6
11.3
11.3
77.5
76.1
86.0
87.5
83.0
84.0
Rev. B | Page 5 of 48
11.2
77.5
85.0
86.0
76.0
83.0
84.0
72.8
73.1
71.5
71.6
69.0
72.5
72.7
70.9
71.0
68.5
11.8
11.8
11.5
11.5
11.2
77.5
84.0
86.0
73.0
80.0
80.5
Unit
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
Bits
Bits
Bits
Bits
Bits
Bits
Bits
Bits
Bits
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
AD9248
Parameter
WORST OTHER SPUR
(NONSECOND or THIRD)
fINPUT = 2.4 MHz
fINPUT = 9.7 MHz
fINPUT = 19.6 MHz
fINPUT = 35 MHz
fINPUT = 100 MHz
SPURIOUS-FREE DYNAMIC RANGE (SFDR)
fINPUT = 2.4 MHz
fINPUT = 9.7 MHz
fINPUT = 19.6 MHz
fINPUT = 35 MHz
CROSSTALK
Temp
Test
Level
Full
25°C
Full
25°C
Full
25°C
Full
25°C
25°C
V
I
V
I
V
I
V
I
V
Full
25°C
Full
25°C
Full
25°C
Full
25°C
Full
V
IV
V
I
V
I
V
I
V
AD9248BST/BCP-20
Min Typ
Max
83.3
83.1
88.0
89.0
87.0
88.0
AD9248BST/BCP-40
Min Typ
Max
83.5
88.0
89.0
82.6
88.0
88.5
AD9248BST/BCP-65
Min Typ
Max
81.0
79.8
79.0
77.5
86.0
87.5
83.0
76.1
81.0
77.5
85.0
86.0
76.0
83.0
84.0
77.5
85.5
86.0
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
85.5
86.0
75.0
84.0
86.0
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dB
84.0
73.0
−85.0
−85.0
Unit
80.0
80.5
−85.0
DIGITAL SPECIFICATIONS
AVDD = 3 V, DRVDD = 2.5 V, maximum sample rate, CLK_A = CLK_B; AIN = −0.5 dBFS differential input, 1.0 V internal reference,
TMIN to TMAX, DCS enabled, unless otherwise noted.
Table 3.
Parameter
LOGIC INPUTS
High Level Input Voltage
Low Level Input Voltage
High Level Input Current
Low Level Input Current
Input Capacitance
LOGIC OUTPUTS 1
High Level Output Voltage
Temp
Test
Level
AD9248BST/BCP-20
Min
Typ Max
Min
Full
Full
Full
Full
Full
IV
IV
IV
IV
IV
2.0
2.0
Full
IV
Low Level Output Voltage
Full
IV
1
0.8
+10
+10
−10
−10
AD9248BST-40
Typ Max
AD9248BST-65
Typ Max
2.0
0.8
+10
+10
−10
−10
2
Min
−10
−10
2
DRVDD −
0.05
2
DRVDD −
0.05
0.05
Output voltage levels measured with capacitive load only on each output.
Rev. B | Page 6 of 48
0.8
+10
+10
V
V
μA
μA
pF
V
DRVDD −
0.05
0.05
Unit
0.05
V
AD9248
SWITCHING SPECIFICATIONS
AVDD = 3 V, DRVDD = 2.5 V, maximum sample rate, CLK_A = CLK_B; AIN = −0.5 dBFS differential input, 1.0 V internal reference,
TMIN to TMAX, DCS enabled, unless otherwise noted.
Table 4.
Parameter
SWITCHING PERFORMANCE
Maximum Conversion Rate
Minimum Conversion Rate
CLK Period
CLK Pulse-Width High 1
CLK Pulse-Width Low1
DATA OUTPUT PARAMETER
Output Delay 2 (tPD)
Pipeline Delay (Latency)
Aperture Delay (tA)
Aperture Uncertainty (tJ)
Wake-Up Time 3
OUT-OF-RANGE RECOVERY TIME
2
3
AD9248BST/BCP-20
Min
Typ
Max
AD9248BST/BCP-40
Min
Typ
Max
AD9248BST/BCP-65
Min
Typ
Max
Full
Full
Full
Full
Full
VI
V
V
V
V
20
40
65
Full
Full
Full
Full
Full
Full
VI
V
V
V
V
V
1
1
50.0
15.0
15.0
2
6
MSPS
MSPS
ns
ns
ns
1
25.0
8.8
8.8
3.5
7
1.0
0.5
2.5
2
Unit
15.4
6.2
6.2
2
3.5
7
1.0
0.5
2.5
2
6
2
3.5
7
1.0
0.5
2.5
2
6
ns
Cycles
ns
ps rms
ms
Cycles
The AD9248-65 model has a duty cycle stabilizer circuit that, when enabled, corrects for a wide range of duty cycles (see Figure 24).
Output delay is measured from clock 50% transition to data 50% transition, with a 5 pF load on each output.
Wake-up time is dependent on the value of the decoupling capacitors; typical values shown with 0.1 μF and 10 μF capacitors on REFT and REFB.
N
N+1
N+8
N+2
N+3
N–1
ANALOG
INPUT
N+7
N+4
N+5
N+6
CLOCK
DATA
OUT
N–9
N–8
N–7
N–6
N–5
N–4
N–3
N–2
N–1
N
tPD = MIN 2.0ns,
MAX 6.0ns
Figure 2. Timing Diagram
Rev. B | Page 7 of 48
04446-002
1
Temp
Test
Level
AD9248
ABSOLUTE MAXIMUM RATINGS
Absolute maximum ratings are limiting values to be applied
individually, and beyond which the serviceability of the circuit
may be impaired. Functional operability is not necessarily implied.
Exposure to absolute maximum rating conditions for an extended
period may affect device reliability.
EXPLANATION OF TEST LEVELS
I
II
III
IV
Table 5.
Parameter
ELECTRICAL
AVDD to AGND
DRVDD to DRGND
AGND to DRGND
AVDD to DRVDD
Digital Outputs to DRGND
OEB, DFS, CLK, DCS, MUX_SELECT,
SHARED_REF to AGND
VINA, VINB to AGND
VREF to AGND
SENSE to AGND
REFB, REFT to AGND
PDWN to AGND
ENVIRONMENTAL1
Operating Temperature
Junction Temperature
Lead Temperature (10 sec)
Storage Temperature
1
Rating
V
VI
−0.3 V to +3.9 V
−0.3 V to +3.9 V
−0.3 V to +0.3 V
−3.9 V to +3.9 V
−0.3 V to DRVDD + 0.3 V
−0.3 V to AVDD + 0.3 V
100% production tested.
100% production tested at 25°C and sample tested at
specified temperatures.
Sample tested only.
Parameter is guaranteed by design and characterization
testing.
Parameter is a typical value only.
100% production tested at 25°C; guaranteed by design and
characterization testing for industrial temperature range;
100% production tested at temperature extremes for
military devices.
ESD CAUTION
−0.3 V to AVDD + 0.3 V
−0.3 V to AVDD + 0.3 V
−0.3 V to AVDD + 0.3 V
−0.3 V to AVDD + 0.3 V
−0.3 V to AVDD + 0.3 V
−40°C to +85°C
150°C
300°C
−65°C to +150°C
Typical thermal impedances: 64-lead LQFP, θJA = 54°C/W; 64-lead LFCSP, θJA
= 26.4°C/W with heat slug soldered to ground plane. These measurements
were taken on a 4-layer board in still air, in accordance with EIA/JESD51-7.
Rev. B | Page 8 of 48
AD9248
64 63 62 61 60 59 58
D7_A
D8_A
D9_A
DRVDD
DRGND
D10_A
D11_A
D12_A
D13_A (MSB)
OTR_A
OEB_A
PDWN_A
MUX_SELECT
SHARED_REF
CLK_A
AVDD
PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS
57 56 55 54 53 52 51 50 49
AGND 1
48 D6_A
PIN 1
VIN+_A 2
47 D5_A
VIN–_A 3
46 D4_A
AGND 4
45 D3_A
AVDD 5
44 D2_A
REFT_A 6
43 D1_A
AD9248
REFB_A 7
42 D0_A (LSB)
64-LEAD LQFP
TOP VIEW
(Not to Scale)
VREF 8
SENSE 9
41 DRVDD
40 DRGND
REFB_B 10
39 OTR_B
REFT_B 11
38 D13_B (MSB)
AVDD 12
37 D12_B
AGND 13
36 D11_B
VIN–_B 14
35 D10_B
VIN+_B 15
34 D9_B
AGND 16
33 D8_B
04446-003
D7_B
D6_B
D5_B
DRVDD
DRGND
D4_B
D3_B
D2_B
D1_B
D0_B (LSB)
OEB_B
PDWN_B
DFS
DCS
AVDD
CLK_B
17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
AVDD
CLK_A
SHARED_REF
MUX_SELECT
PDWN_A
OEB_A
OTR_A
D13_A (MSB)
D12_A
D11_A
D10_A
DRGND
DRVDD
D9_A
D8_A
D7_A
Figure 3. 64-Lead LQFP Pin Configuration
PIN 1
INDICATOR
AD9248
64-LEAD LFCSP
TOP VIEW
(Not to Scale)
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
D6_A
D5_A
D4_A
D3_A
D2_A
D1_A
D0_A (LSB)
DRVDD
DRGND
OTR_B
D13_B (MSB)
D12_B
D11_B
D10_B
D9_B
D8_B
NOTES
1. THERE IS AN EXPOSED PAD THAT MUST CONNECT TO AGND.
Figure 4. 64-Lead LFCSP Pin Configuration
Rev. B | Page 9 of 48
04446-103
AVDD
CLK_B
DCS
DFS
PDWN_B
OEB_B
D0_B (LSB)
D1_B
D2_B
D3_B
D4_B
DRGND
DRVDD
D5_B
D6_B
D7_B
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
AGND 1
VIN+_A 2
VIN–_A 3
AGND 4
AVDD 5
REFT_A 6
REFB_A 7
VREF 8
SENSE 9
REFB_B 10
REFT_B 11
AVDD 12
AGND 13
VIN–_B 14
VIN+_B 15
AGND 16
AD9248
Table 6. 64-Lead LQFP and 64-Lead LFCSP Pin Function Descriptions
Pin No.
1, 4, 13, 16
2
3
5, 12, 17, 64
6
7
8
9
10
11
14
15
18
19
20
21
Mnemonic
AGND
VIN+_A
VIN−_A
AVDD
REFT_A
REFB_A
VREF
SENSE
REFB_B
REFT_B
VIN−_B
VIN+_B
CLK_B
DCS
DFS
PDWN_B
22
OEB_B
23 to 27,
30 to 38
28, 40, 53
29, 41, 52
D0_B (LSB) to
D13_B (MSB)
DRGND
DRVDD
39
42 to 51,
54 to 57
58
59
OTR_B
D0_A (LSB) to
D13_A (MSB)
OTR_A
OEB_A
60
PDWN_A
61
MUX_SELECT
62
63
SHARED_REF
CLK_A
EP
Description
Analog Ground.
Analog Input Pin (+) for Channel A.
Analog Input Pin (−) for Channel A.
Analog Power Supply.
Differential Reference (+) for Channel A.
Differential Reference (−) for Channel A.
Voltage Reference Input/Output.
Reference Mode Selection.
Differential Reference (−) for Channel B.
Differential Reference (+) for Channel B.
Analog Input Pin (−) for Channel B.
Analog Input Pin (+) for Channel B.
Clock Input Pin for Channel B.
Enable Duty Cycle Stabilizer (DCS) Mode.
Data Output Format Select Pin (Low for Offset Binary, High for Twos Complement).
Power-Down Function Selection for Channel B.
Logic 0 enables Channel B. Logic 1 powers down Channel B (outputs static, not High-Z).
Output Enable Pin for Channel B.
Logic 0 enables Data Bus B. Logic 1 sets outputs to High-Z.
Channel B Data Output Bits.
Digital Output Ground.
Digital Output Driver Supply. Must be decoupled to DRGND with a minimum 0.1 μF capacitor.
Recommended decoupling is 0.1 μF capacitor in parallel with 10 μF capacitor.
Out-of-Range Indicator for Channel B.
Channel A Data Output Bits.
Out-of-Range Indicator for Channel A.
Output Enable Pin for Channel A.
Logic 0 enables Data Bus A. Logic 1 sets outputs to High-Z.
Power-Down Function Selection for Channel A.
Logic 0 enables Channel A. Logic 1 powers down Channel A (outputs static, not High-Z).
Data Multiplexed Mode.
(See Data Format section for how to enable; high setting disables output data multiplexed mode.)
Shared Reference Control Pin (Low for Independent Reference Mode, High for Shared Reference Mode).
Clock Input Pin for Channel A.
For the 64-Lead LFCSP only, there is an exposed pad that must connect to AGND.
Rev. B | Page 10 of 48
AD9248
TERMINOLOGY
Aperture Delay
SHA performance measured from the rising edge of the clock
input to when the input signal is held for conversion.
Aperture Jitter
The variation in aperture delay for successive samples, which is
manifested as noise on the input to the ADC.
Integral Nonlinearity (INL)
Deviation of each individual code from a line drawn from
negative full scale through positive full scale. The point used as
negative full scale occurs ½ LSB before the first code transition.
Positive full scale is defined as a level 1½ LSB beyond the last
code transition. The deviation is measured from the middle of
each particular code to the true straight line.
Differential Nonlinearity (DNL, No Missing Codes)
An ideal ADC exhibits code transitions that are exactly 1 LSB
apart. DNL is the deviation from this ideal value. Guaranteed
no missing codes to 14-bit resolution indicates that all 16,384
codes must be present over all operating ranges.
Offset Error
The major carry transition should occur for an analog value
½ LSB below VIN+ = VIN−. Offset error is defined as the
deviation of the actual transition from that point.
Gain Error
The first code transition should occur at an analog value ½ LSB
above negative full scale. The last transition should occur at an
analog value 1½ LSB below the nominal full scale. Gain error is
the deviation of the actual difference between first and last code
transitions and the ideal difference between first and last code
transitions.
Temperature Drift
The temperature drift for zero error and gain error specifies the
maximum change from the initial (25°C) value to the value at
TMIN or TMAX.
Power Supply Rejection
The specification shows the maximum change in full scale from
the value with the supply at the minimum limit to the value
with the supply at its maximum limit.
Total Harmonic Distortion (THD)
The ratio of the rms sum of the first six harmonic components
to the rms value of the measured input signal, expressed as a
percentage or in decibels relative to the peak carrier signal (dBc).
Signal-to-Noise and Distortion (SINAD) Ratio
The ratio of the rms value of the measured input signal to the
rms sum of all other spectral components below the Nyquist
frequency, including harmonics but excluding dc. The value for
SINAD is expressed dB.
Effective Number of Bits (ENOB)
Using the following formula
ENOB = (SINAD − 1.76)/6.02
ENOB for a device for sine wave inputs at a given input
frequency can be calculated directly from its measured SINAD.
Signal-to-Noise Ratio (SNR)
The ratio of the rms value of the measured input signal to the
rms sum of all other spectral components below the Nyquist
frequency, excluding the first six harmonics and dc. The value
for SNR is expressed in dB.
Spurious-Free Dynamic Range (SFDR)
The difference in dB between the rms amplitude of the input
signal and the peak spurious signal.
Nyquist Sampling
When the frequency components of the analog input are below
the Nyquist frequency (fCLOCK/2), this is often referred to as
Nyquist sampling.
IF Sampling
Due to the effects of aliasing, an ADC is not limited to Nyquist
sampling. Higher sampled frequencies are aliased down into the
first Nyquist zone (DC − fCLOCK/2) on the output of the ADC.
The bandwidth of the sampled signal should not overlap
Nyquist zones and alias onto itself. Nyquist sampling
performance is limited by the bandwidth of the input SHA and
clock jitter (jitter adds more noise at higher input frequencies).
Two-Tone SFDR
The ratio of the rms value of either input tone to the rms value
of the peak spurious component. The peak spurious component
may or may not be an IMD product.
Out-of-Range Recovery Time
The time it takes for the ADC to reacquire the analog input
after a transient from 10% above positive full scale to 10% above
negative full scale, or from 10% below negative full scale to 10%
below positive full scale.
Crosstalk
Coupling onto one channel being driven by a (−0.5 dBFS) signal
when the adjacent interfering channel is driven by a full-scale
signal. Measurement includes all spurs resulting from both
direct coupling and mixing components.
Rev. B | Page 11 of 48
AD9248
TYPICAL PERFORMANCE CHARACTERISTICS
AVDD, DRVDD = 3.0 V, T = 25°C, AIN differential drive, full scale = 2 V, unless otherwise noted.
0
100
SNR = 72.6dB
SINAD = 71.9dB
H2 = –81.5dBc
H3 = –86.8dBc
SFDR = 81.5dB
95
90
SFDR
85
–40
SFDR/SNR (dBc)
–60
THIRD
HARMONIC
–80
80
75
SECOND
HARMONIC
CROSSTALK
SNR
70
65
60
04446-060
–100
–120
0
5
10
15
20
25
04446-007
MAGNITUDE (dBFS)
–20
55
50
30
40
45
50
FREQUENCY (MHz)
Figure 5. Single-Tone FFT of Channel A Digitizing fIN = 12.5 MHz
While Channel B Is Digitizing fIN = 10 MHz
60
65
Figure 8. AD9248-65 Single-Tone SFDR/SNR vs. FS with fIN = 32.5 MHz
0
100
SNR = 70.5dB
SINAD = 69.4dB
H2 = –92.3dBc
H3 = –80.1dBc
SFDR = 80.1dBc
–20
95
90
SFDR
SNR
85
–40
SFDR/SNR (dBc)
MAGNITUDE (dBFS)
55
ADC SAMPLE RATE (MSPS)
–60
SECOND
HARMONIC
THIRD HARMONIC
–80
80
75
SNR
70
65
CROSSTALK
04446-061
–120
0
5
10
15
20
25
55
50
20
30
25
30
40
35
FREQUENCY (MHz)
ADC SAMPLE RATE (MSPS)
Figure 6. Single-Tone FFT of Channel A Digitizing fIN = 70 MHz
While Channel B Is Digitizing fIN = 76 MHz
Figure 9. AD9248-40 Single-Tone SFDR/SNR vs. FS with fIN = 20 MHz
100
0
SNR = 68.1dB
SINAD = 68.0dB
H2 = –83.4dBc
H3 = –83.1dBc
SFDR = 75.1dBc
–20
95
90
SFDR
SFDR/SNR (dBc)
85
–40
–60
SECOND HARMONIC
CROSSTALK
80
75
SNR
70
–80
65
–120
0
5
10
15
20
25
04446-009
60
–100
55
04446-062
MAGNITUDE (dBFS)
04446-008
60
–100
50
0
30
5
10
15
20
ADC SAMPLE RATE (MSPS)
FREQUENCY (MHz)
Figure 7. Single-Tone FFT of Channel A Digitizing fIN = 120 MHz
While Channel B Is Digitizing fIN = 126 MHz
Figure 10. AD9248-20 Single-Tone SFDR/SNR vs. FS with fIN = 10 MHz
Rev. B | Page 12 of 48
AD9248
100
95
90
90
80
SFDR/SNR (dBc)
SFDR/SNR (dBc)
SFDR
SNR
70
SNR
60
85
SNR
SFDR
80
75
SNR
–30
–25
–20
–15
–10
–5
04446-013
40
–35
70
04446-010
50
65
0
0
20
INPUT AMPLITUDE (dBFS)
40
60
80
100
120
140
INPUT FREQUENCY (MHz)
Figure 11. AD9248-65 Single-Tone SFDR/SNR vs. AIN with fIN = 32.5 MHz
Figure 14. AD9248-65 Single-Tone SFDR/SNR vs. fIN
100
95
90
90
80
SNR
SFDR
SFDR/SNR (dBc)
SFDR/SNR (dBc)
SNR
SFDR
70
SNR
60
85
80
75
SNR
04446-011
40
–35
–30
–25
–20
–15
–10
–5
04446-014
70
50
65
0
0
20
40
80
100
120
140
Figure 15. AD9248-40 Single-Tone SFDR/SNR vs. fIN
Figure 12. AD9248-40 Single-Tone SFDR/SNR vs. AIN with fIN = 20 MHz
95
100
90
90
SNR
SFDR
SFDR
SNR
80
SFDR/SNR (dBc)
SFDR/SNR (dBc)
60
INPUT FREQUENCY (MHz)
INPUT AMPLITUDE (dBFS)
70
SNR
60
85
80
75
SNR
04446-012
40
–35
–30
–25
–20
–15
–10
–5
04446-015
70
50
65
0
0
20
40
60
80
100
120
INPUT AMPLITUDE (dBFS)
INPUT FREQUENCY (MHz)
Figure 13. AD9248-20 Single-Tone SFDR/SNR vs. AIN with fIN = 10 MHz
Figure 16. AD9248-20 Single-Tone SFDR/SNR vs. fIN
Rev. B | Page 13 of 48
140
AD9248
100
0
SNR
SFDR
95
–20
SFDR/SNR (dBFS)
MAGNITUDE (dBFS)
90
–40
–60
IMD = –85dBc
–80
85
80
75
SNR
70
–100
–120
0
5
10
15
20
25
60
–24
30
04446-019
04446-063
65
–21
FREQUENCY (MHz)
–18
–15
–12
–9
–6
INPUT AMPLITUDE (dBFS)
Figure 17. Dual-Tone FFT with fIN1 = 39 MHz and fIN2 = 40 MHz
Figure 20. Dual-Tone SFDR/SNR vs. AIN with fIN1 = 45 MHz and fIN2 = 46 MHz
0
100
SNR
SFDR
95
–20
SFDR/SNR (dBFS)
MAGNITUDE (dBFS)
90
–40
IMD =
–83dBc
–60
–80
85
80
75
SNR
70
–100
–120
0
5
10
15
20
25
60
–24
30
04446-020
04446-064
65
–21
FREQUENCY (MHz)
Figure 18. Dual-Tone FFT with fIN1 = 70 MHz and fIN2 = 71 MHz
–15
–12
–9
–6
Figure 21. Dual-Tone SFDR/SNR vs. AIN with fIN1 = 70 MHz and fIN2 = 71 MHz
0
100
95
–20
90
SFDR/SNR (dBFS)
–40
–60
–80
SNR
SFDR
85
80
75
SNR
70
–100
–120
0
5
10
15
20
25
30
65
60
–24
04446-021
04446-018
MAGNITUDE (dBFS)
–18
INPUT AMPLITUDE (dBFS)
–21
–18
–15
–12
–9
FREQUENCY (MHz)
INPUT AMPLITUDE (dBFS)
Figure 19. Dual-Tone FFT with fIN1 = 200 MHz and fIN2 = 201 MHz
Figure 22. Dual-Tone SFDR/SNR vs.
AIN with fIN1 = 200 MHz and fIN2 = 201 MHz
Rev. B | Page 14 of 48
–6
AD9248
74
12.0
–65
600
SINAD –65
11.5
SINAD –40
ENOB
SINAD (dBc)
72
70
AVDD POWER (mW)
SINAD –20
500
400
–40
300
68
11.0
0
20
40
–20
04446-025
04446-022
200
100
0
10
20
60
30
40
50
60
SAMPLE RATE (MSPS)
CLOCK FREQUENCY (MHz)
Figure 26. Analog Power Consumption vs. FS
Figure 23. SINAD vs. FS with Nyquist Input
95
2.5
DCS ON (SFDR)
2.0
90
1.5
85
1.0
80
75
INL (LSB)
DCS ON (SINAD)
70
0
–0.5
65
–1.0
DCS OFF (SINAD)
60
04446-023
50
30
35
40
45
50
55
60
–2.0
–2.5
65
0
2000
4000
6000
8000
10000 12000 14000
DUTY CYCLE (%)
CODE
Figure 24. SINAD/SFDR vs. Clock Duty Cycle
Figure 27. AD9248-65 Typical INL
84
16000
1.0
SFDR
82
0.8
0.6
80
0.4
DNL (LSB)
78
76
74
72
SINAD
0.2
0
–0.2
–0.4
70
–0.6
04446-024
68
66
–50
04446-026
–1.5
55
SINAD/SFDR (dB)
0.5
0
50
100
04446-027
SINAD/SFDR (dBc)
DCS OFF (SFDR)
–0.8
–1.0
0
2000
4000
6000
8000
10000 12000 14000
TEMPERATURE (°C)
CODE
Figure 25. SINAD/SFDR vs. Temperature with fIN = 32.5 MHz
Figure 28. AD9248-65 Typical DNL
Rev. B | Page 15 of 48
16000
AD9248
EQUIVALENT CIRCUITS
AVDD
AVDD
04446-028
04446-030
CLK_A, CLK_B
DCS, DFS,
MUX_SELECT,
SHARED_REF
VIN+_A, VIN–_A,
VIN+_B, VIN–_B
Figure 31. Equivalent Digital Input Circuit
Figure 29. Equivalent Analog Input Circuit
04446-029
DRVDD
Figure 30. Equivalent Digital Output Circuit
Rev. B | Page 16 of 48
AD9248
THEORY OF OPERATION
The AD9248 consists of two high performance ADCs that are
based on the AD9235 converter core. The dual ADC paths are
independent, except for a shared internal band gap reference
source, VREF. Each of the ADC paths consists of a proprietary
front end SHA followed by a pipelined switched-capacitor ADC.
The pipelined ADC is divided into three sections, consisting
of a 4-bit first stage, followed by eight 1.5-bit stages, and a final
3-bit flash. Each stage provides sufficient overlap to correct for
flash errors in the preceding stages. The quantized outputs from
each stage are combined through the digital correction logic
block into a final 14-bit result. The pipelined architecture
permits the first stage to operate on a new input sample, while
the remaining stages operate on preceding samples. Sampling
occurs on the rising edge of the
respective clock.
In IF under-sampling applications, any shunt capacitors
should be removed. In combination with the driving source
impedance, they limit the input bandwidth. For best dynamic
performance, the source impedances driving VIN+ and VIN−
should be matched such that common-mode settling errors are
symmetrical. These errors are reduced by the common-mode
rejection of the ADC.
H
T
T
5pF
VIN+
CPAR
T
5pF
The input stage contains a differential SHA that can be
configured as ac- or dc-coupled in differential or single-ended
modes. The output-staging block aligns the data, carries out the
error correction, and passes the data to the output buffers. The
output buffers are powered from a separate supply, allowing
adjustment of the output voltage swing.
VIN–
CPAR
T
H
04446-031
Each stage of the pipeline, excluding the last, consists of a low
resolution flash ADC and a residual multiplier to drive the next
stage of the pipeline. The residual multiplier uses the flash ADC
output to control a switched-capacitor digital-to-analog converter
(DAC) of the same resolution. The DAC output is subtracted from
the stage’s input signal and the residual is amplified (multiplied)
to drive the next pipeline stage. The residual multiplier stage is
also called a multiplying DAC (MDAC). One bit of redundancy
is used in each one of the stages to facilitate digital correction of
flash errors. The last stage simply consists of a flash ADC.
Figure 32. Switched-Capacitor Input
An internal differential reference buffer creates positive and
negative reference voltages, REFT and REFB, respectively, that
define the span of the ADC core. The output common mode of
the reference buffer is set to midsupply, and the REFT and
REFB voltages and span are defined as:
REFT = ½(AVDD + VREF)
REFB = ½(AVDD −VREF)
Span = 2 × (REFT − REFB) = 2 × VREF
The equations above show that the REFT and REFB voltages are
symmetrical about the midsupply voltage and, by definition, the
input span is twice the value of the VREF voltage.
ANALOG INPUT
The analog input to the AD9248 is a differential, switchedcapacitor SHA that has been designed for optimum performance while processing a differential input signal. The SHA
input accepts inputs over a wide common-mode range. An
input common-mode voltage of midsupply is recommended
to maintain optimal performance.
The SHA input is a differential switched-capacitor circuit. In
Figure 32, the clock signal alternatively switches the SHA
between sample mode and hold mode. When the SHA is
switched into sample mode, the signal source must be capable
of charging the sample capacitors and settling within one-half
of a clock cycle. A small resistor in series with each input can
help reduce the peak transient current required from the output
stage of the driving source. Also, a small shunt capacitor can be
placed across the inputs to provide dynamic charging currents.
This passive network creates a low-pass filter at the ADC input;
therefore, the precise values are dependent on the application.
The internal voltage reference can be pin-strapped to fixed values
of 0.5 V or 1.0 V or adjusted within the same range as discussed
in the Internal Reference Connection section. Maximum SNR
performance is achieved with the AD9248 set to the largest
input span of 2 V p-p. The relative SNR degradation is 3 dB
when changing from 2 V p-p mode to 1 V p-p mode.
The SHA may be driven from a source that keeps the signal
peaks within the allowable range for the selected reference
voltage. The minimum and maximum common-mode input
levels are defined as:
Rev. B | Page 17 of 48
VCMMIN = VREF/2
VCMMAX = (AVDD + VREF)/2
AD9248
The minimum common-mode input level allows the AD9248 to
accommodate ground-referenced inputs. Although optimum
performance is achieved with a differential input, a single-ended
source may be driven into VIN+ or VIN−. In this configuration,
one input accepts the signal, while the opposite input should be
set to midscale by connecting it to an appropriate reference. For
example, a 2 V p-p signal may be applied to VIN+, while a 1 V
reference is applied to VIN−. The AD9248 then accepts an
input signal varying between 2 V and 0 V. In the single-ended
configuration, distortion performance may degrade significantly
as compared to the differential case. However, the effect is less
noticeable at lower input frequencies and in the lower speed grade
models (AD9248-40 and AD9248-20).
Differential Input Configurations
As previously detailed, optimum performance is achieved while
driving the AD9248 in a differential input configuration. For
baseband applications, the AD8138 differential driver provides
excellent performance and a flexible interface to the ADC. The
output common-mode voltage of the AD8138 is easily set to
AVDD/2, and the driver can be configured in a Sallen-Key filter
topology to provide band limiting of the input signal.
At input frequencies in the second Nyquist zone and above, the
performance of most amplifiers is not adequate to achieve the
true performance of the AD9248. This is especially true in IF
under-sampling applications where frequencies in the 70 MHz
to 200 MHz range are being sampled. For these applications,
differential transformer coupling is the recommended input
configuration, as shown in Figure 33.
50Ω
10pF
49.9Ω
Typical high speed ADCs use both clock edges to generate a
variety of internal timing signals and, as a result, may be sensitive
to the clock duty cycle. Commonly, a 5% tolerance is required
on the clock duty cycle to maintain dynamic performance
characteristics.
The AD9248 provides separate clock inputs for each channel. The
optimum performance is achieved with the clocks operated at the
same frequency and phase. Clocking the channels asynchronously
may degrade performance significantly. In some applications, it
is desirable to skew the clock timing of adjacent channels. The
AD9248’s separate clock inputs allow for clock timing skew
(typically ±1 ns) between the channels without significant
performance degradation.
The AD9248-65 contains two clock duty cycle stabilizers, one
for each converter, that retime the nonsampling edge, providing
an internal clock with a nominal 50% duty cycle. When proper
track-and-hold times for the converter are required to maintain
high performance, maintaining a 50% duty cycle clock is
particularly important in high speed applications. It may be
difficult to maintain a tightly controlled duty cycle on the input
clock on the PCB (see Figure 24). DCS can be enabled by tying
the DCS pin high.
The duty cycle stabilizer uses a delay-locked loop to create the
nonsampling edge. As a result, any changes to the sampling
frequency require approximately 2 μs to 3 μs to allow the DLL
to acquire and settle to the new rate.
High speed, high resolution ADCs are sensitive to the quality of
the clock input. The degradation in SNR at a given full-scale
input frequency (fINPUT) due only to aperture jitter (tJ) can be
calculated as
AVDD
VINA
2V p-p
CLOCK INPUT AND CONSIDERATIONS
AD9248
50Ω
⎤
⎡
1
SNR = 20 × log ⎢
⎥
(
)
2
π
f
t
×
×
×
j ⎦
INPUT
⎣
VINB
0.1μF
AGND
1kΩ
04446-032
10pF
1kΩ
Figure 33. Differential Transformer Coupling
The signal characteristics must be considered when selecting a
transformer. Most RF transformers saturate at frequencies
below a few MHz, and excessive signal power can also cause
core saturation, which leads to distortion.
Single-Ended Input Configuration
A single-ended input may provide adequate performance in
cost-sensitive applications. In this configuration, there is a
degradation in SFDR and distortion performance due to the
large input common-mode swing. However, if the source
impedances on each input are matched, there should be little
effect on SNR performance.
In the equation, the rms aperture jitter, tJ , represents the rootsum square of all jitter sources, which includes the clock input,
analog input signal, and ADC aperture jitter specification.
Under-sampling applications are particularly sensitive to jitter.
For optimal performance, especially in cases where aperture
jitter may affect the dynamic range of the AD9248, it is important
to minimize input clock jitter. The clock input circuitry should
use stable references; for example, use analog power and ground
planes to generate the valid high and low digital levels for the
AD9248 clock input. Power supplies for clock drivers should be
separated from the ADC output driver supplies to avoid modulating
the clock signal with digital noise. Low jitter, crystal-controlled
oscillators make the best clock sources. If the clock is generated from
another type of source (by gating, dividing, or other methods), it
should be retimed by the original clock at the last step.
Rev. B | Page 18 of 48
AD9248
A single channel can be powered down for moderate power
savings. The powered-down channel shuts down internal
circuits, but both the reference buffers and shared reference
remain powered on. Because the buffer and voltage reference
remain powered on, the wake-up time is reduced to several
clock cycles.
POWER DISSIPATION AND STANDBY MODE
The power dissipated by the AD9248 is proportional to its
sampling rates. The digital (DRVDD) power dissipation is
determined primarily by the strength of the digital drivers and
the load on each output bit. The digital drive current can be
calculated by
DIGITAL OUTPUTS
IDRVDD = VDRVDD × CLOAD × fCLOCK × N
The AD9248 output drivers can be configured to interface with
2.5 V or 3.3 V logic families by matching DRVDD to the digital
supply of the interfaced logic. The output drivers are sized to
provide sufficient output current to drive a wide variety of logic
families. However, large drive currents tend to cause current
glitches on the supplies that may affect converter performance.
Applications requiring the ADC to drive large capacitive loads
or large fanouts may require external buffers or latches.
where N is the number of bits changing, and CLOAD is the average
load on the digital pins that changed.
The analog circuitry is optimally biased so that each speed
grade provides excellent performance while affording reduced
power consumption. Each speed grade dissipates a baseline
power at low sample rates that increases with clock frequency.
Either channel of the AD9248 can be placed into standby mode
independently by asserting the PDWN_A or PDWN_B pins.
The data format can be selected for either offset binary or twos
complement. See the Data Format section for more information.
It is recommended that the input clock(s) and analog input(s)
remain static during either independent or total standby, which
results in a typical power consumption of 1 mW for the ADC.
Note that if DCS is enabled, it is mandatory to disable the clock
of an independently powered-down channel. Otherwise,
significant distortion results on the active channel. If the clock
inputs remain active while in total standby mode, typical power
dissipation of 12 mW results.
TIMING
The AD9248 provides latched data outputs with a pipeline delay
of seven clock cycles. Data outputs are available one propagation delay (tPD) after the rising edge of the clock signal. Refer
to Figure 2 for a detailed timing diagram.
The internal duty cycle stabilizer can be enabled on the AD9248
using the DCS pin. This provides a stable 50% duty cycle to
internal circuits.
The minimum standby power is achieved when both channels
are placed into full power-down mode (PDWN_A = PDWN_B =
HI). Under this condition, the internal references are powered
down. When either or both of the channel paths are enabled
after a power-down, the wake-up time is directly related to the
recharging of the REFT and REFB decoupling capacitors and to
the duration of the power-down. Typically, it takes approximately
5 ms to restore full operation with fully discharged 0.1 μF and
10 μF decoupling capacitors on REFT and REFB.
A–1
A1
A0
The length of the output data lines and loads placed on them
should be minimized to reduce transients within the AD9248.
These transients can detract from the converter’s dynamic
performance. The lowest typical conversion rate of the AD9248
is 1 MSPS. At clock rates below 1 MSPS, dynamic performance
may degrade.
A7
A3
A4
B1
B0
A6
A5
B8
B2
ANALOG INPUT
ADC B
B7
B3
B4
B6
B5
CLK_A = CLK_B =
MUX_SELECT
A–7
B–8
tPD
B–7
A–6
B–6
A–5
B–5
A–4
B–4
A–3
B–3
A–2
B–2
A–1
B–1
A0
B0
A1
D0_A TO
D11_A
04446-033
B–1
ANALOG INPUT
ADC A
A8
A2
tPD
Figure 34. Multiplexed Data Format Using the Channel A Output and the Same Clock Tied to CLK_A, CLK_B, and MUX_SELECT
Rev. B | Page 19 of 48
AD9248
The AD9248 data output format can be configured for either
twos complement or offset binary. This is controlled by the data
format select pin (DFS). Connecting DFS to AGND produces
offset binary output data. Conversely, connecting DFS to AVDD
formats the output data as twos complement.
The output data from the dual ADCs can be multiplexed onto a
single 14-bit output bus. The multiplexing is accomplished by
toggling the MUX_SELECT bit, which directs channel data to
the same or opposite channel data port. When MUX_SELECT
is logic high, the Channel A data is directed to the Channel A
output bus, and the Channel B data is directed to the Channel B
output bus. When MUX_SELECT is logic low, the channel data
is reversed, that is, the Channel A data is directed to the
Channel B output bus, and the Channel B data is directed to the
Channel A output bus. By toggling the MUX_SELECT bit,
multiplexed data is available on either of the output data ports.
If the ADCs run with synchronized timing, this same clock can
be applied to the MUX_SELECT pin. Any skew between
CLK_A, CLK_B, and MUX_SELECT can degrade AC
performance. It is recommended to keep the clock skew
<100 pS. After the MUX_SELECT rising edge, either data port
has the data for its respective channel; after the falling edge, the
alternate channel’s data is placed on the bus. Typically, the other
unused bus would be disabled by setting the appropriate OEB
high to reduce power consumption and noise. Figure 34 shows
an example of multiplex mode. When multiplexing data, the
data rate is two times the sample rate. Note that both channels
must remain active in this mode and that each channel’s powerdown pin must remain low.
gain and offset matching performance. If the ADCs are to
function independently, the reference decoupling can be
treated independently and can provide superior isolation
between the dual channels. To enable shared reference mode,
the SHARED_REF pin must be tied high and the external
differential references must be externally shorted. (REFT_A
must be externally shorted to REFT_B, and REFB_A must be
shorted to REFB_B.)
Internal Reference Connection
A comparator within the AD9248 detects the potential at the
SENSE pin and configures the reference into four possible
states, which are summarized in Table 7. If SENSE is grounded,
the reference amplifier switch is connected to the internal
resistor divider (see Figure 35), setting VREF to 1 V.
Connecting the SENSE pin to VREF switches the reference
amplifier output to the SENSE pin, completing the loop and
providing a 0.5 V reference output. If a resistor divider is
connected, as shown in Figure 36, the switch is again set to the
SENSE pin. This puts the reference amplifier in a noninverting
mode with the VREF output defined as
VREF = 0.5 × (1 + R2/R1)
In all reference configurations, REFT and REFB drive the ADC
core and establish its input span. The input range of the ADC
always equals twice the voltage at the reference pin for either an
internal or an external reference.
VIN+
VIN–
REFT
0.1μF
ADC
CORE
VOLTAGE REFERENCE
A stable and accurate 0.5 V voltage reference is built into the
AD9248. The input range can be adjusted by varying the
reference voltage applied to the AD9248, using either the
internal reference with different external resistor configurations
or an externally applied reference voltage. The input span of the
ADC tracks reference voltage changes linearly. If the ADC is
being driven differentially through a transformer, the reference
voltage can be used to bias the center tap (common-mode
voltage).
0.1μF
0.1μF
VREF
10μF
The shared reference mode allows the user to connect the
references from the dual ADCs together externally for superior
0.1μF
SELECT
LOGIC
0.5V
SENSE
AD9248
Figure 35. Internal Reference Configuration
Table 7. Reference Configuration Summary
Selected Mode
External Reference
Internal Fixed Reference
Programmable Reference
Internal Fixed Reference
SENSE Voltage
AVDD
VREF
0.2 V to VREF
AGND to 0.2 V
10μF
REFB
Resulting VREF (V)
N/A
0.5
0.5 × (1 + R2/R1)
1.0
Rev. B | Page 20 of 48
Resulting Differential Span (V p-p)
2 × External Reference
1.0
2 × VREF (See Figure 36)
2.0
04446-034
DATA FORMAT
AD9248
1.2
External Reference Operation
VIN+
1.0
VREF ERROR (%)
VREF = 1V
0.8
VREF = 0.5V
0.6
0.4
0
–40 –30 –20 –10
04446-036
0.2
0
10
20
30
50
40
60
70
Figure 37. Typical VREF Drift
0.05
0
–0.05
0.5V ERROR
–0.10
1V ERROR
–0.15
VIN–
REFT
0.1μF
0.1μF
–0.20
04446-037
ADC
CORE
10μF
–0.25
REFB
0
0.1μF
1.0
1.5
2.0
Figure 38. VREF Accuracy vs. Load
10μF
R2
0.5
LOAD (mA)
VREF
10μF
80
TEMPERATURE (°C)
ERROR (%)
The use of an external reference may be necessary to
enhance the gain accuracy of the ADC or to improve thermal
drift characteristics. When multiple ADCs track one another, a
single reference (internal or external) may be necessary to
reduce gain matching errors to an acceptable level. A high
precision external reference may also be selected to provide
lower gain and offset temperature drift. Figure 37 shows the
typical drift characteristics of the internal reference in both
1 V and 0.5 V modes. When the SENSE pin is tied to AVDD,
the internal reference is disabled, allowing the use of an
external reference. An internal reference buffer loads the
external reference with an equivalent 7 kΩ load. The internal
buffer still generates the positive and negative full-scale
references, REFT and REFB, for the ADC core. The input span
is always twice the value of the reference voltage; therefore, the
external reference must be limited to a maximum of 1 V. If the
internal reference of the AD9248 is used to drive multiple
converters to improve gain matching, the loading of the
reference by the other converters must be considered. Figure 38
depicts how the internal reference voltage is affected by loading.
SELECT
LOGIC
0.5V
SENSE
AD9248
04446-035
R1
Figure 36. Programmable Reference Configuration
Rev. B | Page 21 of 48
2.5
3.0
AD9248
AD9248 LQFP EVALUATION BOARD
The evaluation board supports both the AD9238 and AD9248
and has five main sections: clock circuitry, inputs, reference
circuitry, digital control logic, and outputs. A description of
each section follows. Table 8 shows the jumper settings and
notes assumptions in the comment column.
Four supply connections to TB1 are necessary for the evaluation
board: the analog supply of the DUT, the on-board analog
circuitry supply, the digital driver DUT supply, and the onboard digital circuitry supply. Separate analog and digital
supplies are recommended, and on each supply 3 V is nominal.
Each supply is decoupled on-board, and each IC, including the
DUT, is decoupled locally. All grounds should be tied together.
CLOCK CIRCUITRY
The clock circuitry is designed for a low jitter sine wave source
to be ac-coupled and level shifted before driving the 74VHC04
hex inverter chips (U8 and U9) whose output provides the clock
to the part. The POT (R32 and R31) on the level shifting
circuitry allows the user to vary the duty cycle if desired. The
amplitude of the sine wave must be large enough for the trip
points of the hex inverter and within the supplies to avoid noise
from clipping. To ensure a 50% duty cycle internal to the part,
the AD9248-65 has an on-chip duty cycle stabilizer circuit that
is enabled by putting in Jumper JP11. The duty cycle stabilizer
circuitry should only be used at clock rates above 40 MSPS.
Each channel has its own clock circuitry, but normally both
clock pins are driven by a single 74VHC04, and the solder
Jumper JP24 is used to tie the clock pins together. When the
clock pins are tied together and only one 74VHC04 is being
used, the series termination resistor for the other channel must
be removed (either R54 or R55, depending on which inverter is
being used).
A data capture clock for each channel is created and sent to the
output buffers in order to be used in the data capture system if
needed. Jumper JP25 and Jumper JP26 are used to invert the
data clock, if necessary, and can be used to debug data capture
timing problems.
ANALOG INPUTS
The AD9248 achieves the best performance with a differential
input. The evaluation board has two input options for each
channel, a transformer (XFMR) and an AD8138, both of which
perform single-ended-to-differential conversions. The XFMR
allows for the best high frequency performance, and the
AD8138 is ideal for dc evaluation, low frequency inputs, and
driving an ADC differentially without loading the single-ended
signal.
The common-mode level for both input options is set to
midsupply by a resistor divider off the AVDD supply but can
also be overdriven with an external supply using the (test
points) TP12, TP13 for the AD8138s, and TP14, TP15 for the
XFMRs. For low distortion of full-scale input signals when
using an AD8138, put Jumper JP17 and Jumper JP22 in
Position B and put an external negative supply on the TP10 and
TP11 testpoints.
For best performance, use low jitter input sources and a high
performance band-pass filter after the signal source, before the
evaluation board (see Figure 39). For XFMR inputs, use solder
Jumper JP13 and Jumper JP14 for Channel A, and Jumper JP20
and Jumper JP21 for Channel B. For AD8138 inputs, use solder
Jumper JP15 and Jumper JP16 for Channel A, and Jumper JP18
and Jumper JP19 for Channel B. Remove all solder from the
jumpers not being used.
REFERENCE CIRCUITRY
The evaluation board circuitry allows the user to select a
reference mode through a series of jumpers and provides an
external reference if necessary. Please refer to Table 9 to find the
jumper settings for each reference mode. The external reference
on the board is a simple resistor divider/zener diode circuit
buffered by an AD822 (U4). The POT (R4) can be used to
change the level of the external reference to fine adjust the ADC
full scale.
DIGITAL CONTROL LOGIC
The digital control logic on the evaluation board is a series of
jumpers and pull-down resistors used as digital inputs for the
following pins on the AD9248: the power-down and output
enable bar for each channel, the duty cycle restore circuitry, the
twos complement output mode, the shared reference mode, and
the MUX_SELECT pin. Refer to Table 8 for normal operating
jumper positions.
OUTPUTS
The outputs of the AD9248 (and the data clock discussed
earlier) are buffered by 74VHC541s (U2, U3, U7, U10) to
ensure the correct load on the outputs of the DUT, as well as the
extra drive capability to the next part of the system. The
74VHC541s are latches, but on this evaluation board, they are
wired and function as buffers. Jumper JP30 can be used to tie
the data clocks together if desired. If the data clocks are tied, the
R39 or R40 resistor must be removed, depending on which
clock circuitry is being used.
Rev. B | Page 22 of 48
AD9248
Table 9. Reference Jumpers
Reference Mode
1 V Internal
0.5 V Internal
External
Table 8. PCB Jumpers
Description
Reference
Reference
Reference
Reference
Reference
Shared Reference
Shared Reference
PDWN B
PDWN A
Shared Reference
Duty Cycle
Twos Complement
Input
Input
Input
Input
AD8138 Supply
Input
Input
Input
Input
AD8138 Supply
Mux Select
Tie Clocks
Data Clock
Data Clock
Mux Select
OEB_A
Mux Select
Data Clock
OEB_B
Normal
Setting
Out
In
Out
Out
Out
Out
Out
Out
Out
Out
In
Out
In
In
Out
Out
A
Out
Out
In
In
A
Out
In
A
Out
In
Out
Out
Out
Out
Comment
1 V Reference Mode
1 V Reference Mode
1 V Reference Mode
1 V Reference Mode
1 V Reference Mode
JP2
In
Out
Out
JP3
Out
In
Out
JP4
Out
Out
Out
JP5
Out
Out
In
SINE SOURCE
LOW JITTER
(HP8644)
SINE SOURCE
LOW JITTER
(HP8644)
AD9248
EVALUATION BOARD
CLOCK
CIRCUITRY
Duty Cycle Restore On
BAND-PASS
FILTERS
Using XFMR Input
Using XFMR Input
Using XFMR Input
Using XFMR Input
Using XFMR Input
Using XFMR Input
INPUT
CIRCUITRY
AD9248
REFERENCE MODE
SELECTION/EXTERNAL
REFERENCE/CONTROL
LOGIC
Figure 39. PCB Test Setup
Using One Signal for Clock
Using One Signal for Clock
Rev. B | Page 23 of 48
OUTPUT
BUFFERS
04446-038
JP
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
35
JP1
Out
Out
In
AD9248
LQFP EVALUATION BOARD BILL OF MATERIALS (BOM)
Table 10.
No.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
Quantity
18
23
7
15
4
4
2
2
4
4
2
1
1
14
13
4
4
6
1
1
7
6
8
6
2
4
2
4
2
2
2
16
6
2
1
4
4
7
2
1
4
1
2
2
Reference Designator
C1, C2, C11, C12, C27, C28, C33, C34, C50, C51, C73 to C76, C87 to C90
C3 to C10, C29 to C31, C56, C61 to C65, C77, C79, C80, C84 to C86
C13, C15, C18, C19, C21, C23, C25
C6, C14, C16, C17, C20, C22, C24, C26, C32, C35 to C40
C41 to C44
C45 to C48
C49, C53
C52, C57
C54, C55, C68, C69
C58, C59 ,C70, C71
C60, C72
D1
J1
JP1 to JP5, JP8 to JP12, JP23, JP28, JP29, JP35
JP6, JP7, JP13, JP14 to JP16, JP18 to JP21, JP24, JP27, JP30
JP17, JP22, JP25, JP26
L1 to L4
R1, R2, R13, R14, R23, R27
R3
R4
R5, R6, R38, R41, R43, R44, R51
R7, R8, R19, R20, R52, R53
R9, R18, R29, R30, R47 to R50
R10, R12, R15, R24, R25, R28
R11, R26
R16, R17, R21, R22
R31, R32
R33 to R35, R42
R36, R37
R39, R40
R54, R55
RP1 to RP16
S1 to S6
T1, T2
TB1
TP1, TP3, TP5, TP7
TP2, TP4, TP6, TP8
TP9, TP12 to TP17
TP10, TP11
U1
U2, U3, U7, U10
U4
U5, U6
U8, U9
Rev. B | Page 24 of 48
Device
Capacitors
Capacitors
Capacitors
Capacitors
Capacitors
Capacitors
Capacitors
Capacitors
Capacitors
Capacitors
Capacitors
AD1580
IND1210
Resistors
Resistor
Resistor
Resistors
Resistors
Resistors
Resistors
Resistors
Resistors
Resistors
Resistors
Resistors
Resistors
Resistors
Resistor Pack
Package
ACASE
0805
0603
0603
DCASE
1206
ACASE
0201
0805
0603
0603
SOT-23CAN
JPRBLK02
JPRSLD02
JPRBLK03
LC1210
1206
1206
RV3299UP
0805
1206
0805
1206
1206
1206
RV3299W
0805
1206
0805
1206
RCA74204
SMA200UP
DIP06RCUP
LOOPTP
LOOPTP
LOOPMINI
LOOPMINI
64LQFP7X7
SOL20
SOIC-8
SO8NC7
TSSOP-14
Value
10 μF
0.1 μF
0.001 μF
0.1 μF
22 μF
0.1 μF
6.3 V
0.01 μF
DNP
20 pF
1.2 V
SAM080UPM
10 μH
33 Ω
5.49 kΩ
10 kΩ
5 kΩ
49.9 Ω
1 kΩ
499 Ω
523 Ω
40 Ω
10 kΩ
500 Ω
10 kΩ
22 Ω
0Ω
22 Ω
T1-1T
TBLK06REM
RED
BLK
WHT
RED
AD9248
74VHC541
AD822
AD8138
74VHC04
Figure 40. Evaluation Board Schematic
Rev. B | Page 25 of 48
C73
10μF
6.3V
AVDD
CLKB
S5
AVDD
R53
49.9Ω
CLKA
04446-039
S6
AVDD
R52
49.9Ω
C79
0.1μF
C77
0.1μF
R35
500Ω
C84
0.1μF
R33
500Ω
R34
500Ω
R31
10kΩ
R42
500Ω
R32
10kΩ
C74
10μF
6.3V
CW
CW
C80
0.1μF
5
1
3
3
1
5
AGND;7
AVDD;14
6
AGND;7
AVDD;14
4
JP25
3
1
B A
2
74VHC04
AGND;7
U9 AVDD;14
10
74VHC04
AGND;7
U9 AVDD;14
12
74VHC04
AGND;7
AVDD;14
8
AGND;7
AVDD;14
U8
12
AGND;7
U8 AVDD;14
2
74VHC04
AGND;7
U8 AVDD;14
8
AGND;7
U8 AVDD;14
6
74VHC04
74VHC04
74VHC04
9
74VHC04
13
2
B A
3
1
JP26
AGND;7
U8 AVDD;14
11
10
11
13
9
U9
74VHC04
AGND;7
U8 AVDD;14
4
74VHC04
U9
74VHC04
AGND;7
U9 AVDD;14
2
74VHC04
U9
WHT
TP16
CLKAO
TP17
WHT
R55
0Ω
R2
33Ω
R1
33Ω
JP24
R54
0Ω
DUTCLKB
DATACLKB
DATACLKA
DUTCLKA
1
2
3
4
5
TB1 6
DVDDIN
TB1
AGND
TB1
DRVDDIN
TB1
AGND
TB1
DUTAVDDIN
TB1
AVDDIN
C43
22μF
F25V
C44
22μF
25V
C41
22μF
25V
C42
22μF
25V
L2
L1
L4
L3
C47
0.1μF
10μH
C48
0.1μF
10μH
C45
0.1μF
10μH
C46
0.1μF
10μH
DVDD
RED
TP8
BLK
TP7
TP6
BLK
DUTDRVDD
TP5
RED
TP4
BLK
DUTAVDD
TP3
RED
TP2
BLK
AVDD
TP1
RED
AD9248
LQFP EVALUATION BOARD SCHEMATICS
R20
49.9Ω
Rev. B | Page 26 of 48
Figure 41. Evaluation Board Schematic (Continued)
04446-040
S3
R8
49.9Ω
AMP INPUT B
S1
AMP INPUT A
C50
10μF
6.3V
C53
10V
6.3V
R26
523Ω
C49
10V
6.3V
AVDD
R24
499Ω
VOC
U6
VO+
2
1 –IN
4
3 VCC
VO–
AVDD
R15
499Ω
2
6 AD8138
5
8 +IN
R25
499Ω
VEE
TP11
RED
1 –IN
C61
0.1μF
R28
499Ω
VO–
VOC
VO+
5
AD8138
R12
499Ω
4
3 VCC
8 +IN
U5
JP22
3
A B
2
C62
0.1μF
1
R10
499Ω
R11
523Ω
VEE
6
TP10
RED
3
C86
0.1μF
JP17
A B
2
C51
10μF C56
6.3V 0.1μF
1
AVDD
TP13
WHT
AVDD
TP12
WHT
R29
1kΩ
R21
40Ω
R22
40Ω
R18
1kΩ
R16
40Ω
R17
40Ω
VAL
R9
1kΩ
C63
0.1μF
C88
10μF
6.3V
C54
VAL C55
R50
1kΩ
C85
0.1μF
C87
10μF
6.3V
C69
VAL
C68
VAL
4
T1–1T
T1
O
3
2
4
O
T2
O
3
2
6 P NC = 5 S 1
O
T1–1T
6 P NC = 5 S 1
R7
49.9Ω
R19
49.9Ω
XFMR INPUT B
S4
S2
XFMR INPUT A
AVDD
TP15
WHT
JP18
JP21
JP20
JP19
AVDD
TP14
WHT
JP16
JP13
JP14
JP15
R49
1kΩ
R23
33Ω
R27
33Ω
R30
1kΩ
R14
33Ω
R13
33Ω
VIN+_A
R48
1kΩ
C65
0.1μF
C90
10μF
6.3V
C70
DNP
VIN–_B
VIN+_B
SHEET 3
C71
DNP
R47
1kΩ
C64
0.1μF
C89
10μF
6.3V
VIN–_A
SHEET 3
C58
DNP
C72
20PF
C60
20pF
C59
DNP
AD9248
Figure 42. Evaluation Board Schematic (Continued)
Rev. B | Page 27 of 48
04446-041
R37
10kΩ
R36
10kΩ
1 1.2V
D1
2
CW
C1
10μF
6.3V
AD822
C37
0.1μF
AVDD
R51
5kΩ
R5
5kΩ
JP8
C32
0.1μF
C40
0.1μF
C33
10μF
6.3V
JP11
AVDD
C12
10μF
6.3V
JP7
JP6
C36
0.1μF
JP35
JP5
TP9
WHT
C39
0.1μF
C34
10μF
6.3V
C38
0.1μF
JP12
R41
5kΩ
JP4
JP1
JP2
JP3
AD822
DUTAVDD
2 –IN
1
AGND;4
AVDD;8
U4 OUT
3 +IN
AGND;4
5 +IN AVDD;8
7
U4 OUT
6 –IN
C31
0.1μF
C29
0.1μF
R4
10kΩ
R3
5.49kΩ
AVDD
C30
0.1μF
AVDD
VIN–_A
VIN+_A
R44
5kΩ
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
DUTCLKB
VIN+_B
C57
0.01μF VIN–_B
C52
0.01μF
C35
0.1μF
C16
0.1μF
CLK_A
AVDD1
C17
0.1μF
OTR_A
REFB_A
D2_A
D1_A
PDWN_B
OEB_B
D7_B
D6_B
C24
0.1μF
C25
0.001μF
AD9248
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
C26
0.1μF
D8_B
D9_B
D10_B
D11_B
DRVDD1
D5_B
D12_B
(MSB) D13_B
OTR_B
DRVSS2
DRVDD2
DRVSS1
D4_B
D3_B
D2_B
D1_B
D0_A (LSB)
D3_A
DFS
D0_B (LSB)
D4_A
DUTYEN
D6_A
AVDD4
D5_A
D7_A
AVSS4
CLK_B
D8_A
D9_A
DRVDD3
DRVSS3
D10_A
D11_A
D12_A
VIN+_B
VIN–_B
AVSS3
AVDD3
REFT_B
REFB_B
SENSE
(MSB) D13_A
OEB_A
REFT_A
VREF
PDWN_A
U1
MUX_SELECT
SHARED_REF
C18
0.001μF
AVDD2
AVSS2
VIN–_A
VIN+_A
AVSS1
C23
0.001μF
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
C15
0.001μF
DB8
DB9
C14
0.1μF
DB10
DB11
DB12
DB13
OTRB
DA0
DA1
DA2
DA3
DA4
DA5
DA6
DA7
DA8
DA9
DA10
DA11
DA13
DA12
OTRA
C21
0.001μF
JP28
JP9
C11
10μF
6.3V
AVDD
CLKAO
DUTDRVDD
JP23
JP29
JP27
AVDD
C2
10μF
6.3V
JP10
R38 R43 R6
5kΩ 5kΩ 5kΩ
C22
0.1μF
DUTCLKA
C19
0.001μF
C13
0.001μF
C20
0.1μF
DUTAVDD
AD9248
AD9248
C75
10μF
6.3V
C3
0.1μF
C8
0.1μF
C9
0.1μF
C10
0.1μF
C28
10μF
6.3V
DVDD
1 RP9
OTRA
DA13
DA12
DA11
DA10
DA9
DA8
2
3
4
1
2
3
4
RP9
RP9
RP9
RP10
RP10
RP10
RP10
22Ω 8
2
3
4
5
6
7
8
9
22Ω 7
22Ω 6
22Ω 5
22Ω 8
22Ω 7
22Ω 6
22Ω 5
1
19
DA7
DA6
DA5
DA4
DA3
DA2
DA1
DA0
1
2
3
4
1
2
3
4
RP11
RP11
RP11
RP11
RP12
RP12
RP12
RP12
22Ω
22Ω
22Ω
22Ω
22Ω
22Ω
22Ω
22Ω
8
7
6
5
8
7
6
5
2
3
4
5
6
7
8
9
G1
G2
A1
A2
A3
A4
A5
A6
A7
A8
G1
G2
A1
A2
A3
A4
A5
A6
A7
A8
VCC
GND
74VHC541
Y1
Y2
Y3
Y4
Y5
Y6
Y7
Y8
U10
VCC
GND
74VHC541
Y1
Y2
Y3
Y4
Y5
Y6
Y7
Y8
U7
20
10
R40
22Ω
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
1 RP1 22Ω 8
18
17
16
15
14
13
12
11
RP1
RP1
RP1
RP2
RP2
RP2
RP2
RP3
RP3
RP3
RP3
RP4
RP4
RP4
RP4
2
3
4
1
2
3
4
1
2
3
4
1
2
3
4
20
10
18
17
16
15
14
13
12
11
22Ω
22Ω
22Ω
22Ω
22Ω
22Ω
22Ω
22Ω
22Ω
22Ω
22Ω
22Ω
22Ω
22Ω
22Ω
7
6
5
8
7
6
5
8
7
6
5
8
7
6
5
HEADER UP MALE NO SHROUD
1
19
DATACLKA
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
J1
SAM080UPM
JP30
C76
10μF
6.3V
C7
0.1μF
C6
0.1μF
C5
0.1μF
C27
10μF
6.3V
C4
0.1μF
OTRB
DA13
DA12
DA11
DA10
DA9
DA8
DA7
2
3
4
1
2
3
4
1
RP13
RP13
RP13
RP14
RP14
RP14
RP14
RP15
22Ω
22Ω
22Ω
22Ω
22Ω
22Ω
22Ω
22Ω
7
6
5
8
7
6
5
8
2
3
4
5
6
7
8
9
1
19
DA6
DA5
DA4
DA3
DA2
DA1
DA0
2
3
4
1
2
3
4
RP15
RP15
RP15
RP16
RP16
RP16
RP16
22Ω
22Ω
22Ω
22Ω
22Ω
22Ω
22Ω
7
6
5
8
7
6
5
2
3
4
5
6
7
8
9
G1
G2
A1
A2
A3
A4
A5
A6
A7
A8
G1
G2
A1
A2
A3
A4
A5
A6
A7
A8
VCC
GND
74VHC541
Y1
Y2
Y3
Y4
Y5
Y6
Y7
Y8
U3
1
2
3
4
1
2
3
4
1
2
3
4
1
2
3
20
10
18
17
16
15
14
13
12
11
RP5
RP5
RP5
RP5
RP6
RP6
RP6
RP6
RP7
RP7
RP7
RP7
RP8
RP8
RP8
22Ω
22Ω
22Ω
22Ω
22Ω
22Ω
22Ω
22Ω
22Ω
22Ω
22Ω
22Ω
22Ω
22Ω
22Ω
8
7
6
5
8
7
6
5
8
7
6
5
8
7
6
4 RP8 22Ω 5
42
44
46
48
50
52
54
56
58
60
62
64
66
68
70
72
74
76
78
80
41
43
45
47
49
51
53
55
57
59
61
63
65
67
69
71
73
75
77
79
J1
SAM080UPM
R39
22Ω
DATACLKB
Figure 43. Evaluation Board Schematic (Continued)
Rev. B | Page 28 of 48
04446-042
1 RP13 22Ω 8
VCC 20
U2 GND 10
74VHC541
18
Y1
17
Y2
16
Y3
15
Y4
14
Y5
13
Y6
12
Y7
11
Y8
HEADER UP MALE NO SHROUD
DVDD
1
19
AD9248
04446-043
LQFP PCB LAYERS
Figure 44. PCB Top Layer
Rev. B | Page 29 of 48
04446-044
AD9248
Figure 45. Bottom Layer
Rev. B | Page 30 of 48
04446-045
AD9248
Figure 46. PCB Ground Plane
Rev. B | Page 31 of 48
04446-046
AD9248
Figure 47. PCB Split Power Plane
Rev. B | Page 32 of 48
04446-049
AD9248
Figure 48. PCB Top Silkscreen (Note that the PCB Supports Both the AD9238 and AD9248 LQFP)
Rev. B | Page 33 of 48
04446-048
AD9248
Figure 49. PCB Bottom Silkscreen
Rev. B | Page 34 of 48
AD9248
DUAL ADC LFCSP PCB
The PCB requires a low jitter clock source, analog sources, and
power supplies. The PCB interfaces directly with Analog Devices
standard dual-channel data capture board (HSC-ADC-EVAL-DC),
which together with ADI’s ADC Analyzer™ software allows for
quick ADC evaluation.
POWER CONNECTOR
Power is supplied to the board via three detachable 4-lead
power strips.
Table 11. Power Connector
Terminal
VCC1 3.0 V
VDD1 3.0 V
VDL1 3.0 V
VREF
+5 V
−5 V
Comments
Analog supply for ADC
Output supply for ADC
Supply circuitry
Optional external VREF
Optional op amp supply
Optional op amp supply
CLOCK
The clock inputs are buffered on the board at U5 and U6. These
gates provide buffered clocks to the on-board latches, U2 and
U4, ADC input clocks, and DRA, DRB that are available at the
output Connector P3, P8. The clocks can be inverted at the
timing jumpers labeled with the respective clocks. The clock
paths also provide for various termination options. The ADC
input clocks can be set to bypass the buffers at solder bridges
P2, P9 and P10, P12. An optional clock buffer U3, U7 can also
be placed. The clock inputs can be bridged at TIEA, TIEB (R20,
R40) to allow one to clock both channels from one clock source;
however, optimal performance is obtained by driving J2 and J3.
Table 12. Jumpers
1
VCC, VDD, and VDL are the minimum required power connections.
ANALOG INPUTS
The evaluation board accepts a 2 V p-p analog input signal
centered at ground at two SMB connectors, Input A and
Input B. These signals are terminated at their respective
transformer primary side. T1 and T2 are wideband RF
transformers that provide the single-ended-to-differential
conversion, allowing the ADC to be driven differentially,
minimizing even-order harmonics. The analog signals can be
low-pass filtered at the transformer secondary to reduce high
frequency aliasing.
OPTIONAL OPERATIONAL AMPLIFIER
The PCB has been designed to accommodate an optional
AD8139 op amp that can serve as a convenient solution for
dc-coupled applications. To use the AD8139 op amp, remove
C14, R4, R5, C13, R37, and R36. Place R22, R23, R30, and R24.
Terminal
OEB A
PDWN A
MUX
SHARED REF
DR A
LATA
ENC A
OEB B
PDWN B
DFS
SHARED REF
DR B
LATB
ENC B
Comments
Output Enable for A Side
Power-Down A
Mux Input
Shared Reference Input
Invert DR A
Invert A Latch Clock
Invert Encode A
Output Enable for B Side
Power-Down B
Data Format Select
Shared Reference Input
Invert DR B
Invert B Latch Clock
Invert Encode B
VOLTAGE REFERENCE
The ADC SENSE pin is brought out to E41, and the internal
reference mode is selected by placing a jumper from E41 to
ground (E27). External reference mode is selected by placing a
jumper from E41 to E25 and E30 to E2. R56 and R45 allow for
programmable reference mode selection.
DATA OUTPUTS
The ADC outputs are latched on the PCB at U2, U4. The ADC
outputs have the recommended series resistors in line to limit
switching transient effects on ADC performance.
Rev. B | Page 35 of 48
AD9248
LFCSP EVALUATION BOARD BILL OF MATERIALS (BOM)
Table 13.
No.
1
2
3
Quantity
2
7
44
4
5
6
7
8
9
10
11
12
13
14
15
16
6
2
6
3
3
2
4
6
4
9
6
2
27
17
18
19
20
21
22
23
24
25
26
27
4
2
1
8
2
1
2
2
2
2
4
1
2
Reference Designator
C1, C3
C2, C5, C7, C9, C10, C22, C36
C4, C6, C8, C11 to C15, C20, C21,
C24 to C27, C29 to C35, C39 to C61
C16 to C19, C37, C38
C23, C28
J1 to J6
P1, P4, P11
P1, P4, P11
P3 1 , P8
R1, R2, R32, R34
R3, R6, R7, R8, R11, R14, R33, R42, R51, R61
R4, R5, R36, R37
R9, R10, R12, R13, R20, R35, R38, R40, R43
R15, R16, R18, R26, R29, R31
R17, R25
R19, R21, R27, R28, R39, R41, R44,
R46 to R49, R52, R54, R55, R57 to R60, R62 to R70
R22 to R24, R30
R45, R56
R50
RZ1 to RZ6, RZ9, RZ10
T1, T2
U1
U2, U425
U3 2 , U7
U5, U6
U11, U12
R6, R8, R33, R42
Device
Capacitors
Capacitors
Capacitors
Package
0201
0805
0402
Value
20 pF
10 μF
0.1 μF
Capacitors
Capacitors
SMBs
Power Connector Posts
Detachable Connectors
Connectors
Resistors
Resistors
Resistors
Resistors
Resistors
Resistors
Resistors
TAJD
0201
10 μF
0.1 μF
Z5.531.3425.0
25.602.5453.0
Wieland
Wieland
0402
0402
0402
0402
0402
0402
0402
36 Ω
50 Ω
33 Ω
0Ω
499 Ω
525 Ω
1 kΩ
0402
0402
0402
40 Ω
10 kΩ
22 Ω
220 Ω
Mini-Circuits®
Resistors
Resistors
Resistor
Resistor Pack
Transformers
AD9248
SN74LVTH162374
SN74LVC1G04
SN74VCX86
AD8139
Resistors
P3, P8 implemented as one 80-pin connector SAMTEC TSW-140-08-L-D-RA.
U3, U7 not placed.
Rev. B | Page 36 of 48
AWT-1WT
LFCSP-64
TSSOP-48
SOT-70
SO-14
SO-8/EP
0402
100 Ω
04446-050
J1
AIN B
C9
10μF
R57
1kΩ
R59
1kΩ
C10
10μF
C12
0.1μF
3
VDD
4
2
3
4
R4
33Ω
6
5 CTAPA
4
10μF
+
R5
33Ω
+5V
2
–5V
3
+
C19
+
C24
0.1μF
C1
20pF
AMPOUTA
+
C5
4
C44 C45
C23
0.1μF
1
2
3
4
5
E5
VD
R66
1kΩ
AGND
VIN_A
VIN_AB
AGND1
AVDD1
0.1μF 0.1μF 0.1μF 0.1μF
C39 C43
VD
VDD VDL EXT_VREF
C16 C17 C18
VD
10μF 10μF 10μF 10μF 10μF
+
+5V
C38
–5V
1
P1
T1
EXT_VREF
VD
E27
E2
E25
R36
33Ω
E30
E41
R56
10kΩ
R45
10kΩ
AMPOUTB
VREF AND SENSE CIRCUIT
C13
R7
50Ω 0.1μF
2
3
C30
0.1μF
VREF
C2
10μF
SENSE
C11
0.1μF
C55
VD
E24
R67
1kΩ
VD
E6
R65
1kΩ
VD 6
REFT_A
C26
7
REFB_A
10μF 0.1μF
AMPOUTAB
0.1μF
R58
8
PADS TO SHORT
VREF
VREF
SEE
1kΩ
REFERENCES TOGETHER
9
C29
BELOW SENSE
SENSE
0.1μF
REFTA
P15
E43
VD
REFB_B 10
REFTB
C7 C54
REFB_B
P16
E42
VD
C27
REFT_B
11
REFBA
REFT_B
10μF 0.1μF
0.1μF
P18
12
REFBB
R60
VD
AVDD2
P17
C28
1kΩ
13
0.1μF
AGND2
CTAPB
AMPOUTBB
14
VIN_BB
6
1
15
R37
VIN_B
CTAPB 2
5
C3
33Ω
16
AGND3
AMPINB
20pF
4
3
CTAPA 1
1
VDL EXT_VREF
C37
T2
VD
VDD
VDL
C14
R3
50Ω 0.1μF
P5
P6
P7
2
AMPINA
C31
0.1μF
AIN A
J4
H4
MTHOLE6
H3
MTHOLE6
H1
MTHOLE6
H2
MTHOLE6
VD
1
P4
ENCA
P11
VD
E22
R63
1kΩ
E18
R62
1kΩ
E20
C8
0.1μF
U1
E21
VD
E29
R70 1kΩ
VD
E33
E26
R69
1kΩ
VDD
J2
TIEB
E31
ENCODE B R51
50Ω
C6
0.1μF
VD
R54
1kΩ
C42
0.1μF
R52
1kΩ
D8_B 33
39
38
37
36
35
34
48
47
46
45
44
43
42
41
40
R41
1kΩ
E4
E36
C41
0.1μF
VD
R49
1kΩ
E35
VD
P13
P2 P9
8
9
10
11
12
13
14
U3
2
A
3
GND
U6
1A VCC
4B
1B
4A
1Y
4Y
2A
3B
2B
3A
2Y
GND 3Y
14
VD
13
12
11 0Ω
10 R10 DRA
9
8 0Ω
R9
CLKLATA
C25
0.1μF
R33
100Ω
ENCA
R14
50Ω
U5
74LCX86
7
6
5
4
3
2
1
R50 R8
100Ω
22Ω VD
E13 E12
TIEB
TIEA
MUX
R47
1kΩ
R46
1kΩ
E14 E15
VD
VD
0Ω
R13
0Ω
R12
DRB
R55
1kΩ
R48
1kΩ
E37 E38
CLKLATB
E34 E16
VD
VD
DUT CLOCK SELECTABLE
TO BE DIRECT OR
BUFFERED
R40
R20
0Ω
R6
100Ω
ENCB
VD
C57
C22 0.1μF
10μF
J5
R35
R38 0Ω
0Ω
0Ω
TO TIE CLOCKS TOGETHER
1
2
3
4
5
6
7
74LCX86
R42
100Ω
R43
0Ω VD
VD
C58
C36 0.1μF
10μF
3Y GND
2Y
3A
2B
3B
2A
4Y
1Y
4A
1B
4B
VCC 1A
Y
4
D8B 1
5
NC VCC
OTRB
D13B
D12B
D11B
D10B
D9B SN74LVC1G04
VDD
C4
0.1μF
P14
P10 P12
U7
SN74LVC1G04
5
1
NC VCC
2
A
3
4
Y
GND
E3
R44
1kΩ
VD
D6A
D5A
D4A
D3A
D2A
D1A
D0A
VD
0.1μF
C40
R39
1kΩ
TIEA
R11
50Ω
D6_A
D5_A
D4_A
D3_A
D2_A
D1_A
D0_A
DRVDD1
DRGND1
OTR_B
D13_B
D12_B
D11_B
D10_B
D9_B
J3
VDD ENCODE A
J6
DUT CLOCK SELECTABLE
TO BE DIRECT OR BUFFERED
R61
50Ω
C56
0.1μF
E10
MUX
VD
E17
E9
VD
E40
R68
1kΩ
VD
ENCB
65
E7
D0B
D1B
D2B
D3B
D4B
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
Rev. B | Page 37 of 48
AVDD3
CLK_B
DCS
DFS
PDWN_B
OEB_B
D0_B
D1_B
D2_B
D3_B
D4_B
DRGND
DRVDD
D5_B
D6_B
D7_B
+
Figure 50. PCB Schematic (1 of 3)
D5B
D6B
D7B
R64
1kΩ
OTRA
D13A
D12A
D11A
D10A
EPAD
AVDD5
CLK_A
SH_REF
MUX_SEL
PDWN_A
OEB_A
OTR_A
D13_A
D12_A
D11_A
D10_A
DRGND2
DRVDD2
D9_A
D8_A
D7_A
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
D9A
D8A
D7A
VD
AD9248
LFCSP PCB SCHEMATICS
Figure 51. PCB Schematic (2 of 3)
Rev. B | Page 38 of 48
04446-051
D5B
D4B
D3B
D2B
D1B
D0B
D6B
OTRB
D13B
D12B
D11B
D10B
D9B
D8B
D7B
D6A
D5A
D4A
D3A
D2A
D1A
D0A
OTRA
D13A
D12A
D11A
D10A
D9A
D8A
D7A
220
RZ2
RSO16ISO
1 R1
16
2 R2
15
3 R3
14
4 R4
13
5 R5
12
6 R6
11
7 R7
10
8 R8
9
RZ1 220
RSO16ISO
1 R1 16
2 R2 15
3 R3 14
4 R4 13
5 R5 12
6 R6 11
7 R7 10
8 R8 9
220
RZ4
RSO16ISO
1 R1 16
2 R2 15
3 R3 14
4 R4 13
5 R5 12
6 R6 11
7 R7 10
8 R8 9
RZ3 220
RSO16ISO
1 R1 16
2 R2 15
3 R3 14
4 R4 13
5 R5 12
6 R6 11
7 R7 10
8 R8 9
VDL
C48
C47
C46
SN74LVCH16373A
U4
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
C53
Q = OUTPUT
LE2 D = INPUT OE2
2Q8
2D8
2Q7
2D7
GND
GND
2D6
2Q6
2D5
2Q5
VCC
VCC
2Q4
2D4
2D3
2Q3
GND
GND
2D2
2Q2
2Q1
2D1
1D8
1Q8
1D7
1Q7
GND
GND
1D6
1Q6
1D5
1Q5
VCC
VCC
1D4
1Q4
1D3
1Q3
GND
GND
1D2
1Q2
1D1
1Q1
OE1
LE1
SN74LVCH16373A
U2
Q = OUTPUT
LE2 D = INPUT OE2
2D8
2Q8
2D7
2Q7
GND
GND
2D6
2Q6
2D5
2Q5
VCC
VCC
2D4
2Q4
2D3
2Q3
GND
GND
2D2
2Q2
2D1
2Q1
1D8
1Q8
1Q7
1D7
GND
GND
1D6
1Q6
1D5
1Q5
VCC
VCC
1D4
1Q4
1Q3
1D3
GND
GND
1Q2
1D2
1D1
1Q1
LE1
OE1
C52
VDL
VDL
VDL
VDL
C51
C50
0.1μF 0.1μF 0.1μF 0.1μF 0.1μF 0.1μF 0.1μF 0.1μF
C49
CLKLATB
25
26
27
28
29
30
VDL
31
32
33
34
35
36
37
38
39
40
41
VDL
42
43
44
45
46
47
CLKLATB 48
25
26
27
28
29
30
VDL
31
32
33
34
35
36
37
38
39
40
41
VDL
42
43
44
45
46
47
CLKLATA 48
CLKLATA
R1
R2
R3
R4
R5
R6
R7
R8
16
15
14
13
12
11
10
9
1
2
3
4
5
6
7
8
R1
R2
R3
R4
R5
R6
R7
R8
16
15
14
13
12
11
10
9
RZ9 220
RSO16ISO
1
2
3
4
5
6
7
8
RZ10 220
RSO16ISO
RZ6 220
RSO16ISO
1 R1 16
2 R2 15
3 R3 14
4 R4 13
5 R5 12
6 R6 11
7 R7 10
8 R8 9
RZ5 220
RSO16ISO
1 R1 16
2 R2 15
3 R3 14
4 R4 13
5 R5 12
6 R6 11
7 R7 10
8 R8 9
D6Q
D5Q
D4Q
D3Q
D2Q
D1Q
D0Q
DORQ
D13Q
D12Q
D11Q
D10Q
D9Q
D8Q
D7Q
D6P
D5P
D4P
D3P
D2P
D1P
D0P
DORP
D13P
D12P
D11P
D10P
D9P
D8P
D7P
40
38
36
34
32
30
28
26
24
22
20
18
16
14
12
10
8
6
4
2
40
38
36
34
32
30
28
26
24
22
20
18
16
14
12
10
8
6
4
2
P3
39
37
35
33
31
29
27
25
23
21
19
17
15
13
11
9
7
5
3
1
P8
37
35
33
31
29
27
25
23
21
19
17
15
13
11
9
7
5
3
1
39
HEADER40
40
38
36
34
32
30
28
26
24
22
20
18
16
14
12
10
8
6
4
2
HEADER40
40
38
36
34
32
30
28
26
24
22
20
18
16
14
12
10
8
6
4
2
39
37
35
33
31
29
27
25
23
21
19
17
15
13
11
9
7
5
3
1
39
37
35
33
31
29
27
25
23
21
19
17
15
13
11
9
7
5
3
1
DRB
GND
D13Q
D12Q
D11Q
D10Q
D9Q
D8Q
D7Q
D6Q
D5Q
D4Q
D3Q
D2Q
D1Q
D0Q
DORQ
DRA
GND
D13P
D12P
D11P
D10P
D9P
D8P
D7P
D6P
D5P
D4P
D3P
D2P
D1P
D0P
DORP
AD9248
Figure 52. PCB Schematic (3 of 3)
Rev. B | Page 39 of 48
04446-052
R31
499Ω
C61
–5V
C34
0.1μF
9
AMPOUTBB
AMPOUTB
U12
R30
40Ω
AD8139
3
V+
4
+OUT
2
1
V–
–OUT
–IN
VOCM
EPAD
NC
+IN
VD
C35
0.1μF
+5V
R27
1kΩ
R25
525Ω
R24
40Ω
5
6
7
8
R29
499Ω
AMPINB
R28
1kΩ
0.1μF
C20
R26
499Ω
R15
499Ω
C15
C60
–5V
R23
40Ω
5
6
7
9
–IN
AD8139
V+
+OUT
VOCM
EPAD
–OUT
V–
NC
+IN
AMPOUTAB
C33
0.1μF
8
R17
525Ω
R22
40Ω
AMPOUTA
U11
4
3
2
1
VD
C32
0.1μF
+5V
R21
1kΩ
R16
499Ω
AMPINA
R19
1kΩ
R18
499Ω
0.1μF
C21
OP AMP INPUT OFF PIN 1 OF TRANSFORMER
C59
AD9248
AD9248
04446-053
LFCSP PCB LAYERS
Figure 53. PCB Top-Side Silkscreen
Rev. B | Page 40 of 48
04446-054
AD9248
Figure 54. PCB Top-Side Copper Routing
Rev. B | Page 41 of 48
04446-055
AD9248
Figure 55. PCB Ground Layer
Rev. B | Page 42 of 48
04446-056
AD9248
Figure 56. PCB Split Power Plane
Rev. B | Page 43 of 48
04446-057
AD9248
Figure 57. PCB Bottom-Side Copper Routing
Rev. B | Page 44 of 48
04446-058
AD9248
Figure 58. PCB Bottom-Side Silkscreen
The AD9248 LFCSP has an integrated heat slug
that improves the thermal and electrical properties of the
package when locally attached to a ground plane at the PCB.
A thermal (filled) via array to a ground plane beneath the
part provides a path for heat to escape the package, lowering
junction temperature. Improved electrical performance
also results from the reduction in package parasitics due to
proximity of the ground plane. Recommended array is 0.3 mm
vias on 1.2 mm pitch. θJA = 26.4°C/W with this recommended
configuration. Soldering the slug to the PCB is a requirement
for this package.
Rev. B | Page 45 of 48
04446-059
THERMAL CONSIDERATIONS
Figure 59. Thermal Via Array
AD9248
OUTLINE DIMENSIONS
0.75
0.60
0.45
9.20
9.00 SQ
8.80
1.60
MAX
64
49
1
48
PIN 1
7.20
7.00 SQ
6.80
TOP VIEW
(PINS DOWN)
0.15
0.05
0.20
0.09
7°
3.5°
0°
0.08
COPLANARITY
SEATING
PLANE
16
33
32
17
VIEW A
VIEW A
ROTATED 90° CCW
0.23
0.18
0.13
0.40
BSC
LEAD PITCH
051706-A
1.45
1.40
1.35
COMPLIANT TO JEDEC STANDARDS MS-026-BBD
Figure 60. 64-Lead Low Profile Quad Flat Package [LQFP]
(ST-64-1)
Dimensions shown in millimeters
9.00
BSC SQ
0.60 MAX
8.75
BSC SQ
33
32
16
17
7.50
REF
0.80 MAX
0.65 TYP
0.05 MAX
0.02 NOM
0.50 BSC
PIN 1
INDICATOR
*4.85
4.70 SQ
4.55
EXPOSED PAD
(BOTTOM VIEW)
0.50
0.40
0.30
SEATING
PLANE
1
0.20 REF
FOR PROPER CONNECTION OF
THE EXPOSED PAD, REFER TO
THE PIN CONFIGURATION AND
FUNCTION DESCRIPTIONS
SECTION OF THIS DATA SHEET.
*COMPLIANT TO JEDEC STANDARDS MO-220-VMMD-4
EXCEPT FOR EXPOSED PAD DIMENSION
Figure 61. 64-Lead Lead Frame Chip Scale Package [LFCSP_VQ]
9 mm × 9 mm Body, Very Thin Quad
(CP-64-1)
Dimensions shown in millimeters
Rev. B | Page 46 of 48
082908-B
TOP
VIEW
12° MAX
64
49
48
PIN 1
INDICATOR
1.00
0.85
0.80
0.30
0.25
0.18
0.60 MAX
AD9248
ORDERING GUIDE
Model 1
AD9248BSTZ-20
AD9248BSTZ-40
AD9248BSTZ-65
AD9248BSTZRL-20
AD9248BSTZRL-40
AD9248BSTZRL-65
AD9248BCPZ-20
AD9248BCPZ-40
AD9248BCPZ-65
AD9248BCPZRL-20
AD9248BCPZRL-40
AD9248BCPZRL-65
AD9248BST-65EBZ
AD9248BCP-65EBZ
1
Temperature Range
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
Package Description
64-Lead Low Profile Quad Flat Package (LQFP)
64-Lead Low Profile Quad Flat Package (LQFP)
64-Lead Low Profile Quad Flat Package (LQFP)
64-Lead Low Profile Quad Flat Package (LQFP)
64-Lead Low Profile Quad Flat Package (LQFP)
64-Lead Low Profile Quad Flat Package (LQFP)
64-Lead Lead Frame Chip Scale Package (LFCSP_VQ)
64-Lead Lead Frame Chip Scale Package (LFCSP_VQ)
64-Lead Lead Frame Chip Scale Package (LFCSP_VQ)
64-Lead Lead Frame Chip Scale Package (LFCSP_VQ)
64-Lead Lead Frame Chip Scale Package (LFCSP_VQ)
64-Lead Lead Frame Chip Scale Package (LFCSP_VQ)
Evaluation Board with AD9248BSTZ-65
Evaluation Board with AD9248BCPZ-65
Z = RoHS Compliant Part.
Rev. B | Page 47 of 48
Package Option
ST-64-1
ST-64-1
ST-64-1
ST-64-1
ST-64-1
ST-64-1
CP-64-1
CP-64-1
CP-64-1
CP-64-1
CP-64-1
CP-64-1
AD9248
NOTES
©2005–2010 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D04446–0–11/10(B)
Rev. B | Page 48 of 48