Circuit Note
CN-0205
Circuits from the Lab™ reference circuits are engineered and
tested for quick and easy system integration to help solve today’s
analog, mixed-signal, and RF design challenges. For more
information and/or support, visit www.analog.com/CN0205.
Devices Connected/Referenced
AD9122
Dual Channel, 1.2 GSPS, 16-Bit, TxDAC®
Digital-to Analog Converter
ADL5375
Broadband Quadrature Modulator
Interfacing the ADL5375 I/Q Modulator to the
AD9122 Dual Channel, 1.2 GSPS High Speed DAC
The 1.2 GSPS AD9122 DAC sampling rate and the wide
bandwidth of the ADL5375-05 modulator I and Q inputs
ensure that both zero-IF (ZIF) or complex-IF (CIF)
architectures can be supported. In addition to filtering Nyquist
images, the baseband filter provides excellent rejection of both
differential-mode and common-mode DAC spurs.
EVALUATION AND DESIGN SUPPORT
Circuit Evaluation Boards
AD9122/ADL5375 Evaluation Board (AD9122-M5375-EBZ)
Design and Integration Files
Schematics, Layout Files, Bill of Materials
CIRCUIT FUNCTION AND BENEFITS
CIRCUIT DESCRIPTION
This circuit provides a simple and flexible interface between
the AD9122 dual high speed TxDAC digital-to-analog
converter and the ADL5375-05 broadband I/Q modulator.
Because the DAC outputs and ADL5375-05 I/Q modulator
inputs share a common bias level of 0.5 V, there is no need
for any active or passive level shifting circuitry. The dc coupled
interface facilitates I/Q modulator local oscillator (LO) leakage
compensation by the DAC.
The circuit and board shown in Figure 1 and Figure2 utilize the
AD9122 TxDAC and the ADL5375-05 wideband transmit
modulator. Signal biasing and scaling in the interface circuit is
controlled by the four ground-referenced resistors (RBIP, RBIN,
RBQP, RBQN) and the two shunt resistors (RSLI,RSLQ),
respectively.
AD9122
ADL5375-05
67
21
IOUT1P
IBBP
RBIP
50Ω
RBIN
66 50Ω
LOW-PASS
FILTER
RSLI
100Ω
22
IBBN
IOUT1N
59
9
IOUT2N
QBBN
RBQP
58 50Ω
LOW-PASS
FILTER
IOUT2P
RSLQ
100Ω
10
QBBP
09740-001
RBQN
50Ω
Figure 1. Interface Between the AD9122 and ADL5375-05 with 50 Ω Resistors to Ground to Establish the
500 mV DC Bias for the ADL5375-05 Baseband Inputs (Simplified Schematic)
Rev. 0
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whatsoever connected to the use of any Circuits from the Lab circuits. (Continued on last page)
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©2011 Analog Devices, Inc. All rights reserved.
CN-0205
Circuit Note
TOP VIEW
BOTTOM VIEW
ADL5375
MODULATOR
FILTER
AD9122
09740-002
DAC
Figure 2. AD9122-M5375-EBZ Evaluation Board for Circuit Implementation
The DAC’s full-scale output current (IFS) is programmable from
10 mA to 30 mA. The nominal and default value is 20 mA. In
this configuration, the DAC outputs swing from 0 mA to 20 mA
across each of the four ground-referenced 50 Ω resistors (RB =
RBIP = RBIN = RBQP = RBQN). This establishes the 500 mV
dc bias level and a full-scale voltage swing of 2 V p-p differential
on each output pair (with no load). This 2 V p-p voltage swing
can be adjusted by the RL (RL = RSLI = RSLQ) shunt resistors
without affecting the 500 mV bias level. The resulting
differential peak-to-peak swing at the I/Q modulator input
is given by the equation
VSIGNAL = I FS ×
[2 × RB × RL ]
[2 × RB + RL ]
Note that the relatively high differential input impedance of the
ADL5375 (typically >60 kΩ) can be ignored when calculating
this signal level. Figure 3 shows the relationship between the
peak-to-peak voltage swing and RL when 50 Ω bias-setting
resistors are used.
The ADL5375-05 and AD9122 are well matched in terms of
dynamic range and gain. As a result, there is no need for any
active gain between the devices. The I/Q modulator drive level
can be fine tuned as needed by adjusting the value of RL as
described above. For most applications, a value of 100 Ω for
RL is recommended. This results in a full-scale signal level of
1 V p-p (DAC output at 0 dBFS).
Rev. 0 | Page 2 of 9
Circuit Note
CN-0205
2.0
0
36
1.8
MAGNITUDE
30
1.4
1.2
1.0
0.8
–20
24
GROUP DELAY
–30
18
–40
12
–50
6
GROUP DELAY (ns)
1.6
MAGNITUDE (dB)
0.6
0.4
0.2
–60
100
1k
09740-003
1
0
10
10k
RL (Ω)
10
0
100
FREQUENCY (MHz)
09740-005
DIFFERENTIAL SWING (V p-p)
–10
Figure 5. Frequency Response for DAC Modulator Interface with
10 MHz Third-Order Bessel Filter
Figure 3. Peak-to-Peak Differential Swing and the Swing Limiting
Resistor (RL) with 50 Ω Bias-Setting Resistors
Baseband Filtering
Filtering for Complex IF (CIF) Applications
A filter must be inserted between the AD9122 and ADL5375 to
remove Nyquist images, spurs, and broadband noise originating
from the DAC. The filter should be placed between the dc bias
setting resistors and the ac swing-limiting resistor. With this
configuration, the dc bias setting resistors (RB in Figure 4) and
the signal scaling resistors (RL in Figure 4) conveniently set the
source and load resistances for the filter design.
Figure 6 shows the frequency response of the ADL5375
baseband I and Q inputs. Because this device has a wide and flat
frequency response (−3 dB point = 750 MHz), it is well suited to
complex IF (CIF) applications where the output signal from the
DAC has been digitally upconverted. In CIF applications, a lowpass Nyquist filter is still desirable, primarily because the dc bias
level can be preserved from the DAC output to the modulator
input.
Figure 4 shows a third-order Bessel low-pass filter with a −3 dB
frequency of 10 MHz. Matching input and output impedances of
the filter makes the filter design easy and results in better
passband flatness, which allows wide bandwidth filter designs.
In this example, the shunt resistor chosen is 100 Ω, producing
an ac swing of 1 V p-p differential. The frequency response of
this filter is shown in Figure 5.
ADL5375-05
LPI
771.1nH
67
21
OUT1_P
RBIP
50Ω
66
OUT1_N
RBIN
50Ω
53.62pF
C1I
350.1pF
C2I
22
LNI
771.1nH
LNQ
771.1nH
59
9
OUT2_N
RBQN
50Ω
OUT2_P
RBQP
58 50Ω
53.62pF
C1Q
350.1pF
C2Q
The simulated and measured responses of this filter are shown
in Figure 8 and Figure 9. The measured flatness is ±0.6 dB from
dc to 250 MHz and ±0.4 dB from 125 MHz to 250 MHz. This
data was taken with the AD9122 inverse sinc function on. In
this configuration, Figure 10 shows the common-mode
rejection performance of the 2 × FDAC common-mode spur vs.
common-mode frequency with and without IF filter shown in
Figure 7.
IBBP
RSLI
100Ω
IBBN
QBBN
RSLQ
100Ω
10
09740-004
AD9122
The filter topology shown in Figure 7 is a 5th order Butterworth
filter with a 300 MHz corner frequency and is the
recommended filter topology. A purely differential filter can
reject differential-mode images, spurs, and noise from the DAC.
Using two capacitors with their common connection grounded
(C2 and C4 in Figure 7) diverts some of the common-mode
current to ground and results in better common-mode rejection
of high-frequency signals than would be obtained with a purely
differential filter.
QBBP
LPQ
771.1nH
Figure 4. DAC Modulator Interface with 10 MHz Third-Order, Bessel Filter
Rev. 0 | Page 3 of 9
CN-0205
Circuit Note
0
4.0
MAGNITUDE
3.5
–5
MAGNITUDE (dB)
–1.0
2.0
–15
1.5
GROUP DELAY
1.0
–2.0
–20
0.5
–3.0
1
10
–4.0
100
09740-008
0
–25
500
FREQUENCY (MHz)
Figure 8 . Frequency Response for DAC Modulator Interface with 300 MHz
Fifth-Order Butterworth Filter (Simulated)
–5.0
–6.0
1M
10M
100M
09740-006
BASEBAND FREQUENCY RESPONSE (dB)
0
2.5
–10
GROUP DELAY (ns)
3.0
1.0
1G
BB FREQUENCY (Hz)
0
Figure 6. Baseband (BB) Frequency Response of ADL5375-05
C2PI
22pF
RBIP
50Ω
66
RBIN
50Ω
IOUT1N
L1PI
33nH
C1I
3.6pF
ADL5375-05
21
IBBP
L2PI
33nH
C3I
6pF
RSLI
100Ω
–20
–30
22
L1NI
33nH
C2NI
22pF
IBBN
L2NI
33nH
C4NI
3pF
–40
0
100
200
300
400
500
FREQUENCY (MHz)
C4NQ
3pF
59
RBQN
50Ω
RBQP
50Ω
58
IOUT2P
9
L1NQ
33nH
C1Q
3.6pF
L2NQ
33nH
C3Q
6pF
QBBN
RSLQ
100Ω
0
10
L1PQ
33nH
C2PQ
22pF
QBBP
L2PQ
33nH
09740-007
IOUT2N
Figure 9. Measured Frequency Response for DAC Modulator Interface with
300 MHz Fifth-Order Butterworth Filter
C4PQ
3pF
Figure 7. Recommended DAC Modulator Interface topology with Fc =300
MHz Fifth-Order, Butterworth Filter
OUTPUT POWER OF COMMON MODE (dBm)
C2NQ
22pF
09740-009
IOUT1P
C4PI
3pF
–10
–20
–30
–40
NO FILTER
–50
–60
–70
–80
–90
WITH FILTER
–100
–110
–120
300
400
500
600
700
800
COMMON MODE FREQUENCY (MHz)
900
1000
09740-010
67
FILTER RESPONSE (dBm)
AD9122
–10
Figure10. Measured Common-Mode Rejection Performance at ADL5375-05
RF output with Filter and without Filter
Rev. 0 | Page 4 of 9
CN-0205
09740-011
Circuit Note
Figure 11. Spreadsheet to Calculate Modulator Output Power
AD9122
OUT1_P
In addition to the bias-setting and signal scaling resistors, the
power level at the output of the ADL5375 is a function of the
DAC’s digital backoff level (dBFS), the signal’s peak-to-average
ratio, the DAC’s full-scale current, the insertion loss of the
Nyquist filter, and I/Q modulator’s voltage gain. The
spreadsheet shown in Figure 11 can be used to make this
calculation.
RBIP
45.3Ω
OUT1_N
The ADL5375-15 requires a dc bias level of 1500 mV. Other
than the difference in bias levels, the ADL5375-05 and
ADL5375-15 are identical. To drive the ADL5375-15 from the
AD9122, either a passive or active level-shifting network must
be used. The passive level shifting network shown in Figure 12
uses four series resistors along with four pull-up resistors to
achieve a bias level of 1500 mV at the ADL5375-15 input. This
passive level shifting network introduces a loss of
approximately 2 dB in the signal level.
An active level shifting circuit would use a dual-differential
amplifier, such as ADA4938, where placing 1500 mV on the
VOCM pin sets the output dc bias level. In this approach,
however, the interface bandwidth is limited by the op amp.
RBIN
45.3Ω
RLIP
3480Ω
RSIP
1kΩ
RBQN
45.3Ω
58
OUT2_P
21
22
RBQP
45.3Ω
9
RLQN
3480Ω
RSQP
1kΩ
RLQP
3480Ω
IBBP
5V
RLIN
3480Ω
RSQN
1kΩ
59
OUT2_N
This spreadsheet can be downloaded using the following URL:
www.analog.com/CN0205-PowerCalculator.
Level Shifting to Drive the ADL5375-15
66
ADL5375-15
RSIN
1kΩ
67
IBBN
QBBN
5V
10
QBBP
09740-012
Calculating the Output Power of the AD9122 and the
ADL5375
Figure 12. Passive Level-Shifting Network For Biasing ADL5375-15 from the
AD9122 TxDAC
As previously mentioned, it is necessary to put a filter between
AD9122 and ADL5375-15. The LC filter can be located
anywhere between the DAC termination resistors (R1 in Figure 13)
and the ac swing-limiting resistor (R4 in Figure 13). However,
the circuit in Figure 13 allows flexibility in the design of the
level shifting circuit with low loss by R2 and a high driving
level to modulator. It also allows a matched filter at source and
load impedance. Figure 13 is the recommended passive levelshifting network with filter.
Rev. 0 | Page 5 of 9
CN-0205
Circuit Note
REQUIRED DC LEVEL
B = 1.5V
R2
A
B
R1
R3
AD9122
LC FILTER
R1
IOUT_N
A
ADL5375-15
R4
V1
R3
09740-013
IOUT_P
B
R2
Figure13. Recommended Passive Level-Shifting Network with LC Filter
The differential source impedance and load impedance of the
filter are
2 × (R1 + R2) and
To calculate dc bias level and ac swing level at the A and B
points (Figure 13), attenuation by R2, and source/load
impedances of the filter, the spreadsheet below can be used.
This can be downloaded at the following URL:
www.analog.com/CN0205-LevelShifter.
2 × {R3||(R4/2)}, respectively.
The single-ended impedance seen by DAC is
R1||{R2+R3||(R4/2)}.
R4 acts as the ac load to the DAC. The differential ac swing at
DAC output is
The ADIsimRF tool can also be used to perform DACmodulator power level calculations. The tool can be
downloaded from www.analog.com/ADIsimRF.
2 × IFS × R1||{R2+R3||(R4/2)},
and the differential ac swing at the modulator input is
Layout Recommendations
2 × {R3||(R4/2)}÷{R2+(R3||(R4/2)}
Special care should be taken in the layout of the
DAC/modulator interface. Here are some recommendations.
Figure 15 shows a top-level layout, which follows these
recommendations:
multiplied by the differential ac swing at DAC output.
MOD
FILTER
34.0
R2 (Ω)
218
R3(Ω)
760
•
Keep all I/Q differential trace lengths well matched.
R4 (Ω)
750
•
IFS (MA)
20
Place filter termination resistor as close as possible to
modulator input.
V1 (V)
5.00
•
DAC R
(SINGLE)
31.70
Place DAC output 50 Ω resistors as close as possible to
DAC.
•
DAC
COMMON VOLTAGE (V)
0.50
Thicken trace widths through the filter network to
reduce signal loss.
DAC SWING (V p_p)
(SINGLE)
•
0.63
MODULATOR
COMMON VOLTAGE (V)
Place vias around all DAC output traces, filter
networks, modulator output traces, and LO input
traces.
1.50
•
MOD INPUT SWING
(V p_p)
Route LO and modulator outputs on different layers
or at 90° angle to each other to prevent coupling.
0.34
(SINGLE)
LOSS BY R2 (DB)
–5.43
INPUT IMPEDANCE (Ω)
504
OUTPUT IMPEDANCE (Ω)
502
Figure14. Spreadsheet for the Level Shifting Circuit
09740-015
DAC
R1 (Ω)
09740-014
SETUP
The LC filter should be placed close to the DAC to allow short
return current path. The 5 V bias supply (V1) should be close
to the modulator because it is shared with the modulator. For
the case when R1, R2, R3, and R4 are 34 Ω, 218 Ω, 760 Ω, and
750 Ω, respectively, the 500 mV dc bias at the AD9122 DAC
output is matched to the 1500 mV dc bias at ADL5375-15.
Actually, it is not necessary to be 500 mV at point A of Figure
13, but it will give flexibility in the ac swing level without
exceeding the compliance voltage of the DAC output. The DAC
load is 31.7 Ω. The input and output impedance of the filter are
504 Ω and 502 Ω. The attenuation by R2, which is the voltage
drop by R2 between the DAC output and modulator input, is
set by the combination of R2 and R3||(R4/2),which is about 5.4 dB.
Figure15. General Layout Recommendations
Rev. 0 | Page 6 of 9
Circuit Note
CN-0205
0mA TO 20mA
IOUT1
50Ω
IOUT1
DPG
DATA
PATTERN
GENERATOR
FDATA
BB
FILTER
50Ω
100Ω
20mA TO 0mA
J6
AD9122
0mA TO 20mA
IOUT2
50Ω
IOUT2
DPG
USB DOWNLOADER
SOFTWARE
SPECTRUM
ANALYZER
ADL5375-05
BB
FILTER
50Ω
100Ω
20mA TO 0mA
J9
J1
AD9122-M5375-EBZ
SIGNAL
GENERATOR
FOR LO
LO
USB
FDAC
AD9122
SOFTWARE
POWER SUPPLY
09740-016
PC
5V
SIGNAL
GENERATOR
FOR FDAC
Figure 16. Test Setup Functional Block Diagram
Further insight to proper layout can be found by examining the
AD9122-M5375-EBZ layout files in the design support package
www.analog.com/CN0205-DesignSupport.
Setup and Test
1.
Connect the setup and measurement system shown in
Figure 16.
COMMON VARIATIONS
2.
Set the power supply to +5 V.
The interface described in this circuit note can be used between
any TxDAC digital-to-analog converter (AD9779A, AD9788,
AD9125, AD9148) that is set for 20 mA full-scale current and
the ADL5370, ADL5371/ADL5372, ADL5373, ADL5374,
ADL5385, ADL5386, etc., family of I/Q modulators that require
0.5 V baseband dc bias levels.
3.
Set the signal generator for FDAC to 368.64 MHz @ 5 dBm,
and the signal generator for LO to 2140 MHz @ 0 dBm.
4.
Turn on the power supply and signal generators. Set the
spectrum analyzer at 2 × FDAC MHz, 1 MHz span.
5.
Set up the AD9122 through USB at AD9122/AD9125
SPI control software as shown in Figure 17 and run.
Refer to the AD9122 Evaluation Board Quick Start
Guide in www.analog.com-CN0205-DesignSupport.
The interface can also be adapted to the AD8345/AD8349 low
current modulators, with some adjustment to the bias level by
properly selecting the DAC termination resistors.
CIRCUIT EVALUATION AND TEST
The following section describes details of performing the
common-mode test (results shown in Figure 10). The test setup
is flexible and allows other measurements shown in this circuit
note to be performed.
6.
Equipment Needed (Equivalents Can be Substituted)
• DPG : ADI Digital Pattern Generator
• Signal Generator for clock: Agilent E4437B
• Signal generator for LO: Agilent 8665B
• Spectrum analyzer: Agilent E4440A
• Power supply: Agilent E3631A
Rev. 0 | Page 7 of 9
•
Interpolation ("1" in Figure 17) : 1×
•
Fine modulation ("2" in Figure 17) : ON
•
Data rate ("3" in Figure 17) : same as FDAC
frequency
•
NCO frequency ("4" in Figure 17) : 173.32 MHz
Set up DPG (refer to AD9122 Evaluation Board Quick
Start Guide)
•
Make sure DCO frequency ("1" in Figure 18)
is close to FDAC frequency.
•
Set sample rate ("2" in Figure 18) same as
FDAC frequency and 1 MHz at desired
frequency.
CN-0205
•
Set "3" and "4 "as shown in Figure 18.
•
Download I and Q vector by clicking buttons
at "1" in Figure 18.
Measure common-mode noise levels at 2 × FDAC
8.
Change frequency of signal generator for FDAC, change
“Data Rate” mentioned in (5), and “Sample Rate”
mentioned in (6)
9.
Measure common-mode noise levels at 2 × FDAC (NEW)
09740-017
10. Repeat (8), (9)
Figure 17. SPI Control User Interface Setup for Data Clock and NCO Control
09740-018
7.
Circuit Note
Figure 18. Setting up the DPG Using the DPG Downloader Software
Rev. 0 | Page 8 of 9
Circuit Note
CN-0205
LEARN MORE
Data Sheets and Evaluation Boards
CN0205 Design Support Package:
www.analog.com/CN0205-DesignSupport
AD9122 Data Sheet
MT-016 Tutorial, Basic DAC Architectures III: Segmented DACs.
Analog Devices.
AD9122 Evaluation Board
ADL5375 Data Sheet
ADL5375-05 Evaluation Board
MT-017 Tutorial, Oversampling Interpolating DACs, Analog
Devices.
AD9122-M 5375-EBZ Evaluation Board
MT-031 Tutorial, Grounding Data Converters and Solving the
Mystery of 'AGND' and 'DGND'. Analog Devices.
REVISION HISTORY
MT-101 Tutorial, Decoupling Techniques, Analog Devices.
8/11—Revision 0: Initial Version
CN-0021 Circuit Note, Interfacing the ADL5375 I/Q Modulator
to the AD9779A Dual-Channel, 1 GSPS High Speed DAC ,
Analog Devices.
CN-0134 Circuit Note, Broadband Low EVM Direct Conversion
Transmitter, Analog Devices.
CN-0144 Circuit Note, Broadband Low EVM Direct Conversion
Transmitter Using LO Divide-by-2 Modulator, Analog
Devices.
Nash, Eamon. AN-1039 Application Note, Correcting
Imperfections in IQ Modulators to Improve RF Signal Fidelity,
Analog Devices.
Zhang, Yi. AN-1100 Application Note, Wireless Tranmitter I/Q
Balance and Sideband Suppression, Analog Devices.
Brandon, David and David Crook, Ken Gentile, AN-0996, The
Advantages of Using a Quadrature Digital Upconverter
(QDUC) in Point-to-Point Microwave Transmit Systems,
Analog Devices.
ADIsimPLL Design Tool
ADIsimRF Design Tool
AD9122 Evaluation Board Quick Start Guide
Analog Devices Data Pattern Generator (DPG)
(Continued from first page) Circuits from the Lab circuits are intended only for use with Analog Devices products and are the intellectual property of Analog Devices or its licensors. While you
may use the Circuits from the Lab circuits in the design of your product, no other license is granted by implication or otherwise under any patents or other intellectual property by
application or use of the Circuits from the Lab circuits. Information furnished by Analog Devices is believed to be accurate and reliable. However, "Circuits from the Lab" are supplied "as is"
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purpose and no responsibility is assumed by Analog Devices for their use, nor for any infringements of patents or other rights of third parties that may result from their use. Analog Devices
reserves the right to change any Circuits from the Lab circuits at any time without notice but is under no obligation to do so.
©2011 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
CN09740-0-8/11(0)
Rev. 0 | Page 9 of 9