Data Sheet
Cascadable IF VGAs with
Programmable RMS Detectors
ADL5336
FEATURES
Pair of VGAs with rms AGC detectors
VGA and AGC modes of operation
Continuous gain control range: 48 dB
Noise figure (NF) = 6.8 dB at maximum gain
IMD3 > 62 dBc for 1.0 V p-p composite output
Differential input and output
Multiplexed inputs for VGA2
Programmable detector AGC setpoints
Programmable VGA maximum gain
Power-down feature
Single 5 V supply operation
FUNCTIONAL BLOCK DIAGRAM
COM
OPP1 OPM1 IP2A IM2A COM IP2B IM2B
VCM1
VCM2
VPOS
VPOS
VGA2
VGA1
INP1
OPP2
INM1
OPM2
VPOS
X2
X2
VPOS
ADL5336
COM
COM
MODE
SDO
SPI
Point-to-multipoint radios
Instrumentation
Medical
ENBL
DATA
GAIN1 DTO1 GAIN2 DTO2 COMD VPSD
LE
CLK
09550-001
APPLICATIONS
Figure 1.
GENERAL DESCRIPTION
The ADL5336 consists of a pair of variable gain amplifiers
(VGAs) designed for cascaded IF applications. The amplifiers
have linear-in-dB gain control and operate from low frequencies to
1 GHz. Their excellent gain conformance over the control range
and flatness over frequency are due to Analog Devices, Inc.,
patented X-AMP® architecture, an innovative technique for
implementing high performance variable gain control.
Each VGA has 24 dB of gain control range. Their maximum gain
can be independently programmable over a 6 dB range via the
SPI. The VGAs can be cascaded to provide a total range of 48 dB.
When connected to a 50 Ω source through a 1:4 balun, the gain
is 6 dB higher. The second VGA has an SPI programmable input
switch that selects one of two external inputs.
When driven from a 200 Ω source or from a 50 Ω source through
a 1:4 balun, the noise figure (NF) for the composite amplifier is
6.8 dB at maximum gain. The output of each VGA can drive
100 Ω loads to 5 V p-p maximum.
Each VGA has an independent square law detector for autonomous,
automatic gain control (AGC) operation. Each detector setpoint
can be programmed independently through the SPI from −24 dBV
to −3 dBV in 3 dB steps. When both VGAs are arranged in AGC
mode and are programmed to the same setpoint, the composite NF
increases to 9 dB when backed off by 18 dB from maximum gain.
The ADL5336 operates from a 5 V supply and consumes a typical
supply current of 80 mA. When disabled, it consumes 4 mA. It is
fabricated in an advanced silicon-germanium BiCMOS process and
is available in a 32-lead exposed paddle LFCSP package. Performance
is specified over a −40°C to +85°C temperature range.
Rev. B
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.461.3113 ©2011–2012 Analog Devices, Inc. All rights reserved.
ADL5336
Data Sheet
TABLE OF CONTENTS
Features .............................................................................................. 1
Supply Decoupling ..................................................................... 20
Applications ....................................................................................... 1
Input Signal Path ........................................................................ 20
Functional Block Diagram .............................................................. 1
Output Signal Path ..................................................................... 20
General Description ......................................................................... 1
Detector Output and Gain Pin ................................................. 21
Revision History ............................................................................... 2
Common-Mode Bypassing ....................................................... 21
Specifications..................................................................................... 3
Serial Port Connections............................................................. 21
Timing Diagrams.......................................................................... 5
Mode and Enable Connections ................................................ 21
Absolute Maximum Ratings ............................................................ 6
Error Vector Magnitude (EVM) ............................................... 21
ESD Caution .................................................................................. 6
Effect of CAGC on EVM............................................................... 22
Pin Configuration and Function Descriptions ............................. 7
AGC Insensitivity to Modulation Type ................................... 22
Typical Performance Characteristics ............................................. 8
Effect of Setpoint on EVM ........................................................ 23
Theory of Operation ...................................................................... 17
Cascaded VGA/AGC Performance.......................................... 23
Circuit Description..................................................................... 17
Evaluation Board Layout ............................................................... 25
Gain Control Interface ............................................................... 18
Bill of Materials (BOM) ............................................................. 28
Input and Output Impedances.................................................. 18
Evaluation Board Control Software ......................................... 29
AGC Operation........................................................................... 18
Outline Dimensions ....................................................................... 30
Register Map and Codes ................................................................ 19
Ordering Guide .......................................................................... 30
Applications Information .............................................................. 20
Basic Connections ...................................................................... 20
REVISION HISTORY
2/12—Rev. A to Rev. B
Changes to Figure 70 ...................................................................... 25
Changes to Figure 71 and Figure 72............................................. 26
Changes to Table 11 ........................................................................ 28
Changes to Figure 73 ...................................................................... 29
Updated Outline Dimensions ....................................................... 30
6/11—Rev. 0 to Rev. A
Changes to Table 1 ............................................................................ 3
Changes to Typical Performance Charteristics
Section Format .................................................................................. 8
Changes to Figure 7 and Figure 10................................................. 8
Changes to Figure 11 to Figure 16.................................................. 9
Changes to Figure 17 to Figure 22................................................ 10
Changes to Figure 23 and Figure 26............................................. 11
Inserted Figure 53 and Figure 56; Renumbered Sequentially .. 16
Changes to Figure 60 ...................................................................... 17
Changes to Figure 61 Caption....................................................... 18
Changes to Cascaded VGA/AGC Performance Section and
Figure 68 .......................................................................................... 24
Changes to Figure 72 ...................................................................... 26
2/11—Revision 0: Initial Version
Rev. B | Page 2 of 32
Data Sheet
ADL5336
SPECIFICATIONS
VS = 5 V, TA = 25°C, ZS = 200 Ω, ZL VGA1 = 200 Ω, ZL VGA2 = 100 Ω, RF input = −20 dBm at 140 MHz, maximum gain setting for both VGAs,
unless otherwise noted. 1:4 balun voltage gain is not included. All dBm numbers are with respect to each VGA’s load impedance.
Table 1.
Parameter
OVERALL FUNCTION
Frequency Range
Maximum Input
Maximum Output
AC Input Impedance
VGA1
VGA2 Selected Input
VGA2 Unselected Input
AC Output Impedance
GAIN CONTROL INTERFACE
Voltage Gain Range
VGA1
VGA2
Gain Step Response Time
Gain Slope
VGA1
VGA2
Gain Error
Input Impedance
f = 140 MHz
Noise Figure
Output IP3
Output Voltage Level of 1.0 V p-p
Output P1dB
Test Conditions/Comments
Min
3 dB bandwidth
INP1/INM1, IP2A/IM2A, IP2B/IM2B differential
OPP1/OPM1, OPP2/OPM2 differential at P1dB
LF
Differential across INP1, INM1
Differential across IP2A, IM2A or IP2B, IM2B
VGA1
VGA2
GAIN1/GAIN2, MODE
GAIN1/GAIN2 from 0 V to 1 V
Gain Code 00
Gain Code 01
Gain Code 10
Gain Code 11
Gain Code 00
Gain Code 01
Gain Code 10
Gain Code 11
Typ
Max
Unit
1000
8
5
MHz
V p-p
V p-p
200
200
10
1
3.5
Ω
Ω
kΩ
Ω
Ω
−14.6
−12.2
−10.3
−8.9
−10.8
−8.2
−6.6
−4.7
+9.7
+12
+13.8
+15.2
+13.4
+15.9
+17.7
+19.5
dB
dB
dB
dB
dB
dB
dB
dB
8.5 dB Gain Step
5
ns
MODE = VS
VGAINx from 0.2 V to 0.8 V
VGAINx to COM
35
35
±0.2
4.6
mV/dB
mV/dB
dB
MΩ
VGA1, Gain Code 00, VGAIN = 1 V
VGA2, Gain Code 11, VGAIN = 1 V
VGA1, Gain Code 00, VGAIN = 1 V
7.4
7.1
21 (28)
dB
dB
dBV (dBm)
VGA1, Gain Code 11, VGAIN = 1 V
VGA2, Gain Code 00, VGAIN = 1 V
VGA2, Gain Code 11, VGAIN = 1 V
VGA1, Gain Code 00, VGAIN = 1 V
VGA1, Gain Code 11, VGAIN = 1 V
VGA2, Gain Code 00, VGAIN = 1 V
VGA2, Gain Code 11, VGAIN = 1 V
18 (25)
26 (36)
24 (34)
3.5(10.5)
3.5(10.5)
4 (14)
4 (14)
dBV (dBm)
dBV (dBm)
dBV (dBm)
dBV (dBm)
dBV (dBm)
dBV (dBm)
dBV (dBm)
Rev. B | Page 3 of 32
ADL5336
Parameter
f = 350 MHz
Noise Figure
Output IP3
Output Voltage Level of 1.0 V p-p
Output P1dB
SQUARE LAW DETECTORS
Output Setpoint
Output Range
AGC Step Response Range
DIGITAL LOGIC
Input High Voltage, VINH
Input Low Voltage, VINL
Input Current, IINH/IINL
Input Capacitance, CIN
SPI TIMING
fCLK
tDH
tDS
tLH
tLS
tPW
tD
POWER AND ENABLE
Supply Voltage Range
Total Supply Current
Disable Current
Disable Threshold
Enable Response Time
Disable Response Time
Data Sheet
Test Conditions/Comments
VGA1, Gain Code 00, VGAIN = 1 V
VGA2, Gain Code 11, VGAIN = 1 V
VGA1, Gain Code 00, VGAIN = 1 V
VGA1, Gain Code 11, VGAIN = 1 V
VGA2, Gain Code 00, VGAIN = 1 V
VGA2, Gain Code 11, VGAIN = 1 V
VGA1, Gain Code 00, VGAIN = 1 V
VGA1, Gain Code 11, VGAIN = 1 V
VGA2, Gain Code 00, VGAIN = 1 V
VGA2, Gain Code 11, VGAIN = 1 V
DTO1, DTO2
SPI controlled, 3 dB steps
Min
Typ
Max
8
7.7
12 (19)
10.5(17.5)
18 (28)
16 (26)
0 (7)
0 (7)
−1.5 (+8.5)
−1.5 (+8.5)
−24
0.1
5 dB input step, CAGC = 0.1 µF
LE, CLK, DATA, SDO
Unit
dB
dB
dBV (dBm)
dBV (dBm)
dBV (dBm)
dBV (dBm)
dBV (dBm)
dBV (dBm)
dBV (dBm)
dBV (dBm)
−3
VS/2
1.5
>2.2
<1.8
<1
2
dBV
V
ms
V
V
µA
pF
LE, CLK, DATA, SDO
20
5
5
5
5
5
5
DATA hold time
DATA setup time
LE hold time
LE setup time
CLK high pulse width
CLK-to-SDO delay
VPOS, VPSD, COM, COMD, ENBL
4.5
ENBL = 5 V
ENBL = 0 V
Delay following low-to-high transition until
device meets full specifications in VGA mode
Delay following high-to-low transition until
device produces full attenuation in VGA mode
Rev. B | Page 4 of 32
5
80
4
2.3
800
20
MHz
ns
ns
ns
ns
ns
ns
5.5
V
mA
mA
V
ns
ns
Data Sheet
ADL5336
TIMING DIAGRAMS
tPW
tCLK
CLK
tLH
tLS
LE
tDS
DATA
tDH
WRITE BIT
LSB
LSB + 1
LSB + 2
LSB + 3
MSB – 3
MSB – 2
MSB – 1
MSB
09550-002
NOTES
1. THE FIRST DATA BIT DETERMINES WHETHER THE PART IS WRITING TO OR READING FROM THE INTERNAL 8-BIT REGISTER. FOR A WRITE
OPERATION, THE FIRST BIT SHOULD BE A LOGIC 1. THE 8-BIT WORD IS THEN REGISTERED INTO THE DATA PIN ON CONSECUTIVE RISING
EDGES OF THE CLOCK.
Figure 2. Write Mode Timing Diagram
tPW
tCLK
tD
CLK
tLH
tLS
LE
DATA
SDO
tDH
READ BIT
DC
LSB
DC
LSB + 1
DC
DC
LSB + 2
LSB + 3
DC
MSB – 3
DC
MSB – 2
DC
MSB – 1
DC
MSB
NOTES
1. THE FIRST DATA BIT DETERMINES WHETHER THE PART IS WRITING TO OR READING FROM THE INTERNAL 8-BIT REGISTER. FOR A READ
OPERATION, THE FIRST BIT SHOULD BE A LOGIC 0. THE 8-BIT WORD IS THEN UPDATED AT THE SDO PIN ON CONSECUTIVE FALLING EDGES
OF THE CLOCK.
Figure 3. Read Mode Timing Diagram
Rev. B | Page 5 of 32
09550-003
tDS
ADL5336
Data Sheet
ABSOLUTE MAXIMUM RATINGS
Table 2.
Parameter
Supply Voltages (VPOS, VPSD)
LE, CLK, DATA, SDO
ENBL, MODE
INP1, INM1, IP2A, IM2A, IP2B, IM2B
OPP1, OPM1, OPP2, OPM2
DTO1, DTO2, GAIN1, GAIN2
Internal Power Dissipation
θJA (With Pad Soldered to Board)
Maximum Junction Temperature
Operating Temperature Range
Storage Temperature Range
Lead Temperature (Soldering, 60 sec)
Rating
5.5 V
VPOS + 0.5 V
VPOS + 0.5 V
VPOS + 0.5 V
VPOS + 0.5 V
VPOS/2 + 0.5 V
530 mW
37.4°C/W
150°C
−40°C to +85°C
−65°C to +150°C
300°C
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
ESD CAUTION
Rev. B | Page 6 of 32
Data Sheet
ADL5336
32
31
30
29
28
27
26
25
COM
OPP1
OPM1
IP2A
IM2A
COM
IP2B
IM2B
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
1
2
3
4
5
6
7
8
PIN 1
INDICATOR
ADL5336
TOP VIEW
(Not to Scale)
24
23
22
21
20
19
18
17
VCM2
VPOS
OPP2
OPM2
VPOS
COM
SDO
DATA
NOTES
1. EXPOSED PADDLE. CONNECT TO LOW
IMPEDANCE GROUND PAD.
09550-004
GAIN1
DTO1
GAIN2
DTO2
COMD
VPSD
LE
CLK
9
10
11
12
13
14
15
16
VCM1
VPOS
INP1
INM1
VPOS
COM
MODE
ENBL
Figure 4. Pin Configuration
Table 3. Pin Function Descriptions
Pin No.
1, 24
2, 5, 14, 20, 23
3, 4, 25, 26, 28, 29
6, 13, 19, 27, 32
7
8
9, 11
10, 12
15, 16, 17, 18
21, 22, 30, 31
Mnemonic
VCM1, VCM2
VPOS, VPSD
INP1, INM1, IM2B,
IP2B, IM2A, IP2A
COM, COMD
MODE
ENBL
GAIN1, GAIN2
DTO1, DTO2
LE, CLK, DATA, SDO
OPM2, OPP2,
OPM1, OPP1
EP
Description
Common-Mode Voltages. Decouple to common for ac-coupled operation.
Analog and Digital Positive Supply Voltage (4.5 V to 5.5 V).
Differential Inputs. 200 Ω input impedance; ac coupling recommended.
Analog and Digital Common. Connect via lowest possible impedance to external circuit common.
Gain Mode Control. Pull high for VGA mode, and pull low for AGC mode.
Chip Enable. Pull high to enable.
Analog Gain Control (0 V to 1 V).
Detector Outputs (0.1 V to VPOS/2 Range).
SPI Programming and Data Readout Pins. CMOS levels VLOW < 1.8 V, VHIGH > 2.2 V.
Differential Outputs. Low output impedance; ac coupling recommended.
Exposed Paddle. Connect to low impedance ground pad.
Rev. B | Page 7 of 32
ADL5336
Data Sheet
TYPICAL PERFORMANCE CHARACTERISTICS
VS = 5 V, TA = 25°C, ZS = 200 Ω, ZL VGA1 = 200 Ω, ZL VGA2 = 100 Ω, RF input = −20 dBm at 140 MHz, unless otherwise noted. Gain code =
11, VGAIN = 1 V, setpoint code = 000, MODE = 5 V (VGA mode) for both amplifiers, unless otherwise noted.
20
30
20
10
VOLTAGE GAIN (dB)
–10
GAIN1
0mV
200mV
400mV
600mV
800mV
1000mV
–30
–10
–20
GAIN2
–30
0mV
200mV
400mV
600mV
800mV
1000mV
–40
–40
10M
100M
–50
10M
09550-005
–20
0
1G
FREQUENCY (Hz)
100M
09550-008
VOLTAGE GAIN (dB)
10
0
1G
FREQUENCY (Hz)
Figure 5. Gain vs. Frequency over VGAIN at Gain Code 11 for VGA1
Figure 8. Gain vs. Frequency over VGAIN at Gain Code 11 for VGA2
5
10
5
0
VOLTAGE GAIN (dB)
VOLTAGE GAIN (dB)
0
–5
–10
–15
–5
–10
–15
–20
–30
10M
09550-006
1G
FREQUENCY (Hz)
Figure 6. Gain vs. Frequency over Gain Code at VGAIN = 0.5 V for VGA1
140MHz
350MHz
140MHz
350MHz
25
4
140MHz
350MHz
140MHz
350MHz
1.5
20
3
2
0
0
–0.5
ERROR (dB)
0.5
5
VOLTAGE GAIN (dB)
1.0
10
–5
15
1
0
10
–1
5
–2
–1.0
0
–10
–3
–1.5
–15
0
100
200
300
400
500
600
700
800
900
–2.0
1000
GAIN1 (mV)
09550-007
VOLTAGE GAIN (dB)
1G
Figure 9. Gain vs. Frequency over Gain Code at VGAIN = 0.5 V for VGA2
2.0
20
100M
FREQUENCY (Hz)
ERROR (dB)
–25
100M
15
GAIN CODE 00
GAIN CODE 01
GAIN CODE 10
GAIN CODE 11
–25
09550-009
GAIN CODE 00
GAIN CODE 01
GAIN CODE 10
GAIN CODE 11
Figure 7. Gain vs. VGAIN over Frequency at Gain Code 11 for VGA1
–5
0
100
200
300
400
500
600
700
800
900
–4
1000
GAIN1 (mV)
Figure 10. Gain vs. VGAIN over Frequency at Gain Code 11 for VGA2
Rev. B | Page 8 of 32
09550-010
–20
ADL5336
25
4
15
3
20
3
10
2
15
5
1
0
0
–5
–1
200
300
400
500
600
700
800
900
–2
–5
–3
1000
–10
GAIN1 (mV)
0
200
300
400
500
600
700
800
900
GAIN1 (mV)
40
30
30
23
35
25
25
18
30
20
25
15
20
13
20
10
15
8
15
5
10
0
5
–2
0
100
200
300
400
500
600
700
800
900
–7
1000
GAIN1 (mV)
OIP3 (dBm re: 100Ω)
3
–5
5
0
09550-114
10
OIP3 (dBV)
GAIN CODE 11
GAIN CODE 00
0
GAIN CODE 11
GAIN CODE 00
0
18
20
13
15
8
10
3
5
–2
4.8
4.9
5.0
5.1
5.2
5.3
5.4
–7
5.5
VPOS (V)
OIP3 (dBm re: 100Ω)
25
OIP3 (dBV)
23
4.7
200
300
400
500
600
700
800
900
–10
1000
GAIN2 (mV)
09550-015
30
4.6
100
Figure 15. OIP3 vs. VGAIN over Gain Code for VGA2
Figure 12. OIP3 vs. VGAIN over Gain Code for VGA1
0
4.5
ERROR (dB)
–4
1000
28
35
OIP3 (dBm re: 200Ω)
100
–3
Figure 14. Gain Conformance over Temperature for VGA2
Figure 11. Gain Conformance over Temperature for VGA1
OIP3 (dBm re: 200Ω)
–2
–40°C
+25°C
+85°C
–40°C
+25°C
+85°C
09550-014
100
–1
0
OIP3 (dBV)
0
0
5
09550-017
–15
1
10
Figure 13. OIP3 vs. Supply Voltage at VGAIN = 0.5 V for VGA1
40
30
35
25
30
20
25
15
20
10
15
5
10
0
5
–5
0
4.5
4.6
4.7
4.8
4.9
5.0
5.1
5.2
5.3
5.4
–10
5.5
VPOS (V)
Figure 16. OIP3 vs. Supply Voltage at VGAIN = 0.5 V for VGA2
Rev. B | Page 9 of 32
OIP3 (dBV)
–10
2
09550-018
–40°C
+25°C
+85°C
–40°C
+25°C
+85°C
VOLTAGE GAIN (dB)
4
ERROR (dB)
20
09550-011
VOLTAGE GAIN (dB)
Data Sheet
28
30
23
25
18
20
13
15
8
10
3
5
–2
150
200
250
300
350
400
450
–7
500
FREQUENCY (MHz)
35
25
30
20
25
15
20
10
15
5
10
0
5
–5
0
0
150
200
250
300
350
400
450
–10
500
Figure 20. OIP3 vs. Frequency over Temperature for VGA2
6
12
5
14
4
10
3
12
2
10
0
8
1
8
–2
6
–1
6
–4
4
–3
4
–6
2
–5
0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
–7
1.0
GAIN1 (V)
–8
2
GAIN CODE 11
GAIN CODE 00
0
09550-020
0
OP1dB (dBm re: 100Ω)
16
GAIN CODE 11
GAIN CODE 00
OP1dB (dBV)
7
14
OP1dB (dBm re: 200Ω)
100
FREQUENCY (MHz)
Figure 17. OIP3 vs. Frequency over Temperature for VGA1
0
15
16
6
–4
4
–6
–10
2
–8
–12
500
0
–6
–1
–8
–3
400
450
FREQUENCY (MHz)
OP1dB (dBm re: 100Ω)
1
OP1dB (dBV)
–4
09550-019
3
350
–10
1.0
–2
–2
300
0.9
8
5
250
0.8
0
0
200
0.7
10
7
150
0.6
2
2
100
0.5
12
9
50
0.4
14
4
0
0.3
6
–40°C
+25°C
+85°C 4
11
–5
0.2
GAIN2 (V)
8
–40°C
+25°C 6
+85°C
13
0.1
Figure 21. OP1dB vs. VGAIN over Gain Code for VGA2
Figure 18. OP1dB vs. VGAIN over Gain Code for VGA1
OP1dB (dBm re: 200Ω)
50
OP1dB (dBV)
100
30
09550-022
50
40
Figure 19. OP1dB vs. Frequency over Temperature for VGA1
0
50
100
150
200
250
300
350
400
450
–10
500
FREQUENCY (MHz)
Figure 22. OP1dB vs. Frequency over Temperature for VGA2
Rev. B | Page 10 of 32
OP1dB (dBV)
0
45
09550-021
0
OIP3 (dBm re: 100Ω)
OIP3 (dBm re: 200Ω)
35
40
–40°C
+25°C
+85°C 35
50
33
OIP3 (dBV)
–40°C
+25°C
+85°C
09550-013
40
OIP3 (dBV)
Data Sheet
09550-016
ADL5336
3
8
1
6
–1
4
–3
2
–5
4.6
4.7
4.8
4.9
5.0
5.1
5.2
5.3
5.4
–7
5.5
VPOS (V)
6
14
4
12
2
10
0
8
–2
6
–4
4
–6
2
–8
0
4.5
09550-023
0
4.5
16
4.6
5.0
5.1
5.2
5.3
5.4
–10
5.5
40
25
30
NOISE FIGURE (dB)
30
20
15
25
20
15
10
10
5
5
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
1.0
VGAIN1 (V)
0
Figure 24. Noise Figure vs. VGAIN1 over Supply and Temperature for VGA1
0
14
11
13
10
12
NOISE FIGURE (dB)
15
9
8
7
6
100
200
0.5
0.6
0.7
0.8
0.9
1.0
11
10
9
8
GAIN CODE 00
GAIN CODE 01
GAIN CODE 10
GAIN CODE 11
6
300
400
500
FREQUENCY (MHz)
600
700
800
5
09550-033
0
0.4
7
GAIN CODE 00
GAIN CODE 01
GAIN CODE 10
GAIN CODE 11
3
0.3
Figure 27. Noise Figure vs. VGAIN2 over Supply and Temperature for VGA2
12
4
0.2
VGAIN2 (V)
13
5
0.1
0
100
200
300
400
500
FREQUENCY (MHz)
Figure 25. Noise Figure vs. Frequency over Maximum Gains for VGA1
600
700
800
09550-034
0.1
09550-030
0
4.5Vdc/–40°C
5.0Vdc/–40°C
5.5Vdc/–40°C
4.5Vdc/+25°C
5.0Vdc/+25°C
5.5Vdc/+25°C
4.5Vdc/+85°C
5.0Vdc/+85°C
5.5Vdc/+85°C
35
09550-031
4.5Vdc/–40°C
5.0Vdc/–40°C
5.5Vdc/–40°C
4.5Vdc/+25°C
5.0Vdc/+25°C
5.5Vdc/+25°C
4.5Vdc/+85°C
5.0Vdc/+85°C
5.5Vdc/+85°C
35
NOISE FIGURE (dB)
4.9
Figure 26. OP1dB vs. Supply Voltage for VGA2
40
NOISE FIGURE (dB)
4.8
VPOS (V)
Figure 23. OP1dB vs. Supply Voltage for VGA1
0
4.7
09550-026
10
OP1dB (dBV)
5
OP1dB (dBm re: 200Ω)
12
OP1dB (dBV)
ADL5336
OP1dB (dBm re: 100Ω)
Data Sheet
Figure 28. Noise Figure vs. Frequency over Maximum Gains for VGA2
Rev. B | Page 11 of 32
ADL5336
Data Sheet
80
70
70
60
50
50
IMD3 (dBc)
IMD3 (dBc)
60
40
40
30
30
20
0
100
200
300
400
500
600
700
800
900
1000
GAIN1 (mV)
0
0
100
200
140MHz
140MHz
350MHz
350MHz
300
400
500
600
700
800
900
1000
GAIN2 (mV)
Figure 32. IMD3 vs. VGAIN over Frequency and Gain Code, VOUT = 1 V p-p
Composite, 2 MHz Spacing for VGA2
GAIN2 (100mV/DIV)
GAIN1 (100mV/DIV)
Figure 29. IMD3 vs. VGAIN over Frequency and Gain Code, VOUT = 1 V p-p
Composite, 2 MHz Spacing for VGA1
GAIN1
RF OUTPUT
GAIN2
09550-039
09550-036
RF OUTPUT (20mV/DIV)
RF OUTPUT (20mV/DIV)
RF OUTPUT
TIME (100ns/DIV)
TIME (100ns/DIV)
Figure 30. VGAIN Step Response (VGA Mode) over Gain Step, VIN = 100 mV p-p
for VGA1
Figure 33. VGAIN Step Response (VGA Mode) over Gain Step, VIN = 100 mV p-p
for VGA2
90
50
80
45
40
SUPPLY CURRENT (mA)
70
60
50
40
30
35
30
25
20
15
20
10
10
5
0
–40
–20
0
20
40
TEMPERATURE (°C)
60
80
0
–40
09550-131
SUPPLY CURRENT (mA)
GAIN CODE 00,
GAIN CODE 11,
GAIN CODE 00,
GAIN CODE 11,
10
–20
0
20
40
TEMPERATURE (°C)
Figure 31. Supply Current (VGA1 Switch Disabled) over Temperature
Rev. B | Page 12 of 32
60
80
09550-134
0
140MHz
140MHz
350MHz
350MHz
09550-029
GAIN CODE 11,
GAIN CODE 00,
GAIN CODE 00,
GAIN CODE 11,
10
09550-132
20
Figure 34. Supply Current (VGA2 Switch Enabled) over Temperature
1.5
100
1.0
50
0.5
0
100M
FREQUENCY (Hz)
100
1.0
50
–15
–40
–20
–50
–25
–60
–30
–70
–35
–80
–40
–90
1000
0
100
200
300
400
500
600
700
800
900
S11 MAGNITUDE (dB)
–30
S11 PHASE (Degrees)
–10
GAIN1 (mV)
09550-042
–20
0
100M
FREQUENCY (Hz)
–10
–5
0.5
GAIN CODE 00
GAIN CODE 11
GAIN CODE 00
GAIN CODE 11
Figure 38. Input Resistance and Capacitance vs. Frequency for VGA2
0
–70
–2
–75
–4
–80
–6
–85
–8
–90
–10
–95
–12
–100
–14
–105
–16
–110
–18
–115
–20
0
200
400
600
800
–120
1000
GAIN2 (mV)
Figure 39. S11 (re: 200 Ω) Magnitude and Phase vs. VGAIN for VGA2
Figure 36. S11 (re: 200 Ω) Magnitude and Phase vs. VGAIN for VGA1
10MHz
10MHz
3GHz
500MHz
500MHz
3GHz
GAIN CODE 00
GAIN CODE 11
09550-043
S11 MAGNITUDE (dB)
1.5
0
10M
Figure 35. Input Resistance and Capacitance vs. Frequency for VGA1
0
150
GAIN CODE 00
GAIN CODE 11
Figure 40. S11 (re: 50 Ω) vs. Frequency over VGAIN for VGA2
Figure 37. S11 (re: 50 Ω) vs. Frequency over VGAIN for VGA1
Rev. B | Page 13 of 32
09550-046
0
10M
GAIN CODE 00
GAIN CODE 11
GAIN CODE 00
GAIN CODE 11
2.0
PARALLEL INPUT CAPACITANCE (pF)
150
200
09550-044
2.0
2.5
S11 PHASE (Degrees)
200
250
09550-045
2.5
PARALLEL INPUT RESISTANCE (Ω)
250
PARALLEL INPUT CAPACITANCE (pF)
ADL5336
09550-041
PARALLEL INPUT RESISTANCE (Ω)
Data Sheet
ADL5336
Data Sheet
3GHz
3GHz
500MHz
500MHz
10MHz
GAIN CODE 00
GAIN CODE 11
5
200
5
180
4
190
4
170
3
180
3
160
2
170
2
150
1
160
1
140
0
130
–1
120
–2
110
140
–2
130
–3
120
–3
100
–4
110
–4
90
100
1000
–5
0
100
200
300
400
500
600
700
800
900
GAIN1 (mV)
0
5
7
3
6
5
2
4
1
3
2
0
35
SERIES OUTPUT RESISTANCE (Ω)
4
8
40
SERIES OUTPUT INDUCTANCE (nH)
GAIN CODE 00
GAIN CODE 11
GAIN CODE 00
GAIN CODE 11
800
80
1000
8
GAIN CODE 00
GAIN CODE 11
GAIN CODE 00
GAIN CODE 11
7
6
30
5
25
4
20
3
15
2
10
1
5
1
0
10M
600
Figure 45. S22 (re: 100 Ω) Magnitude and Phase vs. VGAIN for VGA2
100M
FREQUENCY (Hz)
–1
09550-049
SERIES OUTPUT RESISTANCE (Ω)
9
400
GAIN2 (mV)
Figure 42. S22 (re: 200 Ω) Magnitude and Phase vs. VGAIN for VGA1
10
200
Figure 43. Series Output Resistance and Inductance vs.
Frequency over VGAIN for VGA1
0
10M
0
–1
100M
FREQUENCY (Hz)
Figure 46. Series Output Resistance and Inductance vs.
Frequency over VGAIN for VGA2
Rev. B | Page 14 of 32
09550-052
–5
09550-051
S22 MAGNITUDE (dB)
150
09550-048
0
–1
S22 PHASE (Degrees)
Figure 44. S22 (re: 50 Ω) vs. VGAIN over Gain Code for VGA2
S22 PHASE (Degrees)
S22 MAGNITUDE (dB)
Figure 41. S22 (re: 50 Ω) vs. VGAIN over Gain Code for VGA1
SERIES OUTPUT INDUCTANCE (nH)
GAIN CODE 00
GAIN CODE 11
09550-050
09550-047
10MHz
RF INPUT
(200mV/DIV)
ADL5336
DETO1
DETO2
RF OUTPUT
09550-053
RF OUTPUT
(200mV/DIV)
RF OUTPUT
RF OUTPUT
(500mV/DIV)
RF INPUT
DETO2
(200mV/DIV)
DETO1
(100mV/DIV)
RF INPUT
TIME (1ms/DIV)
TIME (1ms/DIV)
Figure 47. RSSI Step Response (AGC Mode) for VGA1
0.14
09550-056
RF INPUT
(500mV/DIV)
Data Sheet
Figure 50. RSSI Step Response (AGC Mode) for VGA2
0.25
140 MHz
350 MHz
0.12
140MHz
350MHz
0.20
VOUT (V rms)
VOUT (V rms)
0.10
0.08
0.06
0.15
0.10
0.04
0.05
–45
–40
–35
–30
–25
–20
–15
–10
–5
PIN (dBm)
Figure 48. VOUT vs. Input Power (PIN) over Frequency (AGC Mode) for VGA1
0.7
VOUT (V rms)
0.6
SETPOINT
SETPOINT
SETPOINT
SETPOINT
SETPOINT
SETPOINT
SETPOINT
SETPOINT
1.4
1.2
1.0
0.4
0.3
–30
–25
–20
–15
–10
–5
SETPOINT
SETPOINT
SETPOINT
SETPOINT
SETPOINT
SETPOINT
SETPOINT
SETPOINT
000
010
100
110
001
011
101
111
–40
–30
0.8
0.6
0.4
0.2
0.2
0.1
–35
–30
–25
–20
–15
–10
PIN (dBm)
–5
0
5
10
0
–45
09550-149
0
–40
–35
Figure 51. VOUT vs. Input Power (PIN) over Frequency (AGC Mode) for VGA2
000
010
100
110
001
011
101
111
0.5
–40
–35
–25
–20
–15
PIN (dBm)
Figure 49. VOUT vs. Input Power (PIN) over Setpoint (AGC Mode) for VGA1
–10
–5
0
5
10
09550-152
0.8
–45
PIN (dBm)
VOUT (V rms)
0.9
0
–50
09550-148
0
–50
09550-151
0.02
Figure 52. VOUT vs. Input Power (PIN) over Setpoint (AGC Mode) for VGA2
Rev. B | Page 15 of 32
ADL5336
0.30
Data Sheet
0.20
–40°C
+25°C
+85°C
0.18
0.25
0.16
0.14
VOUT (V rms)
0.20
VOUT (V rms)
–40°C
+25°C
+85°C
0.15
0.10
0.12
0.10
0.08
0.06
0.04
0.05
–40
–35
–30
–25
–20
–15
–10
–5
PIN (dBm)
0
–50
–40
–35
–30
–25
–20
–20
–10
VOLTAGE GAIN ISOLATION (dB)
0
–40
–60
–80
–100
–30
–40
–50
IN2(a) TO OUT2
IN2(b) TO OUT2
–60
10
09550-059
100
–5
–20
IN2(a) TO OUT1
IN1 TO OUT2
FREQUENCY (MHz)
–10
Figure 56. VOUT vs. Input Power (PIN) over temperature for VGA2
0
–120
10
–15
PIN (dBm)
Figure 53. VOUT vs. Input Power (PIN) over temperature for VGA1
VOLTAGE GAIN ISOLATION (dB)
–45
09550-062
–45
09550-157
–50
09550-158
0.02
0
–55
100
FREQUENCY (MHz)
Figure 54. Amplifier Isolation vs. Frequency; VGA1 Differential Input (IN1) to
VGA2 Differential Output (OUT2); VGA2 Differential Input A (IN2(a)) to VGA1
Differential Output (OUT1)
Figure 57. VGA2 Input Switch Isolation vs. Frequency; VGA2 Disabled
Differential Input (IN2(a), IN2(b)) to VGA2 Differential Output (OUT2)
80
60
70
50
40
CMRR (dB)
50
40
30
30
20
20
0
10M
100M
FREQUENCY (Hz)
1G
Figure 55. CMRR vs. Frequency for VGA1
0
10M
100M
FREQUENCY (Hz)
Figure 58. CMRR vs. Frequency for VGA2
Rev. B | Page 16 of 32
1G
09550-156
10
10
09550-154
CMRR (dB)
60
Data Sheet
ADL5336
THEORY OF OPERATION
The weighted sum of the different tap points is fed into the
programmable gain stage. The programmable gain stage achieves
its different gain settings by changing the feedback network of
the amplifier.
CIRCUIT DESCRIPTION
The ADL5336 contains two differential VGAs, each with a
programmable, internally connected, square law detector. VGA2
includes an input select switch that allows the user to choose
between two sets of differential inputs.
The input attenuator and gm stages provide analog gain control
of 24 dB, whereas the programmable gain amplifier sets the
maximum gain of each VGA.
The signal path of each VGA, shown in Figure 59 and
Figure 60, consists of a variable input attenuator followed by
a programmable gain amplifier (PGA).
Table 4. VGA Gain Range
The input attenuator is built from an 18-section resistor ladder,
providing 1.34 dB of attenuation at each successive tap point.
The resistor ladder acts as a linear input attenuator, in addition
to providing an accurate 200 Ω input impedance. The variable
transconductance (gm) stages are used to select the attenuated
signal from the appropriate tap point along the ladder and feed
this signal to the fixed gain amplifier. To realize a continuous
gain control function from discrete tap points, the gain interpolator
creates a weighted sum of signals appearing on adjacent tap points
by carefully controlling the variable gm stages.
Maximum Gain Word
VGA1
VGA2
0
0
0
1
1
0
1
1
VGA1 Range (dB)
−14.5 to +9.5
−12 to +12.0
−10 to +14.0
−8.4 to +15.6
MODE
GAIN INTERPOLATOR
GAIN1
PGA
OPP1
OPM1
gm STAGES
–1.4dB
–2.8dB
–22.4dB
–23.8dB
PGA LINEAR
VOLTAGE GAIN:
G = 3, 4, 5, 6
200Ω
INM1
ATTENUATOR LADDER
09550-065
0dB
INP1
Figure 59. VGA1 Functional Block Diagram
MODE
GAIN INTERPOLATOR
GAIN2
PGA
OPP2
OPM2
gm STAGES
IP2B
IM2A
0dB
–1.4dB
–2.8dB
–22.4dB
–23.8dB
PGA LINEAR
VOLTAGE GAIN:
G = 5, 7, 9, 11
200Ω
ATTENUATOR LADDER
IM2B
Figure 60. VGA2 Functional Block Diagram
Rev. B | Page 17 of 32
09550-066
IP2A
VGA2 Range (dB)
−10 to +14
−7.1 to +16.9
−5 to +19
−3.1 to +20.9
ADL5336
Data Sheet
GAIN CONTROL INTERFACE
AGC OPERATION
The ADL5336 has a linear-in-dB gain control interface that can
operate in either a gain-up mode or gain-down mode. In the
gain-up mode, with the MODE pin pulled high, the gain increases
with increasing gain voltages. In the gain-down mode, with the
MODE pin pulled low, the gain decreases with increasing gain
voltages. In both modes of operation, the gain control slope is
maintained at +37.5 dB/V or −38 dB/V (depending on mode
selection) over temperature, supply, and process as VGAIN varies
from 100 mV to 900 mV. To form an AGC loop with the on-board
detector around the VGA, the MODE pin has to be pulled low.
The internally connected square law detectors are connected to
the outputs of the VGAs through a programmable attenuator.
The detector compares the output of the attenuator to an
internal reference of 63 mV rms. The AGC loop is closed by
connecting the DTO1/DTO2 pins to the GAIN1/GAIN2 pins,
and having the MODE pin pulled low, configuring the VGAs
for a negative gain slope.
Each VGA has 24 dB of gain range that can be shifted as the
maximum gain is programmed.
The gain functions for MODE pulled high and low are given
respectively by
GainHIGH (dB) = 37.5 × VGAIN − 14
If the amplifier is operated in VGA mode or the detector is not
otherwise being used, the setpoint should be programmed to
maximum attenuation so that the VGA output does not overdrive
the input to the detector, adversely affecting both the detector
and VGA output.
GainLOW (dB) = −38 × VGAIN + 24.8
3
15
2
10
1
5
0
0
–1
VGA1 GAIN
VGA1 GAIN
VGA2 GAIN
VGA2 GAIN
VGA1 ERROR
VGA1 ERROR
VGA2 ERROR
VGA2 ERROR
–5
–10
–15
0
0.1
0.2
0.3
0.4
0.5
0.6
–2
SPI
SETPOINT
CONTROL
X2
GAIN1/
GAIN2
–3
0.7
0.8
VGAIN1/VGAIN2 (V)
0.9
–4
1.0
+
–
REF
63mV rms
DTO1/
DTO2
CAGC
Figure 61. Gain and Conformance Error vs. VGAIN1/VGAIN2 for Gain Code 11, and
MODE = 0 V and MODE = 5 V for Both VGAs
X2
09550-073
20
CONFORMANCE ERROR (dB)
4
09550-067
GAIN (dB)
where VGAIN is expressed in volts.
25
If the attenuator is programmed to pass the full VGA output,
the AGC forces the output of the VGA to 63 mV rms, as long
as the gain required is within the gain range of the VGA. If the
attenuator is programmed to attenuate the VGA output by 21 dB
(Setpoint Word 111) and the AGC loop is closed, the AGC
function forces the VGA output to 707 mV rms. If the gain
required to achieve the programmed target output level is out of
the VGA range, the GAINx pin rails to either VPOS/2 or GND.
Figure 62. RMS Detection Diagram (Shows the Signal Path from VGA1/VGA2
Output to Squarer Cell)
INPUT AND OUTPUT IMPEDANCES
The ADL5336 offers differential broadband, 200 Ω input
impedance. The output of each VGA is a low impedance buffer
with negative feedback within the programmable gain amplifier.
The negative feedback reduces the output impedance at low
frequencies, but the output impedance increases with increasing
frequency above 300 MHz.
Rev. B | Page 18 of 32
Data Sheet
ADL5336
REGISTER MAP AND CODES
Table 5. Register Map
MSB
B10
B9
VGA2 Maximum Gain
B8
B7
VGA1 Maximum Gain
B6
B5
VGA2 Switch
B4 B3
VGA2 Setpoint
Table 6. RMS Output Setpoint Map
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
Setpoint Word
0
1
0
1
0
1
0
1
RMS Output (mV rms/dBV)
+62.5/−24
+88/−21
+125/−18
+176/−15
+250/−12
+353/−9
+500/−6
+707/−3
Table 7. VGA2 Input Switch Logic
VGA2 Switch
0
1
Selected Input
IP2A, IM2A
IP2B, IM2B
Table 8. Maximum Gain Map
0
0
1
1
Maximum Gain Word
0
1
0
1
VGA1 Maximum Gain (dB)
9.5
12.0
14.0
15.6
Rev. B | Page 19 of 32
VGA2 Maximum Gain (dB)
14
16.9
19
20.9
B2
LSB
B1
B0
VGA1 Setpoint
ADL5336
Data Sheet
APPLICATIONS INFORMATION
BASIC CONNECTIONS
INPUT SIGNAL PATH
The basic connections for a typical ADL5336 application are
shown in Figure 63.
The ADL5336 has three input signal paths, two of which inputs
go to VGA2 via an internal switch, and the other input goes to
VGA1. Each of the three pairs of input pins (INP1/INM1,
IP2A/IM2A, and IP2B/IM2B) has a differential input impedance of
200 Ω. To obtain maximum power transfer, the driving source
impedance also needs to be 200 Ω. On the evaluation board,
this is achieved via a 4:1 impedance ratio balun. The evaluation
board schematic is shown in Figure 70. For more information
on the input signal paths, refer to the Input Signal Path section.
The input common-mode voltage sits at roughly VPOS/2 for
both VGAs, except on VGA2; the nonselected input of VGA2
has an input common-mode voltage that sits at roughly ground.
SUPPLY DECOUPLING
A nominal supply voltage of 5.0 V should be applied to the supply
pins. The supply voltage should be between the limits of 4.5 V
and 5.5 V. All of the supply pins must be decoupled to ground
with at least one low inductance, surface-mount ceramic capacitor
of 0.1 µF. Place these decoupling capacitors as close as possible
to the ADL5336 device. The ADL5336 has an analog supply and
a digital supply. Take care to separate the two supplies with a
large surface-mount inductor of 33 µH, and each supply must
then be decoupled separately to their respective grounds through a
10 µF capacitor. The ADL5336 also has two separate grounds: an
analog ground and a digital ground. Again, a large surface-mount
inductor of 33 µH should be used to separate the grounds.
INPUT 3
BALUN
INPUT 1
INPUT 1
BALUN
INPUT 3
IM2B
IP2B
COM
IM2A
IP2A
OPM1
OPP1
OUTPUT 1
BALUN
COM
+5V
There are two output signal paths on the ADL5336; one signal
path per VGA. The output of VGA1 can be ac-coupled into either
of the inputs of VGA2, which cascades the two VGAs, or ac-coupled
into a 200 Ω termination impedance. VGA1 is designed to drive a
200 Ω differential load, whereas VGA2 is designed to drive a 100 Ω
differential load. On the evaluation board, a 100 Ω differential
impedance is presented to the output of VGA2. This is achieve
via a 1:1 balun and a resistive matching network. For more
information on the evaluation board, see the evaluation board
schematic in Figure 70. The output common-mode voltage on
both VGAs sits at roughly VPOS/2.
INPUT 2
BALUN
INPUT 2
OUTPUT 1
OUTPUT SIGNAL PATH
VCM1
VCM2
VPOS
VPOS
INP1
OPP2
INM1
OPM2
+5V
OUTPUT 2
BALUN
OUTPUT 2
ADL5336
SDO
+5V
SPI CONTROL
Figure 63. Basic Connections Schematic
Rev. B | Page 20 of 32
09550-075
CLK
DATA
LE
ENBL
VPSD
MODE
COMD
COM
DTO2
COM
GAIN2
VPOS
VPOS
DTO1
VPOS
VPOS
GAIN1
+5V
Data Sheet
ADL5336
DETECTOR OUTPUT AND GAIN PIN
MODE AND ENABLE CONNECTIONS
The ADL5336 has a pair of detector squaring cells. Each squaring
cell has a VGA output applied to its input. This is shown Figure 1
and Figure 62. These on-board detector squaring cells are used to
achieve an AGC function with the VGAs. Each of the squared
output signals is compared to a reference signal and the difference
is then output in a current-mode signal. The DTO1 pin is the
detector squaring cell output that taps off of the output VGA1,
and the DTO2 pin is the detector squaring cell output that taps
off of the output of VGA2. By shorting the DTO1 and GAIN1
pins together and putting a capacitor to ground on the DTO1/
GAIN1 node, the AGC function can be achieved using VGA1.
The same connections can be done to DTO2 and GAIN2 to
achieve the AGC function using VGA2. The MODE pin must
be pulled low for the AGC function. For more information on
the detector squaring cells and the AGC function, refer to the
AGC Operation section. For information concerning the capacitor
value used, refer to the Theory of Operation section.
The ADL5336 can have both a positive and negative gain slope.
This function is controlled by the MODE pin. When the MODE
is pulled high, it puts each VGA into traditional VGA mode, where
the gain slope is positive. When the MODE pin is pulled to
ground, both VGAs have a negative gain slope, which is needed
to obtain an AGC function with either VGA. The MODE
threshold voltage levels are: VMODE > 3 V for the positive gain
slope and VMODE < 2 V for the negative gain slope.
COMMON-MODE BYPASSING
Decouple the two common-mode pins, VCM1 (Pin 1) and VCM2
(Pin 24), of the ADL5336 using low inductance, surface-mount
ceramic capacitors. The evaluation board has 0.1 µF capacitor
values for each of the common-mode pins (see Figure 70).
Pulling the ENBL pin high enables the part and allows for normal
operation. If the ENBL pin is pulled low, then the ADL5336 powers
down and only draws approximately 4 mA of supply current.
ERROR VECTOR MAGNITUDE (EVM)
EVM is a measure used to quantify the performance of a digital
radio transmitter or receiver by measuring the fidelity of the digital
signal transmitted or received. Various imperfections in the link,
such as magnitude and phase imbalance, noise, and distortion,
cause the constellation points to deviate from their ideal locations.
In general, as signal power increases, the distortion components
increase. A typical receiver exhibits the three following distinct
EVM limitations vs. the received input signal power:
•
SERIAL PORT CONNECTIONS
The SPI port of the ADL5336 writes data into the device and
reads data out of it. The SPI port controls maximum VGA gain
levels, output setpoint levels, and VGA2 input selection. It is
recommended to put low-pass RC filtering on the SPI lines to
filter out any high frequency glitches if reading and writing to the
SPI port becomes problematic. Capacitors C26 through C29,
shown in Figure 70, can be populated, along with replacing the
standard 0 Ω jumper resistors (R9 to R12) to make an
appropriate low-pass RC filter network on each SPI line.
•
•
Rev. B | Page 21 of 32
At large enough signal levels, where the distortion
components due to the harmonic nonlinearities in the
device are falling in-band, EVM degrades as signal levels
increase.
At medium signal levels, where the signal chain behaves in
a linear manner and the signal is well above any notable noise
contributions, EVM has a tendency to reach an optimal level
determined dominantly by either the quadrature accuracy
and I/Q gain match of the signal chain or the precision of
the test equipment.
As signal levels decrease, such that noise is a major
contributor, EVM performance vs. the signal level exhibits
a decibel-for-decibel degradation with decreasing signal
level. At these lower signal levels, where noise is the dominant
limitation, decibel EVM is directly proportional to the SNR.
ADL5336
Data Sheet
EFFECT OF CAGC ON EVM
AGC INSENSITIVITY TO MODULATION TYPE
The choice of CAGC is a compromise of averaging time constant,
response time, and carrier leakage. If CAGC is selected to be too
small to speed up the response time, the AGC loop could start
tracking and leveling any amplitude envelope and corrupt the
constellation. The AGC loop bandwidth (BW) is given by the
equation
Given that CAGC is chosen correctly for the symbol rate of the
modulated signal and carrier frequency, EVM should not degrade
much with different modulation types. The four different
modulation types, and how EVM changes with each, are shown in
Figure 65. There is an approximately 4 dB spread across the curves.
All modulated signals were set to 4.5 Msym/sec using a pulse
shaping filter and an alpha of 0.35. The frequency used was
140 MHz. CAGC = 0.1 µF and output setpoints for both VGAs were
250 mV rms. Both VGAs were set to maximum gain codes of 11.
where RAGC is the on-chip equivalent resistance of the loop.
By increasing CAGC (which decreases the loop BW), EVM can be
improved because the signal is outside of the AGC loop BW,
and therefore, the AGC no longer levels the amplitude envelope
of the signal. Figure 64 illustrates this behavior with three different
AGC capacitor values while the ADL5336 VGAs are cascaded.
There is a drastic degradation of EVM when the smaller capacitor
values are used. This example uses a 16 QAM modulated signal
at 4.5 Msym/sec using a pulse shaping filter and an alpha of
0.35. The frequency used was 140 MHz and output setpoints for
both VGAs were 250 mV rms. Both VGAs were set to maximum
gain codes of 11.
0
–10
–15
–30
–35
–40
–50
–65
–55
–45
–35
–25
–15
–5
5
15
25
RF INPUT POWER (dBm)
Figure 65. EVM vs. RF Input Power Over Several Modulation Types
–15
–20
–25
–30
–35
–40
–45
–55
–45
–35
–25
–15
–5
5
15
25
RF INPUT POWER (dBm)
09550-072
EVM (dB)
–25
Figure 64. EVM vs. RF Input Power over Several CAGC Values
Rev. B | Page 22 of 32
09550-070
CAGC = 0.1µF
CAGC = 1000pF
CAGC = 100pF
–10
–50
–65
–20
–45
0
–5
16QAM
256QAM
QPSK
8PSK
–5
EVM (dB)
BWLOOP = 1/(2π × RAGC × CAGC)
Data Sheet
ADL5336
EFFECT OF SETPOINT ON EVM
CASCADED VGA/AGC PERFORMANCE
While in AGC mode, the EVM can degrade depending on the
output setpoint each VGA is set to. There is a strong relationship
between the output setpoint of VGA2 and EVM performance
while the output setpoint of VGA1 is held constant. Conversely,
the EVM does not change much while the output setpoint of the
VGA2 is held constant and the output setpoint of VGA1 is
changed. This behavior can be seen in Figure 66 where several
different setpoints of both VGAs were tested. This example uses
a 16 QAM modulated signal at 4.5 Msym/sec using a pulse
shaping filter and an alpha of 0.35.The frequency used was 140
MHz and CAGC = 0.1 μF. Both VGAs were set to maximum gain
codes of 11.
The ADL5336 is designed for easy cascading of the two VGAs.
Cascading VGAs decreases the overall noise figure by keeping
as much gain as possible before the final gain stage/noise source. A
single X-AMP has constant output referred noise. For an 8 dB
NF amplifier, with 36 dB maximum gain, in a 200 Ω matched
system, output referred noise VN, RTO = 144 nV/√Hz. RTO, the
noise contribution from the source, is the constant source noise
multiplied by the gain (as the gain is reduced, the noise contribution
from the source decreases). Measuring noise figure as 20 × log10
(total noise/noise from source), the dB-for-dB degradation in
NF typical of this architecture can be seen.
0
VGA1 88mV rms, VGA2 250mV rms
VGA1 250mV rms, VGA2 250mV rms
VGA1 707mV rms, VGA2 250mV rms
VGA1 250mV rms, VGA2 88mV rms
VGA1 250mV rms, VGA2 500mV rms
VGA1 250mV rms, VGA2 125mV rms
VGA1 250mV rms, VGA2 176mV rms
–5
–10
–15
EVM (dB)
–20
–25
–30
–35
When VGA1 and VGA2 are cascaded and operating in AGC
mode, setpoint programming affects dynamic range. The noise
measured at the output of VGA1 is relatively constant across
gain, which is a feature common to X-AMP VGAs. However,
measured at the output of VGA2, the noise contribution from
VGA2 is constant, but the noise contribution from VGA1 depends
on the gain of VGA2. For a given overall gain (VGA1 and VGA2),
the gain partitioning between VGA1 and VGA2 controls total
RTO noise and distortion.
–40
–55
–45
–35
–25
–15
–5
5
15
25
RF INPUT POWER (dBm)
09550-071
–45
–50
–65
Figure 66. EVM vs. RF Input Power over Several Setpoints
0
–10
EVM (dB)
–15
2.5
VGA2 88mV rms
VGA2 125mV rms
VGA2 176 mV rms
VGA2 250mV rms
VGA2 500mV rms
VGAIN2 250/88
VGAIN2 250/125
VGAIN2 250/176
VGAIN2 250/250
VGAIN2 250/500
To illustrate, consider the case where both VGAs are programmed
to a maximum gain of 14 dB and the setpoint of VGA2 is 101,
or 353 mV rms. Gain and signal levels can also be looked at
when the setpoint of VGA1 is programmed to 011, 101, and
111, 176 mV rms, 353 mV rms, and 707 mV rms (see Table 9).
2.0
1.5
–20
–25
1.0
–30
VGAIN1/VGAIN2 (V)
–5
When the gain is partitioned into two VGAs, consider 18 dB
each. If each has an 8 dB NF, then each has an RTO noise of
18 nV/√Hz, including the source noise, and 16.5 nV/√Hz,
excluding the source noise. At maximum gain, the total RTO
noise is 145 nV/√Hz. As overall gain is decreased, the gain of
VGA2 is decreased first. When the gain of VGA2 is decreased
by 6 dB, the noise contributions from the source and VGA1
both decrease by 6 dB for an overall RTO noise of the system
that falls to 74 nV/√Hz.
–35
0.5
–40
–45
VGAIN1
–55
–45
–35
–25
–15
–5
5
15
0
25
09550-165
–50
–65
RF INPUT POWER (dBm)
Figure 67. EVM vs. RF Input Power While VGA1 Setpoint Held Constant to
250 mV rms and VGA2 Setpoint Swept; VGA1/VGA2 Gain Code = 11
Table 9. Total Cascaded Output Noise
Vi (mV rms)
176
176
176
AV1 (dB)
0
6
12
VO1 (mV rms)
176
353
707
AV2 (dB)
+6
0
−6
Rev. B | Page 23 of 32
VO (mV rms)
353
353
353
n1
20
10
5
n2
10
10
10
nTOTAL
22.4
14.1
11.2
ADL5336
Data Sheet
In linear terms, the noise figure of the cascaded amplifiers can
be given by
NFCAS = NFVGA1 + (NFVGA2 − 1)/GVGA1
Because both VGAs are X-AMPs, the noise figure of each VGA
degrades dB-for-dB as the gain of each VGA decreases. This is
due to the attenuation ladder on the input that attenuates the
signal before the signal is gained up. If only the gain of the second
VGA is changing, the cascaded noise figure does not change
appreciably because the noise figure of the second VGA is being
divided by the constant gain of the first VGA. When the gain of
VGA2 drops to the minimum and the input signal level is still
decreasing, VGA1 takes over and its gain starts to change. The
cascaded noise figure increases dB-for-dB while the gain of VGA1
decreases.
Figure 68 shows how the OIP3 changes while input power is
varied in AGC mode, which consequently changes the analog
gains of the VGAs. The setpoint of VGA2 is fixed to 100 (or
250 mV rms), and the setpoint of VGA1 is changed from 001
(88 mV rms) to 100 (250 mV rms), and finally, to 111
(707 mV rms).
35
25
30
20
25
15
20
10
LOW TONE, SETPOINT = 001
HIGH TONE, SETPOINT = 001
LOW TONE, SETPOINT = 100 5
HIGH TONE, SETPOINT = 100
LOW TONE, SETPOINT = 111
HIGH TONE, SETPOINT = 111
0
5
10
15
20
25
30
15
While cascading the VGAs, keeping intermodulation distortion
components low is at direct odds with keeping noise figure and
output noise density low. It can be shown that the third-order
intercept of a cascaded system in linear terms is
10
–20
–15
–10
–5
0
OVERALL VOLTAGE GAIN (dB)
Figure 68. OIP3 vs. Overall Voltage Gain over Several Setpoints;
VGA1 Gain Code = 11 and VGA2 Gain Code = 00
P3 = 1/(1/(GVGA2P3_VGA1) + 1/P3_VGA2)
60
Table 10 provides conditions for optimization for the output
noise density, noise figure, and distortion parameters.
SETPOINT = 001
SETPOINT = 100
SETPOINT = 111
50
NOISE FIGURE (dB)
where P3_VGA1 and P3_VGA2 are the third-order intercept points of
each VGA in watts. Thus, when the overall IP3 is the largest
(distortion is the smallest), the gain of VGA2 is at its maximum.
Vice-versa, when the gain of VGA2 is at its minimum, the
overall IP3 is the smallest, and distortion is at its maximum.
OIP3 (dBV)
For each VGA, total RTO noise increases at higher maximumgain settings; therefore, the overall combination of maximum
gain should be minimized while still satisfying all system
requirements with adequate margin.
09550-076
Linearity limits how high the setpoint of VGA1 for a given
system can be programmed. For two equal sinusoidal tones,
353 mV rms corresponds to 1.4 V p-p, whereas 707 mV rms
corresponds to 2.8 V p-p. For a 1.4 V p-p composite output,
IMD3 is approximately −65 dBc; however, for a 2.8 V p-p
composite output, IMD3 is theoretically 12 dB worse at −53 dBc.
When starting from a very small input power, such that neither
VGA has reached their respective setpoints, and the analog gain
of both VGAs is forced to its maximum, the cascaded OIP3 is at
its maximum, while the cascaded noise figure is at its minimum.
As the input power is increased, each VGA keeps its gain at
maximum until its respective setpoint is reached, at which point
the gain of the VGA (whose setpoint has been reached) decreases
to accomodate the increaced input power and thus changes the
cascaded OIP3 and noise figure.
OIP3 (dBm re: 100Ω)
As the setpoint of VGA1 increases, the total output noise decreases.
40
30
20
Table 10. Optimized Conditions
10
VGA2 Gain
Minimum
Maximum1
Maximum
0
–20
–10
0
10
OVERALL VOLTAGE GAIN (dB)
1
Having the gain of VGA2 at maximum does not change the overall noise
figure much due to the noise figure contribution of VGA2 being divided by
the gain of VGA1.
2
IMD levels do not change much over the X-Amp gain range, but best IMD
levels are achieved at high gains.
20
30
09550-077
Output Noise
Noise Figure
IMD/IP3
VGA1 Gain
Minimum
Maximum
Maximum2
Figure 69. Noise Figure vs. Overall Voltage Gain over Several Setpoints;
VGA1 Gain Code = 11 and VGA2 Gain Code = 00
Figure 69 shows how the NF changes while the input power is
varied in AGC, which again, consequently changes the analog
gains of the VGAs. The setpoint of VGA2 is still fixed to 100
(250 mV rms), and the changes made to the setpoint of VGA1
is the same as before.
Rev. B | Page 24 of 32
Data Sheet
ADL5336
EVALUATION BOARD LAYOUT
An evaluation board is available for testing the ADL5336. The evaluation board schematic is shown in Figure 70. Table 11 provides the
component values and suggestions for modifying the component values for the various modes of operation.
VPOSD
VPOS
INPUT2
L2
33µH
VPOS
DIG_VPOS
6
4
T5
R4
open
1
4
R13
open
R3
open
2
OUTPUT1
C14
0.1µF
3
T4
6
INPUT1
28
27
26
25
IP2B
IM2B
OPM1
29
COM
30
IP2A
31
IM2A
32
COM
C15
0.1µF
C24
0.1µF
VCM2
C25
0.1µF
1
VCM1
VCM2
24
2
VPOS
VPOS
23
C17
VPOS
C3
0.1µF
T1
6
1
OPP1
VCM1
C5
0.1µF
INPUT3
2
R15
open
C7
0.1µF
4
3
C9
0.1µF
C22
0.1µF
C19
0.1µF
0.1µF
1
R7
24.9Ω
R5
37.4Ω
T3
3
INP1
OPP2
22
5
1
4
INM1
OPM2
21
4
3
5
VPOS
VPOS
20
COM
19
2
MODE
8
ENBL
20
0.1µF
R6
37.4Ω
OUTPUT2
R8
24.9Ω
SDO 18
DATA
9
P2
VPOS
C18
0.1µF
10
11
12
R10
17
SDO
13
14
15
CLK
COM
7
GAIN1
VPOS
6
LE
C21
0.1µF
ADL5336
VPSD
C6
0.1µF
COMD
VPOS
DTO2
C4
0.1µF
GAIN2
3
DTO1
4
COM
C10
0.1µF
C8
0.1µF
T2
6
C11
0.1µF
C2
10µF
L1
33µH
COMD
2
C23
0.1µF
R14
open
C1
10µF
1
3
C29
0Ω
open
16
C28
open
VPOS
R11
0Ω
C16
P5
GAIN1
0.1µF
DATA
R1
0Ω
P3
C27
Legend
–
Net Name
–
Test Point
–
SMA Input/Output
–
Digital ground
–
Analog ground
–
Jumper
R9
0Ω
open
C12
0.1µF
CLK
C26
open
P4
GAIN2
R12
0Ω
R2
0Ω
LE
C13
09550-081
0.1µF
Figure 70. Evaluation Board Schematic
Rev. B | Page 25 of 32
ADL5336
Data Sheet
Y1
24 MHz
3
1
C51
22pF
C54
22pF
4
2
3V3_USB
3V3_USB
R62
100kΩ
R64
100kΩ
C45
0.1µF
C48
10pF
50
49
48
47
46
45
44
43
PD4_FD12
PD3_FD11
PD2_FD10
PD1_FD9
PD0_FD8
WAKEUP
VCC
RDY1_SLWR
51
PD5_FD13
CLKOUT
RDY0_SLRD
2
52
PD6_FD14
GND
1
53
GND
54
PD7_FD15
55
VCC
C37
0.1µF
56
GND
3 AVCC
C49
0.1µF
RESET_N 42
41
PA7_FLAGD_SCLS_N 40
4
XTALOUT
5
XTALIN
6
AGND
7
AVCC
PA6_PKTEND 39
5V_USB
P1
1
2
3V3_USB
3
4
PA5_FIFOARD1 38
PA4_FIFOARD0 37
CY7C68013A-56LTXC
U4
8 DPLUS
5
9
G1
LE
PA3_WU2 36
DMINUS
PA2_SLOE 35
CLK
PA1_INT1_N 34
DATA
G2
G4
3V3_USB
SDO
PA0_INT0_N 33
10 AGND
G3
11 VCC
3V3_USB
VCC 32
12 GND
CTL2_FLAGC 31
13 IFCLK
SCL
SDA
VCC
PB0_FD0
PB1_FD1
PB2_FD2
PB3_FD3
PB4_FD4
PB5_FD5
PB6_FD6
PB7_FD7
GND
VCC
GND
CTL1_FLAGB 30
15
16
17
18
19
20
21
22
23
24
25
26
27
28
14 RESERVED
R61
2kΩ
CTL0_FLAGA 29
CR2
3V3_USB
3V3_USB
24LC64-I_SN
U2
3V3_USB
1
A0
SDA 5
2
A1
SCL 6
A2
WC_N 7
3
4 GND
VCC
8
R59
2kΩ
C38
10pF
C39
0.1µF
ADP3334
U3
R60
2kΩ
3V3_USB
C52
1.0µF
3V3_USB
R70
140kΩ
C50
1000pF
R69
78.7kΩ
1
OUT1
IN2
8
2
OUT2
IN1
7
3
FB
SD 6
4
NC
GND
5V_USB
C47
1.0µF
R65
2kΩ
5
CR1
3V3_USB
DGND
C41
0.1µF
C42
0.1µF
C35
0.1µF
C36
0.1µF
C44
0.1µF
C46
0.1µF
09550-084
C40
0.1µF
Figure 71. Evaluation Board Schematic USB
Rev. B | Page 26 of 32
ADL5336
09550-083
Data Sheet
09550-082
Figure 72. Silkscreen Top
Figure 73. Silkscreen Bottom
Rev. B | Page 27 of 32
ADL5336
Data Sheet
BILL OF MATERIALS (BOM)
Table 11. Evaluation Board Configuration Options
Components
C1, C2, C5, C6, C7, C16,
C17, C18, C25, L1, L2
Function
Power supply and ground decoupling. Nominal supply
decoupling consists of 0.1 µF capacitor to ground.
C3, C4, C21, T1
VGA1 input interface. The balun T1 has a 4:1 impedance ratio that
transforms a single-ended signal in a 50 Ω system into a
differential signal in a 200 Ω system. C3 and C4 provide ac
coupling into VGA1, and C21 provides an ac ground for the balun.
VGA2 input interface. The T4 and T5 baluns have 4:1 impedance
ratios that transform single-ended signals in a 50 Ω system into
differential signals in a 200 Ω system. The user has a choice of
either Input A or Input B, which is set by Bit B6 in the internal
register (see the register map in Table 5). C11, C14, C15, and C23
provide ac coupling into VGA2, and C10 and C24 provide an ac
ground for the baluns. R3, R4, and R13 are left open by default. AC
ground can be achieve by placing 0 Ω jumpers at R3 and R4. A
0 Ω jumper can be installed at R13 to drive Input B of VGA2 single
ended. Note that R4 must be open and R3 must have a 0 Ω
jumper installed.
VGA1 output interface. The T2 balun has a 4:1 impedance ratio
that transforms a differential signal in a 200 Ω system into a
single-ended signal in a 50 Ω system. C8 and C9 provide ac
coupling out of VGA1, and C22 provides an ac ground for the
balun. R14 and R15 can be made 0 Ω and dc-couple the output of
VGA1 into the input of VGA2 in cascading applications.
VGA2 output interface. The transmission line transformer, T3, has
a 1:1 impedance ratio that transforms a differential signal to a
single-ended signal. The 50 Ω impedance is the same on both the
primary and secondary side balun. C19 and C20 provide ac
coupling out of VGA2. R5, R6, R7, and R8 raise the impedance that
the output of VGA2 sees to 100 Ω differential.
Detector 1 interface. R1 serves as a 0 Ω jumper to connect the
integrating capacitor, C12, that is needed when VGA1 is being
used in AGC mode.
Detector 2 interface. R2 serves as a 0 Ω jumper to connect the
integrating capacitor, C13, that is needed when VGA2 is being
used in AGC mode.
Enable interface. The ADL5336 is powered up by applying a logic
high voltage to the ENBL pin. Jumper P3 is connected to VPOS.
MODE interface. The MODE pin must be pulled to a logic high to
be used in VGA mode. If AGC mode is desired, a logic low must be
applied to the MODE pin. The P2 jumper must be connected to
either VPOS (logic high) or ground (logic low).
Serial control interface. The digital interface sets the VGA1
setpoint, VGA2 setpoint, VGA2 input selection, VGA1 maximum
gain, and the VGA2 maximum gain of the device using the serial
interface lines CLK, LE, DATA, and SDO. RC filter networks are
provided on CLK and LE lines to filter the PC signals (possibly on
all the lines). CLK, DATA, SDO, and LE signals can be observed via
SMB connectors for debug purposes.
Analog VGA1 gain control. The range of the GAIN1 pin is from 0 V
to 1 V, creating a gain scaling of 35 mV/dB.
Analog VGA2 gain control. The range of the GAIN2 pin is from 0 V
to 1 V, creating a gain scaling of 35 mV/dB.
C10, C11, C14, C15, C23,
C24, R3, R4, R13, T4, T5
C8, C9, C22, R14, R15, T2
C19, C20, R5, R6, R7, R8, T3
R1, C12
R2, C13
P3
P2
R9, R10, R11, R12, C26,
C27, C28, C29, P1
P5
P4
Rev. B | Page 28 of 32
Default Conditions
C1, C2 = 10 µF (0805),
C5, C6, C7, C16, C17 = 0.1 µF (0402),
C18, C25 = 0.1 µF (0402),
L1, L2 = 33 μH (0805)
C3, C4, C21 = 0.1 µF (0402),
T1 = Mini-Circuits TC4-1W
C10, C11, C14 = 0.1 µF (0402),
C15, C23, C24 = 0.1 µF (0402),
R3, R4, R13 = open (0402),
T4, T5 = Mini-Circuits TC4-1W
C8, C9, C22 = 0.1 µF (0402),
R14, R15 = open (0402),
T2 = Mini-Circuits TC4-1W
C19, C20 = 0.1 µF (0402),
R5, R6 = 37.4 Ω (0402),
R7, R8 = 24.9 Ω (0402),
T3 = M/A-COM ETC1-1-13
R1 = 0 Ω (0402),
C12 = 0.1 µF (0402)
R2 = 0 Ω (0402),
C13 = 0.1 µF (0402)
P3 = installed for enable
P2 = installed
R9, R10, R11, R12 = 0 Ω (0402),
C26, C27, C28, C29 = open (0402)
P5 installed
P4 installed
Data Sheet
ADL5336
Components
U2, U3, U4, P1
Function
Cypress microcontroller, EEPROM and LDO
C35, C36, C40, C41, C42,
C44, C46
C37, C45, C38, C39, C48,
C49, R59, R60, R61, R62,
R64, CR2
3.3 V supply decoupling; several capacitors are used for
decoupling on the 3.3 V supply
Cypress and EEPROM components
C47, C50, C52, R65, R69,
R70, CR1
LDO components
Y1, C51, C54
Crystal oscillator and components. 24 MHz crystal oscillator
EVALUATION BOARD CONTROL SOFTWARE
The ADL5336 evaluation board is controlled through the parallel
port on a PC. The parallel port is programmed via the ADL5336
evaluation software. This software controls the following:
•
•
•
The setpoints of VGA1 and VGA2
The maximum gains of VGA1 and VGA2
The input control switch of VGA2
Default Conditions
U2 = MICROCHIP MICRO24LC64
U3 = Analog Devices, Inc., ADP3334ACPZ
U4 = Cypress Semiconductor
CY7C68013A-56LTXC
P1 = Mini USB Connector
C35, C36, C40, C41, C42, C44, C46 =
0.1 µF (0402)
C38, C48 = 10 pF (0402)
C37, C39, C45, C49 = 0.1 µF (0402)
R59, R60, R61 = 2 kΩ (0402)
R62, R64 = 100 kΩ (0402)
CR2 = ROHM SML-21OMTT86
C47, C52 = 1 µF (0402)
C50 = 1000 pF (0402)
R65 = 2 kΩ (0402)
R69 = 78.7 kΩ (0402)
R70 = 140 kΩ (0402)
CR1 = ROHM SML-21OMTT86
Y1 = NDK NX3225SA-24MHz
C51, C54 = 22 pF (0402)
On VGA2, the user can switch to either Input A or Input B by
selecting the slider switch, VGA 2 Switch.
Because the speed of the parallel port varies from PC to PC, the
Clock Stretch function can be used to change the effective frequency
of the CLK line. The CLK line has a scalar range from 1 to 10;
10 is the fastest speed, and 1 is the slowest.
For information about the register map, see Table 5, Table 6,
Table 7, and Table 8. For information about SPI port timing and
control, see Figure 2 and Figure 3.
After the software is downloaded and installed, start the basic user
interface to program the maximum gains, setpoints, and the input
of VGA2, see Figure 74.
To program the setpoints of each VGA, click on the respective pulldown menu of the desired VGA under RMS Out (mVrms/dBV),
select the desired setpoint, and click Write Bits.
When the user clicks Write Bits, a write operation executes,
immediately followed by a read operation. The updated
information is displayed in the VGA1 Current State and VGA2
Current State fields. The gain displayed does not represent the
analog VGA gain, only the digital maximum gain.
Rev. B | Page 29 of 32
09550-084
To program the maximum gain of each VGA, click on the respective
pull-down menu of the desired VGA under the VGA 1 Max
Gain (dB)/VGA 2 Max Gain (dB), select the desired maximum
gain, and click Write Bits.
Figure 74. ADL5336 Software Screen Capture
ADL5336
Data Sheet
OUTLINE DIMENSIONS
5.00
BSC SQ
0.60 MAX
0.60 MAX
25
32
1
24
0.50
BSC
3.25
3.10 SQ
2.95
EXPOSED
PAD
17
TOP VIEW
12° MAX
1.00
0.85
0.80
SEATING
PLANE
0.80 MAX
0.65 TYP
0.30
0.25
0.18
0.50
0.40
0.30
0.05 MAX
0.02 NOM
COPLANARITY
0.08
0.20 REF
8
16
9
BOTTOM VIEW
0.25 MIN
3.50 REF
FOR PROPER CONNECTION OF
THE EXPOSED PAD, REFER TO
THE PIN CONFIGURATION AND
FUNCTION DESCRIPTIONS
SECTION OF THIS DATA SHEET.
COMPLIANT TO JEDEC STANDARDS MO-220-VHHD-2
05-25-2011-A
4.75
BSC SQ
PIN 1
INDICATOR
PIN 1
INDICATOR
Figure 75. 32-Lead Lead Frame Chip Scale Package [LFCSP_VQ]
5 mm × 5 mm Body, Very Thin Quad
(CP-32-2)
Dimensions shown in millimeters
ORDERING GUIDE
Model1
ADL5336ACPZ-R7
ADL5336-EVALZ
1
Temperature Range
−40°C to +85°C
Package Description
32-Lead LFCSP_VQ, 7” Tape and Reel
Evaluation Board
Z = RoHS Compliant Part.
Rev. B | Page 30 of 32
Package Option
CP-32-2
Data Sheet
ADL5336
NOTES
Rev. B | Page 31 of 32
ADL5336
Data Sheet
NOTES
©2011–2012 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D09550-0-2/12(B)
Rev. B | Page 32 of 32